mirror of
https://github.com/rzzzwilson/pymlac.git
synced 2025-06-10 09:32:41 +00:00
Main CPU and test moved to a class
This commit is contained in:
Ross Wilson
1439
pymlac/MainCPU.py
1439
pymlac/MainCPU.py
File diff suppressed because it is too large
Load Diff
@@ -14,7 +14,7 @@ where <filename> is a file of test instructions and
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# We implement a small interpreter to test the CPU. The test code is read in
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# from a file:
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#
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# # LAW
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# # LAW
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# setreg ac 012345; setreg l 1; setreg pc 0100; setmem 0100 [LAW 0]; RUN; checkcycles 1; checkreg pc 0101; checkreg ac 0
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# setreg ac 012345; setreg l 0; setmem 0100 [LAW 0]; RUN 0100
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# checkcycles 1; checkreg pc 0101; checkreg ac 0
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@@ -70,423 +70,387 @@ import Memory
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import log
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log = log.Log('test_CPU.log', log.Log.DEBUG)
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# fake a Display instance
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DisplayState = False
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class TestCPU(object):
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# temporary assembler file and listfile prefix
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AsmFilename = '_#ASM#_'
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# number of cycles used in previous instruction
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UsedCycles = 0
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def __init__(self):
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"""Initialize the test."""
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# register+value explicitly set by test
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RegValues = {}
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pass
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# memory address+value explicitly set by test
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MemValues = {}
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def assemble(self, addr, opcode):
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"""Assemble a single instruction, return opcode."""
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# memory value all explicitly set to (shouldn't change)
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MemAllValue = None
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# create ASM file with instruction
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with open(self.AsmFilename+'.asm', 'wb') as fd:
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fd.write('\torg\t%07o\n' % addr)
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fd.write('\t%s\n' % opcode[1:-1])
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fd.write('\tend\n')
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# registers value all explicitly set to (shouldn't change)
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RegAllValue = None
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# now assemble file
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os.system('../iasm/iasm -l %s.lst %s.asm' % (self.AsmFilename, self.AsmFilename))
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# temporary assembler file and listfile prefix
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AsmFilename = '_#ASM#_'
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# read the listing file to get assembled opcode (second line)
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with open(self.AsmFilename+'.lst', 'rb') as fd:
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lines = fd.readlines()
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line = lines[1]
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(opcode, _) = line.split(None, 1)
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return int(opcode, base=8)
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def assemble(addr, opcode):
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"""Assemble a single instruction, return opcode."""
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def setreg(self, name, value):
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"""Set register to a value.
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# create ASM file with instruction
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with open(AsmFilename+'.asm', 'wb') as fd:
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fd.write('\torg\t%07o\n' % addr)
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fd.write('\t%s\n' % opcode[1:-1])
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fd.write('\tend\n')
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Remember value to check later.
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"""
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# now assemble file
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os.system('../iasm/iasm -l %s.lst %s.asm' % (AsmFilename, AsmFilename))
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self.reg_values[name] = value
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# read the listing file to get assembled opcode (second line)
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with open(AsmFilename+'.lst', 'rb') as fd:
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lines = fd.readlines()
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line = lines[1]
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(opcode, _) = line.split(None, 1)
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return int(opcode, base=8)
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def setreg(name, value):
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"""Set register to a value.
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Remember value to check later.
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"""
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global RegValues
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RegValues[name] = value
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if name == 'ac':
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MainCPU.AC = value
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elif name == 'l':
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MainCPU.L = value & 1
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elif name == 'pc':
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MainCPU.PC = value
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elif name == 'ds':
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MainCPU.DS = value
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else:
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raise Exception('setreg: bad register name: %s' % name)
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def setmem(addr, value):
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"""Set memory location to a value."""
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if isinstance(value, basestring):
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log.debug('setmem: addr=%s, value=%s' % (oct(addr), value))
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else:
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log.debug('setmem: addr=%s, value=%s' % (oct(addr), oct(value)))
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global MemValues
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# check if we must assemble var2
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if isinstance(value, basestring) and value[0] == '[':
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# assemble an instruction
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value = assemble(addr, value)
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log.debug('setmem: assembled opcode=%07o' % value)
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MemValues[addr] = value
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log.debug('setmem: After, MemValues=%s' % str(MemValues))
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Memory.put(value, addr, False)
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log.debug('setmem: After, Memory at %07o is %07o' % (addr, Memory.fetch(addr, False)))
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def allmem(value):
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"""Set all of memory to a value.
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Remember value to check later.
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"""
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global MemAllValue
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log.debug('allmem: setting memory to %07o' % value)
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MemAllValue = value
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for mem in range(MEMORY_SIZE):
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Memory.put(value, mem, False)
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def allreg(value):
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"""Set all registers to a value."""
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global RegAllValue
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RegAllValue = value
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MainCPU.AC = value
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MainCPU.L = value & 1
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MainCPU.PC = value
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MainCPU.DS = value
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def check_all_mem():
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"""Check memory for unwanted changes."""
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result = []
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for mem in range(MEMORY_SIZE):
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value = Memory.fetch(mem, False)
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if mem in MemValues:
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if value != MemValues[mem]:
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result.append('Memory at %07o changed, is %07o, should be %07o'
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% (mem, value, MemValues[mem]))
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if name == 'ac':
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self.cpu.AC = value
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elif name == 'l':
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self.cpu.L = value & 1
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elif name == 'pc':
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self.cpu.PC = value
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elif name == 'ds':
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self.cpu.DS = value
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else:
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if value != MemAllValue:
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result.append('Memory at %07o changed, is %07o, should be %07o'
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% (mem, value, MemAllValue))
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raise Exception('setreg: bad register name: %s' % name)
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def check_all_regs():
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"""Check registers for unwanted changes."""
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def setmem(self, addr, value):
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"""Set memory location to a value."""
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result = []
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if 'ac' in RegValues:
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if MainCPU.AC != RegValues['ac']:
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result.append('AC changed, is %07o, should be %07o'
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% (MainCPU.AC, RegValues['ac']))
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else:
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if MainCPU.AC != RegAllValue:
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result.append('AC changed, is %07o, should be %07o'
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% (MainCPU.AC, RegAllValue))
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if 'l' in RegValues:
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if MainCPU.L != RegValues['l']:
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result.append('L changed, is %02o, should be %02o'
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% (MainCPU.L, RegValues['l']))
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else:
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if MainCPU.L != RegAllValue & 1:
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result.append('L changed, is %02o, should be %02o'
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% (MainCPU.L, RegAllValue & 1))
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if 'pc' in RegValues:
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if MainCPU.PC != RegValues['pc']:
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result.append('PC changed, is %07o, should be %07o'
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% (MainCPU.PC, RegValues['pc']))
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else:
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if MainCPU.PC != RegAllValue:
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result.append('PC changed, is %07o, should be %07o'
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% (MainCPU.PC, RegAllValue))
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if 'ds' in RegValues:
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if MainCPU.DS != RegValues['ds']:
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result.append('DS changed, is %07o, should be %07o'
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% (MainCPU.DS, RegValues['ds']))
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else:
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if MainCPU.DS != RegAllValue:
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result.append('DS changed, is %07o, should be %07o'
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% (MainCPU.DS, RegAllValue))
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return result
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def checkreg(reg, value):
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"""Check register is as it should be."""
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global RegValues
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if reg == 'ac':
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RegValues[reg] = MainCPU.AC
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if MainCPU.AC != value:
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return 'AC wrong, is %07o, should be %07o' % (MainCPU.AC, value)
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elif reg == 'l':
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RegValues[reg] = MainCPU.L
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if MainCPU.L != value:
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return 'L wrong, is %02o, should be %02o' % (MainCPU.L, value)
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elif reg == 'pc':
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RegValues[reg] = MainCPU.PC
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if MainCPU.PC != value:
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return 'PC wrong, is %07o, should be %07o' % (MainCPU.PC, value)
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elif reg == 'ds':
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RegValues[reg] = MainCPU.DS
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if MainCPU.DS != value:
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return 'DS wrong, is %07o, should be %07o' % (MainCPU.DS, value)
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else:
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raise Exception('checkreg: bad register name: %s' % name)
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def checkmem(addr, value):
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"""Check a memory location is as it should be."""
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global MemValues
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MemValues[addr] = value
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log.debug('checkmem: After, MemValues=%s' % str(MemValues))
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memvalue = Memory.fetch(addr, False)
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if memvalue != value:
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return 'Memory wrong at address %07o, is %07o, should be %07o' % (addr, memvalue, value)
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def checkcycles(cycles, var2=None):
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"""Check that opcode cycles used is correct."""
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if cycles != UsedCycles:
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return 'Opcode used %d cycles, expected %d' % (UsedCycles, cycles)
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def run(addr, var2):
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"""Execute instruction."""
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global UsedCycles
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if addr is not None:
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# force PC to given address
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setreg('pc', addr)
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UsedCycles = MainCPU.execute_one_instruction()
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def checkrun(state, var2):
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"""Check CPU run state is as desired."""
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if str(MainCPU.running).lower() != state:
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return 'CPU run state is %s, should be %s' % (str(MainCPU.running), str(state))
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def setd(state, var2):
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"""Set display state."""
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global DisplayState
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if state == 'on':
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DisplayState = True
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elif state == 'off':
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DisplayState = False
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else:
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raise Exception('setd: bad state: %s' % str(state))
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def checkd(state, var2):
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"""Check display state is as expected."""
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global DisplayState
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if state == 'on' and DisplayState is not True:
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return 'DCPU run state is %s, should be True' % str(DisplayState)
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if state == 'off' and DisplayState is True:
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return 'DCPU run state is %s, should be False' % str(DisplayState)
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def debug_operation(op, var1, var2):
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"""Write operation to log file."""
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if var1:
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if var2:
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log.debug('Operation: %s %s %s' % (op, var1, var2))
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if isinstance(value, basestring):
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log.debug('setmem: addr=%s, value=%s' % (oct(addr), value))
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else:
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log.debug('Operation: %s %s' % (op, var1))
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else:
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log.debug('Operation: %s' % op)
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log.debug('setmem: addr=%s, value=%s' % (oct(addr), oct(value)))
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def execute(test):
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"""Execute test string in 'test'."""
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# check if we must assemble var2
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if isinstance(value, basestring) and value[0] == '[':
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# assemble an instruction
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value = self.assemble(addr, value)
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log.debug('setmem: assembled opcode=%07o' % value)
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global RegValues, MemValues
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global RegAllValue, MemAllValue
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global DisplayState
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self.mem_values[addr] = value
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log.debug('setmem: After, MemValues=%s' % str(self.mem_values))
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# set globals
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RegValues = {}
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MemValues = {}
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RegAllValue = {}
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MemAllValue = {}
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self.memory.put(value, addr, False)
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log.debug('setmem: After, Memory at %07o is %07o' % (addr, self.memory.fetch(addr, False)))
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result = []
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def allmem(self, value):
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"""Set all of memory to a value.
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MainCPU.init()
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MainCPU.running = True
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DisplayState = False
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Memory.init()
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Remember value to check later.
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"""
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# clear memory and registers to 0 first
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allmem(0)
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allreg(0)
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log.debug('allmem: setting memory to %07o' % value)
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# interpret the test instructions
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instructions = test.split(';')
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for op in instructions:
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fields = op.split(None, 2)
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op = fields[0].lower()
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try:
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var1 = fields[1].lower()
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except IndexError:
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var1 = None
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try:
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var2 = fields[2].lower()
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except IndexError:
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var2 = None
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self.mem_all_value = value
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debug_operation(op, var1, var2)
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for mem in range(MEMORY_SIZE):
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self.memory.put(value, mem, False)
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# change var strings into numeric values
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if var1 and var1[0] in '0123456789':
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if var1[0] == '0':
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var1 = int(var1, base=8)
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def allreg(self, value):
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"""Set all registers to a value."""
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self.reg_all_value = value
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self.cpu.AC = value
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self.cpu.L = value & 1
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self.cpu.PC = value
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self.cpu.DS = value
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def check_all_mem(self):
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"""Check memory for unwanted changes."""
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result = []
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for mem in range(MEMORY_SIZE):
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value = self.memory.fetch(mem, False)
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if mem in self.mem_values:
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if value != self.mem_values[mem]:
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result.append('Memory at %07o changed, is %07o, should be %07o'
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% (mem, value, self.mem_values[mem]))
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else:
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var1 = int(var1)
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var1 &= 0177777
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if value != self.mem_all_value:
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result.append('Memory at %07o changed, is %07o, should be %07o'
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% (mem, value, self.mem_all_value))
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if var2 and var2[0] in '0123456789':
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if var2[0] == '0':
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var2 = int(var2, base=8)
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else:
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var2 = int(var2)
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var2 &= 0177777
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def check_all_regs(self):
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"""Check registers for unwanted changes."""
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if op == 'setreg':
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r = setreg(var1, var2)
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elif op == 'setmem':
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r = setmem(var1, var2)
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elif op == 'run':
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r = run(var1, var2)
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elif op == 'checkcycles':
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r = checkcycles(var1, var2)
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elif op == 'checkreg':
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r = checkreg(var1, var2)
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elif op == 'checkmem':
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r = checkmem(var1, var2)
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elif op == 'allreg':
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r = allreg(var1, var2)
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elif op == 'allmem':
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r = allmem(var1, var2)
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elif op == 'checkrun':
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r = checkrun(var1, var2)
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elif op == 'setd':
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r = setd(var1, var2)
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elif op == 'checkd':
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r = checkd(var1, var2)
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result = []
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if 'ac' in self.reg_values:
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if self.cpu.AC != self.reg_values['ac']:
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result.append('AC changed, is %07o, should be %07o'
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% (self.cpu.AC, self.reg_values['ac']))
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else:
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raise Exception("Unrecognized operation '%s' in: %s" % (op, test))
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if self.cpu.AC != self.reg_all_value:
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result.append('AC changed, is %07o, should be %07o'
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% (self.cpu.AC, self.reg_all_value))
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if r is not None:
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if 'l' in self.reg_values:
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if self.cpu.L != self.reg_values['l']:
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result.append('L changed, is %02o, should be %02o'
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% (self.cpu.L, self.reg_values['l']))
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else:
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if self.cpu.L != self.reg_all_value & 1:
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result.append('L changed, is %02o, should be %02o'
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% (self.cpu.L, self.reg_all_value & 1))
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if 'pc' in self.reg_values:
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if self.cpu.PC != self.reg_values['pc']:
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result.append('PC changed, is %07o, should be %07o'
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% (self.cpu.PC, self.reg_values['pc']))
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else:
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if self.cpu.PC != self.reg_all_value:
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result.append('PC changed, is %07o, should be %07o'
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% (self.cpu.PC, self.reg_all_value))
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if 'ds' in self.reg_values:
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if self.cpu.DS != self.reg_values['ds']:
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result.append('DS changed, is %07o, should be %07o'
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% (self.cpu.DS, self.reg_values['ds']))
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else:
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if self.cpu.DS != self.reg_all_value:
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result.append('DS changed, is %07o, should be %07o'
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% (self.cpu.DS, self.reg_all_value))
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return result
|
||||
|
||||
def checkreg(self, reg, value):
|
||||
"""Check register is as it should be."""
|
||||
|
||||
if reg == 'ac':
|
||||
self.reg_values[reg] = self.cpu.AC
|
||||
if self.cpu.AC != value:
|
||||
return 'AC wrong, is %07o, should be %07o' % (self.cpu.AC, value)
|
||||
elif reg == 'l':
|
||||
self.reg_values[reg] = self.cpu.L
|
||||
if self.cpu.L != value:
|
||||
return 'L wrong, is %02o, should be %02o' % (self.cpu.L, value)
|
||||
elif reg == 'pc':
|
||||
self.reg_values[reg] = self.cpu.PC
|
||||
if self.cpu.PC != value:
|
||||
return 'PC wrong, is %07o, should be %07o' % (self.cpu.PC, value)
|
||||
elif reg == 'ds':
|
||||
self.reg_values[reg] = self.cpu.DS
|
||||
if self.cpu.DS != value:
|
||||
return 'DS wrong, is %07o, should be %07o' % (self.cpu.DS, value)
|
||||
else:
|
||||
raise Exception('checkreg: bad register name: %s' % name)
|
||||
|
||||
def checkmem(self, addr, value):
|
||||
"""Check a memory location is as it should be."""
|
||||
|
||||
self.mem_values[addr] = value
|
||||
log.debug('checkmem: After, MemValues=%s' % str(self.mem_values))
|
||||
|
||||
memvalue = self.memory.fetch(addr, False)
|
||||
if memvalue != value:
|
||||
return 'Memory wrong at address %07o, is %07o, should be %07o' % (addr, memvalue, value)
|
||||
|
||||
def checkcycles(self, cycles, var2=None):
|
||||
"""Check that opcode cycles used is correct."""
|
||||
|
||||
if cycles != self.used_cycles:
|
||||
return 'Opcode used %d cycles, expected %d' % (self.used_cycles, cycles)
|
||||
|
||||
def run(self, addr, var2):
|
||||
"""Execute instruction."""
|
||||
|
||||
if addr is not None:
|
||||
# force PC to given address
|
||||
self.setreg('pc', addr)
|
||||
|
||||
self.used_cycles = self.cpu.execute_one_instruction()
|
||||
|
||||
def checkrun(self, state, var2):
|
||||
"""Check CPU run state is as desired."""
|
||||
|
||||
if str(self.cpu.running).lower() != state:
|
||||
return 'CPU run state is %s, should be %s' % (str(self.cpu.running), str(state))
|
||||
|
||||
def setd(self, state, var2):
|
||||
"""Set display state."""
|
||||
|
||||
if state == 'on':
|
||||
self.display_state = True
|
||||
elif state == 'off':
|
||||
self.display_state = False
|
||||
else:
|
||||
raise Exception('setd: bad state: %s' % str(state))
|
||||
|
||||
def checkd(self, state, var2):
|
||||
"""Check display state is as expected."""
|
||||
|
||||
if state == 'on' and self.display_state is not True:
|
||||
return 'DCPU run state is %s, should be True' % str(self.display_state)
|
||||
if state == 'off' and self.display_state is True:
|
||||
return 'DCPU run state is %s, should be False' % str(self.display_state)
|
||||
|
||||
def debug_operation(self, op, var1, var2):
|
||||
"""Write operation to log file."""
|
||||
|
||||
if var1:
|
||||
if var2:
|
||||
log.debug('Operation: %s %s %s' % (op, var1, var2))
|
||||
else:
|
||||
log.debug('Operation: %s %s' % (op, var1))
|
||||
else:
|
||||
log.debug('Operation: %s' % op)
|
||||
|
||||
def execute(self, test):
|
||||
"""Execute test string in 'test'."""
|
||||
|
||||
# set globals
|
||||
self.reg_values = {}
|
||||
self.mem_values = {}
|
||||
self.reg_all_value = {}
|
||||
self.mem_all_value = {}
|
||||
|
||||
result = []
|
||||
|
||||
self.memory = Memory.Memory()
|
||||
#self.cpu = MainCPU.MainCPU(memory, display, displaycpu, kbd, ttyin, ttyout, ptp, ptr)
|
||||
self.cpu = MainCPU.MainCPU(self.memory, None, None, None, None, None, None, None)
|
||||
self.cpu.running = True
|
||||
self.display_state = False
|
||||
|
||||
# clear memory and registers to 0 first
|
||||
self.allmem(0)
|
||||
self.allreg(0)
|
||||
|
||||
# interpret the test instructions
|
||||
instructions = test.split(';')
|
||||
for op in instructions:
|
||||
fields = op.split(None, 2)
|
||||
op = fields[0].lower()
|
||||
try:
|
||||
var1 = fields[1].lower()
|
||||
except IndexError:
|
||||
var1 = None
|
||||
try:
|
||||
var2 = fields[2].lower()
|
||||
except IndexError:
|
||||
var2 = None
|
||||
|
||||
self.debug_operation(op, var1, var2)
|
||||
|
||||
# change var strings into numeric values
|
||||
if var1 and var1[0] in '0123456789':
|
||||
if var1[0] == '0':
|
||||
var1 = int(var1, base=8)
|
||||
else:
|
||||
var1 = int(var1)
|
||||
var1 &= 0177777
|
||||
|
||||
if var2 and var2[0] in '0123456789':
|
||||
if var2[0] == '0':
|
||||
var2 = int(var2, base=8)
|
||||
else:
|
||||
var2 = int(var2)
|
||||
var2 &= 0177777
|
||||
|
||||
if op == 'setreg':
|
||||
r = self.setreg(var1, var2)
|
||||
elif op == 'setmem':
|
||||
r = self.setmem(var1, var2)
|
||||
elif op == 'run':
|
||||
r = self.run(var1, var2)
|
||||
elif op == 'checkcycles':
|
||||
r = self.checkcycles(var1, var2)
|
||||
elif op == 'checkreg':
|
||||
r = self.checkreg(var1, var2)
|
||||
elif op == 'checkmem':
|
||||
r = self.checkmem(var1, var2)
|
||||
elif op == 'allreg':
|
||||
r = self.allreg(var1, var2)
|
||||
elif op == 'allmem':
|
||||
r = self.allmem(var1, var2)
|
||||
elif op == 'checkrun':
|
||||
r = self.checkrun(var1, var2)
|
||||
elif op == 'setd':
|
||||
r = self.setd(var1, var2)
|
||||
elif op == 'checkd':
|
||||
r = self.checkd(var1, var2)
|
||||
else:
|
||||
raise Exception("Unrecognized operation '%s' in: %s" % (op, test))
|
||||
|
||||
if r is not None:
|
||||
result.append(r)
|
||||
|
||||
# now check all memory and regs for changes
|
||||
r = self.check_all_mem()
|
||||
if r:
|
||||
result.append(r)
|
||||
|
||||
r = self.check_all_regs()
|
||||
if r:
|
||||
result.extend(r)
|
||||
|
||||
# now check all memory and regs for changes
|
||||
r = check_all_mem()
|
||||
if r:
|
||||
result.append(r)
|
||||
if result:
|
||||
print(test)
|
||||
print('\t' + '\n\t'.join(result))
|
||||
|
||||
r = check_all_regs()
|
||||
if r:
|
||||
result.extend(r)
|
||||
self.memdump('core.txt', 0, 0200)
|
||||
|
||||
if result:
|
||||
print(test)
|
||||
print('\t' + '\n\t'.join(result))
|
||||
def memdump(self, filename, start, number):
|
||||
"""Dump memory from 'start' into 'filename', 'number' words dumped."""
|
||||
|
||||
memdump('core.txt', 0, 0200)
|
||||
with open(filename, 'wb') as fd:
|
||||
for addr in range(start, start+number, 8):
|
||||
a = addr
|
||||
llen = min(8, start+number - addr)
|
||||
line = '%04o ' % addr
|
||||
for _ in range(llen):
|
||||
line += '%06o ' % self.memory.fetch(a, False)
|
||||
a += 1
|
||||
fd.write('%s\n' % line)
|
||||
|
||||
def memdump(filename, start, number):
|
||||
"""Dump memory from 'start' into 'filename', 'number' words dumped."""
|
||||
def main(self, filename):
|
||||
"""Execute CPU tests from 'filename'."""
|
||||
|
||||
with open(filename, 'wb') as fd:
|
||||
for addr in range(start, start+number, 8):
|
||||
a = addr
|
||||
llen = min(8, start+number - addr)
|
||||
line = '%04o ' % addr
|
||||
for _ in range(llen):
|
||||
line += '%06o ' % Memory.fetch(a, False)
|
||||
a += 1
|
||||
fd.write('%s\n' % line)
|
||||
log.debug("Running test file '%s'" % filename)
|
||||
|
||||
def main(filename):
|
||||
"""Execute CPU tests from 'filename'."""
|
||||
# get all tests from file
|
||||
with open(filename, 'rb') as fd:
|
||||
lines = fd.readlines()
|
||||
|
||||
log.debug("Running test file '%s'" % filename)
|
||||
# read lines, join continued, get complete tests
|
||||
tests = []
|
||||
test = ''
|
||||
for line in lines:
|
||||
line = line[:-1] # strip newline
|
||||
if not line:
|
||||
continue # skip blank lines
|
||||
|
||||
# get all tests from file
|
||||
with open(filename, 'rb') as fd:
|
||||
lines = fd.readlines()
|
||||
if line[0] == '#': # a comment
|
||||
continue
|
||||
|
||||
# read lines, join continued, get complete tests
|
||||
tests = []
|
||||
test = ''
|
||||
for line in lines:
|
||||
line = line[:-1] # strip newline
|
||||
if not line:
|
||||
continue # skip blank lines
|
||||
if line[0] == '\t': # continuation
|
||||
if test:
|
||||
test += '; '
|
||||
test += line[1:]
|
||||
else: # beginning of new test
|
||||
if test:
|
||||
tests.append(test)
|
||||
test = line
|
||||
|
||||
if line[0] == '#': # a comment
|
||||
continue
|
||||
|
||||
if line[0] == '\t': # continuation
|
||||
if test:
|
||||
test += '; '
|
||||
test += line[1:]
|
||||
else: # beginning of new test
|
||||
if test:
|
||||
tests.append(test)
|
||||
test = line
|
||||
|
||||
# flush last test
|
||||
if test:
|
||||
tests.append(test)
|
||||
|
||||
# now do each test
|
||||
for test in tests:
|
||||
log.debug('Executing test: %s' % test)
|
||||
execute(test)
|
||||
# flush last test
|
||||
if test:
|
||||
tests.append(test)
|
||||
|
||||
# now do each test
|
||||
for test in tests:
|
||||
log.debug('Executing test: %s' % test)
|
||||
self.execute(test)
|
||||
|
||||
################################################################################
|
||||
|
||||
@@ -524,4 +488,5 @@ if __name__ == '__main__':
|
||||
sys.exit(10)
|
||||
f.close()
|
||||
|
||||
main(filename)
|
||||
test = TestCPU()
|
||||
test.main(filename)
|
||||
|
||||
Reference in New Issue
Block a user