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mirror of https://github.com/rzzzwilson/pymlac.git synced 2025-06-10 09:32:41 +00:00

PTR dumpmem test now completes without error

This commit is contained in:
Ross Wilson
2016-03-12 16:30:46 +07:00
parent f49e9e1fce
commit 4f8d416e09
3 changed files with 13 additions and 5 deletions

View File

@@ -175,6 +175,8 @@ class MainCPU(object):
def execute_one_instruction(self):
"""Execute one MAIN instruction, return # cycles and a trace string."""
log('execute_one_instruction: self.running=%s, .PC=%06o'
% (str(self.running), self.PC))
if not self.running:
return (0, None)
@@ -189,6 +191,7 @@ class MainCPU(object):
indirect = bool(instruction & 0100000)
address = (instruction & 03777)
log('execute_one_instruction: running instruction')
return self.main_decode.get(opcode, self.illegal)(indirect,
address,
instruction)
@@ -224,6 +227,7 @@ class MainCPU(object):
return (1, tracestr)
def i_JMP(self, indirect, address, instruction):
log('JMP handler')
eff_address = self.memory.eff_address(address, indirect)
self.PC = eff_address & PCMASK
tracestr = trace.itrace(self.dot, 'JMP', indirect, address)

View File

@@ -1,3 +1,3 @@
# loads executable tape and dumps 0100+4
bootrom ptr; mount ptr dumpmem_test_c8lds.ptp; setreg pc 040; rununtil 0; dumpmem dumpmem_test.dump 0100,0110
#bootrom tty; mount ttyin dumpmem_test_c8lds.ptp; setreg pc 040; rununtil 0; dumpmem dumpmem_test.dump 0100,0110
# loads executable tape and dumps 0100->0107
bootrom ptr; mount ptr dumpmem_test_c8lds.ptp; setreg pc 040; rununtil 0; checkreg ac 0177777; checkreg pc 03715; dumpmem dumpmem_test.dump 0100,0107; setreg pc 0100; rununtil 0; checkreg ac 0111; checkreg pc 0106
#bootrom tty; mount ttyin dumpmem_test_c8lds.ptp; setreg pc 040; rununtil 0; dumpmem dumpmem_test.dump 0100,0107

View File

@@ -315,13 +315,16 @@ class TestCPU(object):
We also stop if the CPU executes the HLT instruction.
"""
log('rununtil: address=%s' % address)
new_address = self.str2int(address)
if new_address is None:
log('ABORT! rununtil: invalid stop address: %s' % address)
return 'rununtil: invalid stop address: %s' % address
self.used_cycles= 0
log('rununtil: address=%s, self.cpu.running=%s' % (address, str(self.cpu.running)))
self.used_cycles = 0
self.cpu.running = True
while self.cpu.running:
log('rununtil: loop top')
(cycles, tracestr) = self.cpu.execute_one_instruction()
if tracestr:
endstr = trace.itraceend(False)
@@ -332,6 +335,7 @@ class TestCPU(object):
self.used_cycles += cycles
if self.cpu.PC == new_address:
break
log('rununtil: bottom top, PC=%06o' % self.cpu.PC)
def checkcycles(self, cycles, ignore):
"""Check that opcode cycles used is correct.