mirror of
https://github.com/rzzzwilson/pymlac.git
synced 2025-06-10 09:32:41 +00:00
Implemented the multi-line assemble
This commit is contained in:
555
vimlac/CPU.test
555
vimlac/CPU.test
@@ -1,368 +1,368 @@
|
||||
# LAW
|
||||
setreg ac 0177777; setreg l 1; setmem 0100 [LAW 0]; RUN 0100;
|
||||
setreg ac 0177777; setreg l 1; setmem 0100 [LAW 0]; setreg pc 0100; RUN;
|
||||
checkcycles 1; checkreg pc 0101; checkreg ac 0
|
||||
setreg ac 0177777; setreg l 0; setmem 0100 [LAW 0]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0
|
||||
setreg ac 0; setreg l 1; setmem 0100 [LAW 0377]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0377
|
||||
setreg ac 0; setreg l 0; setmem 0100 [LAW 0377]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0377
|
||||
setreg ac 0177777; setreg l 0; setmem 0100 [LAW 0]; setreg pc 0100; RUN; checkcycles 1; checkreg pc 0101; checkreg ac 0
|
||||
setreg ac 0; setreg l 1; setmem 0100 [LAW 0377]; setreg pc 0100; RUN; checkcycles 1; checkreg pc 0101; checkreg ac 0377
|
||||
setreg ac 0; setreg l 0; setmem 0100 [LAW 0377]; setreg pc 0100; RUN; checkcycles 1; checkreg pc 0101; checkreg ac 0377
|
||||
|
||||
# LWC
|
||||
setreg ac 0; setreg l 1; setmem 0100 [LWC 0]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0177777
|
||||
setreg ac 0; setreg l 0; setmem 0100 [LWC 0]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0177777
|
||||
setreg ac 0; setreg l 1; setmem 0100 [LWC 1]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0177776
|
||||
setreg ac 0; setreg l 0; setmem 0100 [LWC 1]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0177776
|
||||
setreg ac 0; setreg l 1; setmem 0100 [LWC 0]; setreg pc 0100; RUN; checkcycles 1; checkreg pc 0101; checkreg ac 0177777
|
||||
setreg ac 0; setreg l 0; setmem 0100 [LWC 0]; setreg pc 0100; RUN; checkcycles 1; checkreg pc 0101; checkreg ac 0177777
|
||||
setreg ac 0; setreg l 1; setmem 0100 [LWC 1]; setreg pc 0100; RUN; checkcycles 1; checkreg pc 0101; checkreg ac 0177776
|
||||
setreg ac 0; setreg l 0; setmem 0100 [LWC 1]; setreg pc 0100; RUN; checkcycles 1; checkreg pc 0101; checkreg ac 0177776
|
||||
|
||||
# JMP
|
||||
setreg ac 012345; setreg l 1; setmem 0100 [JMP 0200]; RUN 0100; checkcycles 2; checkreg pc 0200
|
||||
setreg ac 012345; setreg l 0; setmem 0100 [JMP 0110]; RUN 0100; checkcycles 2; checkreg pc 0110
|
||||
setreg ac 012345; setreg l 1; setmem 0100 [JMP *0110]; setmem 0110 0120; RUN 0100; checkcycles 3; checkreg pc 0120
|
||||
setreg ac 012345; setreg l 0; setmem 0100 [JMP *010]; setmem 010 0120; RUN 0100; checkcycles 3; checkreg pc 0121; checkmem 010 0121
|
||||
setreg ac 012345; setreg l 1; setmem 0100 [JMP 0200]; setreg pc 0100; RUN; checkcycles 2; checkreg pc 0200
|
||||
setreg ac 012345; setreg l 0; setmem 0100 [JMP 0110]; setreg pc 0100; RUN; checkcycles 2; checkreg pc 0110
|
||||
setreg ac 012345; setreg l 1; setmem 0100 [JMP *0110]; setmem 0110 0120; setreg pc 0100; RUN; checkcycles 3; checkreg pc 0120
|
||||
setreg ac 012345; setreg l 0; setmem 0100 [JMP *010]; setmem 010 0120; setreg pc 0100; RUN; checkcycles 3; checkreg pc 0121; checkmem 010 0121
|
||||
|
||||
# DAC
|
||||
setreg ac 1; setreg l 1; setreg pc 0100; setmem 0100 [DAC 0110]; RUN; checkcycles 2; checkreg pc 0101; checkmem 0110 1
|
||||
setreg ac 0177777; setreg l 0; setmem 0100 [DAC *0110]; setmem 0110 0120; RUN 0100; checkcycles 3; checkreg pc 0101; checkmem 0120 0177777
|
||||
setreg ac 0177777; setreg l 1; setmem 0100 [DAC *010]; setmem 010 0120; RUN 0100; checkcycles 3; checkreg pc 0101; checkmem 0121 0177777; checkmem 010 0121
|
||||
setreg ac 0177777; setreg l 0; setmem 0100 [DAC *0110]; setmem 0110 0120; setreg pc 0100; RUN; checkcycles 3; checkreg pc 0101; checkmem 0120 0177777
|
||||
setreg ac 0177777; setreg l 1; setmem 0100 [DAC *010]; setmem 010 0120; setreg pc 0100; RUN; checkcycles 3; checkreg pc 0101; checkmem 0121 0177777; checkmem 010 0121
|
||||
|
||||
# XAM
|
||||
setreg ac 1; setreg l 0; setmem 0100 [XAM 0110]; RUN 0100; checkcycles 2; checkreg pc 0101; checkreg ac 0; checkmem 0110 1
|
||||
setreg ac 0100; setreg l 1; setmem 0100 [XAM *0110]; setmem 0110 0120; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 0; checkmem 0120 0100
|
||||
setreg ac 0200; setreg l 0; setmem 0100 [XAM *010]; setmem 010 0120; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 0; checkmem 010 0121; checkmem 0121 0200
|
||||
setreg ac 1; setreg l 0; setmem 0100 [XAM 0110]; setreg pc 0100; RUN; checkcycles 2; checkreg pc 0101; checkreg ac 0; checkmem 0110 1
|
||||
setreg ac 0100; setreg l 1; setmem 0100 [XAM *0110]; setmem 0110 0120; setreg pc 0100; RUN; checkcycles 3; checkreg pc 0101; checkreg ac 0; checkmem 0120 0100
|
||||
setreg ac 0200; setreg l 0; setmem 0100 [XAM *010]; setmem 010 0120; setreg pc 0100; RUN; checkcycles 3; checkreg pc 0101; checkreg ac 0; checkmem 010 0121; checkmem 0121 0200
|
||||
|
||||
# ISZ
|
||||
setreg ac 1; setreg l 0; setmem 0100 [ISZ 0110]; setmem 0110 0; RUN 0100; checkcycles 2; checkreg pc 0101; checkmem 0110 1
|
||||
setreg ac 1; setreg l 1; setmem 0100 [ISZ 0110]; setmem 0110 0177776; RUN 0100; checkcycles 2; checkreg pc 0101; checkmem 0110 0177777
|
||||
setreg ac 1; setreg l 1; setmem 0100 [ISZ 0110]; setmem 0110 0177777; RUN 0100; checkcycles 2; checkreg pc 0102; checkmem 0110 0
|
||||
setreg ac 1; setreg l 0; setmem 0100 [ISZ 0110]; setmem 0110 0; setreg pc 0100; RUN; checkcycles 2; checkreg pc 0101; checkmem 0110 1
|
||||
setreg ac 1; setreg l 1; setmem 0100 [ISZ 0110]; setmem 0110 0177776; setreg pc 0100; RUN; checkcycles 2; checkreg pc 0101; checkmem 0110 0177777
|
||||
setreg ac 1; setreg l 1; setmem 0100 [ISZ 0110]; setmem 0110 0177777; setreg pc 0100; RUN; checkcycles 2; checkreg pc 0102; checkmem 0110 0
|
||||
|
||||
setreg ac 0; setreg l 1; setmem 0100 [ISZ *0110]; setmem 0110 0120; setmem 0120 0; RUN 0100; checkcycles 3; checkreg pc 0101; checkmem 0120 1
|
||||
setreg ac 0; setreg l 1; setmem 0100 [ISZ *0110]; setmem 0110 0120; setmem 0120 0177776; RUN 0100; checkcycles 3; checkreg pc 0101; checkmem 0120 0177777
|
||||
setreg ac 0; setreg l 1; setmem 0100 [ISZ *0110]; setmem 0110 0120; setmem 0120 0177777; RUN 0100; checkcycles 3; checkreg pc 0102; checkmem 0120 0
|
||||
setreg ac 0; setreg l 1; setmem 0100 [ISZ *0110]; setmem 0110 0120; setmem 0120 0; setreg pc 0100; RUN; checkcycles 3; checkreg pc 0101; checkmem 0120 1
|
||||
setreg ac 0; setreg l 1; setmem 0100 [ISZ *0110]; setmem 0110 0120; setmem 0120 0177776; setreg pc 0100; RUN; checkcycles 3; checkreg pc 0101; checkmem 0120 0177777
|
||||
setreg ac 0; setreg l 1; setmem 0100 [ISZ *0110]; setmem 0110 0120; setmem 0120 0177777; setreg pc 0100; RUN; checkcycles 3; checkreg pc 0102; checkmem 0120 0
|
||||
|
||||
setreg ac 1; setreg l 0; setmem 0100 [ISZ *010]; setmem 010 0120; setmem 0121 0; RUN 0100; checkcycles 3; checkreg pc 0101; checkmem 010 0121; checkmem 0121 1
|
||||
setreg ac 1; setreg l 0; setmem 0100 [ISZ *010]; setmem 010 0120; setmem 0121 0177776; RUN 0100; checkcycles 3; checkreg pc 0101; checkmem 010 0121; checkmem 0121 0177777
|
||||
setreg ac 1; setreg l 0; setmem 0100 [ISZ *010]; setmem 010 0120; setmem 0121 0177777; RUN 0100; checkcycles 3; checkreg pc 0102; checkmem 010 0121; checkmem 0121 0
|
||||
setreg ac 1; setreg l 0; setmem 0100 [ISZ *010]; setmem 010 0120; setmem 0121 0; setreg pc 0100; RUN; checkcycles 3; checkreg pc 0101; checkmem 010 0121; checkmem 0121 1
|
||||
setreg ac 1; setreg l 0; setmem 0100 [ISZ *010]; setmem 010 0120; setmem 0121 0177776; setreg pc 0100; RUN; checkcycles 3; checkreg pc 0101; checkmem 010 0121; checkmem 0121 0177777
|
||||
setreg ac 1; setreg l 0; setmem 0100 [ISZ *010]; setmem 010 0120; setmem 0121 0177777; setreg pc 0100; RUN; checkcycles 3; checkreg pc 0102; checkmem 010 0121; checkmem 0121 0
|
||||
|
||||
# JMS
|
||||
setreg ac 1; setreg l 0; setmem 0100 [JMS 0110]; setmem 0110 1; RUN 0100; checkcycles 2; checkreg pc 0111; checkmem 0110 0101
|
||||
setreg ac 1; setreg l 0; setmem 0100 [JMS *0110]; setmem 0110 0120; setmem 0121 1; RUN 0100; checkcycles 3; checkreg pc 0121; checkmem 0120 0101
|
||||
setreg ac 1; setreg l 0; setmem 0100 [JMS *010]; setmem 010 0120; setmem 0121 1; RUN 0100; checkcycles 3; checkreg pc 0122; checkmem 010 0121; checkmem 0121 0101
|
||||
setreg ac 1; setreg l 0; setmem 0100 [JMS 0110]; setmem 0110 1; setreg pc 0100; RUN; checkcycles 2; checkreg pc 0111; checkmem 0110 0101
|
||||
setreg ac 1; setreg l 0; setmem 0100 [JMS *0110]; setmem 0110 0120; setmem 0121 1; setreg pc 0100; RUN; checkcycles 3; checkreg pc 0121; checkmem 0120 0101
|
||||
setreg ac 1; setreg l 0; setmem 0100 [JMS *010]; setmem 010 0120; setmem 0121 1; setreg pc 0100; RUN; checkcycles 3; checkreg pc 0122; checkmem 010 0121; checkmem 0121 0101
|
||||
|
||||
# AND
|
||||
setreg ac 0; setreg l 0; setmem 0100 [AND 0110]; setmem 0110 1; RUN 0100; checkcycles 2; checkreg pc 0101; checkreg ac 0
|
||||
setreg ac 0177777; setreg l 1; setmem 0100 [AND 0110]; setmem 0110 1; RUN 0100; checkcycles 2; checkreg pc 0101; checkreg ac 1
|
||||
setreg ac 0125252; setreg l 0; setmem 0100 [AND 0110]; setmem 0110 0052525; RUN 0100; checkcycles 2; checkreg pc 0101; checkreg ac 0
|
||||
setreg ac 0177777; setreg l 0; setmem 0100 [AND 0110]; setmem 0110 0052525; RUN 0100; checkcycles 2; checkreg pc 0101; checkreg ac 0052525
|
||||
setreg ac 0; setreg l 0; setmem 0100 [AND 0110]; setmem 0110 1; setreg pc 0100; RUN; checkcycles 2; checkreg pc 0101; checkreg ac 0
|
||||
setreg ac 0177777; setreg l 1; setmem 0100 [AND 0110]; setmem 0110 1; setreg pc 0100; RUN; checkcycles 2; checkreg pc 0101; checkreg ac 1
|
||||
setreg ac 0125252; setreg l 0; setmem 0100 [AND 0110]; setmem 0110 0052525; setreg pc 0100; RUN; checkcycles 2; checkreg pc 0101; checkreg ac 0
|
||||
setreg ac 0177777; setreg l 0; setmem 0100 [AND 0110]; setmem 0110 0052525; setreg pc 0100; RUN; checkcycles 2; checkreg pc 0101; checkreg ac 0052525
|
||||
|
||||
setreg ac 0; setreg l 0; setmem 0100 [AND *0110]; setmem 0110 0120; setmem 0120 1; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 0
|
||||
setreg ac 0177777; setreg l 1; setmem 0100 [AND *0110]; setmem 0110 0120; setmem 0120 1; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 1
|
||||
setreg ac 0125252; setreg l 0; setmem 0100 [AND *0110]; setmem 0110 0120; setmem 0120 0052525; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 0
|
||||
setreg ac 0177777; setreg l 0; setmem 0100 [AND *0110]; setmem 0110 0120; setmem 0120 0052525; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 0052525
|
||||
setreg ac 0; setreg l 0; setmem 0100 [AND *0110]; setmem 0110 0120; setmem 0120 1; setreg pc 0100; RUN; checkcycles 3; checkreg pc 0101; checkreg ac 0
|
||||
setreg ac 0177777; setreg l 1; setmem 0100 [AND *0110]; setmem 0110 0120; setmem 0120 1; setreg pc 0100; RUN; checkcycles 3; checkreg pc 0101; checkreg ac 1
|
||||
setreg ac 0125252; setreg l 0; setmem 0100 [AND *0110]; setmem 0110 0120; setmem 0120 0052525; setreg pc 0100; RUN; checkcycles 3; checkreg pc 0101; checkreg ac 0
|
||||
setreg ac 0177777; setreg l 0; setmem 0100 [AND *0110]; setmem 0110 0120; setmem 0120 0052525; setreg pc 0100; RUN; checkcycles 3; checkreg pc 0101; checkreg ac 0052525
|
||||
|
||||
setreg ac 0; setreg l 0; setmem 0100 [AND *010]; setmem 010 0110; setmem 0111 1; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 0; checkmem 010 0111
|
||||
setreg ac 0177777; setreg l 1; setmem 0100 [AND *010]; setmem 010 0110; setmem 0111 1; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 1; checkmem 010 0111
|
||||
setreg ac 0125252; setreg l 0; setmem 0100 [AND *010]; setmem 010 0110; setmem 0111 0052525; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 0; checkmem 010 0111
|
||||
setreg ac 0177777; setreg l 0; setmem 0100 [AND *010]; setmem 010 0110; setmem 0111 0052525; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 0052525; checkmem 010 0111
|
||||
setreg ac 0; setreg l 0; setmem 0100 [AND *010]; setmem 010 0110; setmem 0111 1; setreg pc 0100; RUN; checkcycles 3; checkreg pc 0101; checkreg ac 0; checkmem 010 0111
|
||||
setreg ac 0177777; setreg l 1; setmem 0100 [AND *010]; setmem 010 0110; setmem 0111 1; setreg pc 0100; RUN; checkcycles 3; checkreg pc 0101; checkreg ac 1; checkmem 010 0111
|
||||
setreg ac 0125252; setreg l 0; setmem 0100 [AND *010]; setmem 010 0110; setmem 0111 0052525; setreg pc 0100; RUN; checkcycles 3; checkreg pc 0101; checkreg ac 0; checkmem 010 0111
|
||||
setreg ac 0177777; setreg l 0; setmem 0100 [AND *010]; setmem 010 0110; setmem 0111 0052525; setreg pc 0100; RUN; checkcycles 3; checkreg pc 0101; checkreg ac 0052525; checkmem 010 0111
|
||||
|
||||
# IOR
|
||||
setreg ac 0; setreg l 0; setmem 0100 [IOR 0110]; setmem 0110 0; RUN 0100; checkcycles 2; checkreg pc 0101; checkreg ac 0
|
||||
setreg ac 0; setreg l 0; setmem 0100 [IOR 0110]; setmem 0110 1; RUN 0100; checkcycles 2; checkreg pc 0101; checkreg ac 1
|
||||
setreg ac 0177777; setreg l 1; setmem 0100 [IOR 0110]; setmem 0110 1; RUN 0100; checkcycles 2; checkreg pc 0101; checkreg ac 0177777
|
||||
setreg ac 0125252; setreg l 0; setmem 0100 [IOR 0110]; setmem 0110 0052525; RUN 0100; checkcycles 2; checkreg pc 0101; checkreg ac 0177777
|
||||
setreg ac 0000777; setreg l 0; setmem 0100 [IOR 0110]; setmem 0110 0177000; RUN 0100; checkcycles 2; checkreg pc 0101; checkreg ac 0177777
|
||||
setreg ac 0; setreg l 0; setmem 0100 [IOR 0110]; setmem 0110 0; setreg pc 0100; RUN; checkcycles 2; checkreg pc 0101; checkreg ac 0
|
||||
setreg ac 0; setreg l 0; setmem 0100 [IOR 0110]; setmem 0110 1; setreg pc 0100; RUN; checkcycles 2; checkreg pc 0101; checkreg ac 1
|
||||
setreg ac 0177777; setreg l 1; setmem 0100 [IOR 0110]; setmem 0110 1; setreg pc 0100; RUN; checkcycles 2; checkreg pc 0101; checkreg ac 0177777
|
||||
setreg ac 0125252; setreg l 0; setmem 0100 [IOR 0110]; setmem 0110 0052525; setreg pc 0100; RUN; checkcycles 2; checkreg pc 0101; checkreg ac 0177777
|
||||
setreg ac 0000777; setreg l 0; setmem 0100 [IOR 0110]; setmem 0110 0177000; setreg pc 0100; RUN; checkcycles 2; checkreg pc 0101; checkreg ac 0177777
|
||||
|
||||
setreg ac 0; setreg l 0; setmem 0100 [IOR *0110]; setmem 0110 0120; setmem 0120 0; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 0
|
||||
setreg ac 0; setreg l 0; setmem 0100 [IOR *0110]; setmem 0110 0120; setmem 0120 1; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 1
|
||||
setreg ac 0177777; setreg l 1; setmem 0100 [IOR *0110]; setmem 0110 0120; setmem 0120 1; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 0177777
|
||||
setreg ac 0125252; setreg l 0; setmem 0100 [IOR *0110]; setmem 0110 0120; setmem 0120 0052525; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 0177777
|
||||
setreg ac 0000777; setreg l 0; setmem 0100 [IOR *0110]; setmem 0110 0120; setmem 0120 0177000; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 0177777
|
||||
setreg ac 0; setreg l 0; setmem 0100 [IOR *0110]; setmem 0110 0120; setmem 0120 0; setreg pc 0100; RUN; checkcycles 3; checkreg pc 0101; checkreg ac 0
|
||||
setreg ac 0; setreg l 0; setmem 0100 [IOR *0110]; setmem 0110 0120; setmem 0120 1; setreg pc 0100; RUN; checkcycles 3; checkreg pc 0101; checkreg ac 1
|
||||
setreg ac 0177777; setreg l 1; setmem 0100 [IOR *0110]; setmem 0110 0120; setmem 0120 1; setreg pc 0100; RUN; checkcycles 3; checkreg pc 0101; checkreg ac 0177777
|
||||
setreg ac 0125252; setreg l 0; setmem 0100 [IOR *0110]; setmem 0110 0120; setmem 0120 0052525; setreg pc 0100; RUN; checkcycles 3; checkreg pc 0101; checkreg ac 0177777
|
||||
setreg ac 0000777; setreg l 0; setmem 0100 [IOR *0110]; setmem 0110 0120; setmem 0120 0177000; setreg pc 0100; RUN; checkcycles 3; checkreg pc 0101; checkreg ac 0177777
|
||||
|
||||
setreg ac 0; setreg l 0; setmem 0100 [IOR *010]; setmem 010 0120; setmem 0121 0; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 0; checkmem 010 0121
|
||||
setreg ac 0; setreg l 0; setmem 0100 [IOR *010]; setmem 010 0120; setmem 0121 1; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 1; checkmem 010 0121
|
||||
setreg ac 0177777; setreg l 1; setmem 0100 [IOR *010]; setmem 010 0120; setmem 0121 1; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 0177777; checkmem 010 0121
|
||||
setreg ac 0125252; setreg l 0; setmem 0100 [IOR *010]; setmem 010 0120; setmem 0121 0052525; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 0177777; checkmem 010 0121
|
||||
setreg ac 0000777; setreg l 0; setmem 0100 [IOR *010]; setmem 010 0120; setmem 0121 0177000; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 0177777; checkmem 010 0121
|
||||
setreg ac 0; setreg l 0; setmem 0100 [IOR *010]; setmem 010 0120; setmem 0121 0; setreg pc 0100; RUN; checkcycles 3; checkreg pc 0101; checkreg ac 0; checkmem 010 0121
|
||||
setreg ac 0; setreg l 0; setmem 0100 [IOR *010]; setmem 010 0120; setmem 0121 1; setreg pc 0100; RUN; checkcycles 3; checkreg pc 0101; checkreg ac 1; checkmem 010 0121
|
||||
setreg ac 0177777; setreg l 1; setmem 0100 [IOR *010]; setmem 010 0120; setmem 0121 1; setreg pc 0100; RUN; checkcycles 3; checkreg pc 0101; checkreg ac 0177777; checkmem 010 0121
|
||||
setreg ac 0125252; setreg l 0; setmem 0100 [IOR *010]; setmem 010 0120; setmem 0121 0052525; setreg pc 0100; RUN; checkcycles 3; checkreg pc 0101; checkreg ac 0177777; checkmem 010 0121
|
||||
setreg ac 0000777; setreg l 0; setmem 0100 [IOR *010]; setmem 010 0120; setmem 0121 0177000; setreg pc 0100; RUN; checkcycles 3; checkreg pc 0101; checkreg ac 0177777; checkmem 010 0121
|
||||
|
||||
# XOR
|
||||
setreg ac 0; setreg l 0; setmem 0100 [XOR 0110]; setmem 0110 0; RUN 0100; checkcycles 2; checkreg pc 0101; checkreg ac 0
|
||||
setreg ac 0; setreg l 0; setmem 0100 [XOR 0110]; setmem 0110 1; RUN 0100; checkcycles 2; checkreg pc 0101; checkreg ac 1
|
||||
setreg ac 1; setreg l 0; setmem 0100 [XOR 0110]; setmem 0110 0; RUN 0100; checkcycles 2; checkreg pc 0101; checkreg ac 1
|
||||
setreg ac 1; setreg l 0; setmem 0100 [XOR 0110]; setmem 0110 1; RUN 0100; checkcycles 2; checkreg pc 0101; checkreg ac 0
|
||||
setreg ac 0177777; setreg l 1; setmem 0100 [XOR 0110]; setmem 0110 1; RUN 0100; checkcycles 2; checkreg pc 0101; checkreg ac 0177776
|
||||
setreg ac 0125252; setreg l 0; setmem 0100 [XOR 0110]; setmem 0110 0052525; RUN 0100; checkcycles 2; checkreg pc 0101; checkreg ac 0177777
|
||||
setreg ac 0000777; setreg l 0; setmem 0100 [XOR 0110]; setmem 0110 0177000; RUN 0100; checkcycles 2; checkreg pc 0101; checkreg ac 0177777
|
||||
setreg ac 0; setreg l 0; setmem 0100 [XOR 0110]; setmem 0110 0; setreg pc 0100; RUN; checkcycles 2; checkreg pc 0101; checkreg ac 0
|
||||
setreg ac 0; setreg l 0; setmem 0100 [XOR 0110]; setmem 0110 1; setreg pc 0100; RUN; checkcycles 2; checkreg pc 0101; checkreg ac 1
|
||||
setreg ac 1; setreg l 0; setmem 0100 [XOR 0110]; setmem 0110 0; setreg pc 0100; RUN; checkcycles 2; checkreg pc 0101; checkreg ac 1
|
||||
setreg ac 1; setreg l 0; setmem 0100 [XOR 0110]; setmem 0110 1; setreg pc 0100; RUN; checkcycles 2; checkreg pc 0101; checkreg ac 0
|
||||
setreg ac 0177777; setreg l 1; setmem 0100 [XOR 0110]; setmem 0110 1; setreg pc 0100; RUN; checkcycles 2; checkreg pc 0101; checkreg ac 0177776
|
||||
setreg ac 0125252; setreg l 0; setmem 0100 [XOR 0110]; setmem 0110 0052525; setreg pc 0100; RUN; checkcycles 2; checkreg pc 0101; checkreg ac 0177777
|
||||
setreg ac 0000777; setreg l 0; setmem 0100 [XOR 0110]; setmem 0110 0177000; setreg pc 0100; RUN; checkcycles 2; checkreg pc 0101; checkreg ac 0177777
|
||||
|
||||
setreg ac 0; setreg l 0; setmem 0100 [XOR *0110]; setmem 0110 0120; setmem 0120 0; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 0
|
||||
setreg ac 0; setreg l 0; setmem 0100 [XOR *0110]; setmem 0110 0120; setmem 0120 1; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 1
|
||||
setreg ac 1; setreg l 0; setmem 0100 [XOR *0110]; setmem 0110 0120; setmem 0120 0; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 1
|
||||
setreg ac 1; setreg l 0; setmem 0100 [XOR *0110]; setmem 0110 0120; setmem 0120 1; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 0
|
||||
setreg ac 0177777; setreg l 1; setmem 0100 [XOR *0110]; setmem 0110 0120; setmem 0120 1; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 0177776
|
||||
setreg ac 0125252; setreg l 0; setmem 0100 [XOR *0110]; setmem 0110 0120; setmem 0120 0052525; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 0177777
|
||||
setreg ac 0000777; setreg l 0; setmem 0100 [XOR *0110]; setmem 0110 0120; setmem 0120 0177000; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 0177777
|
||||
setreg ac 0; setreg l 0; setmem 0100 [XOR *0110]; setmem 0110 0120; setmem 0120 0; setreg pc 0100; RUN; checkcycles 3; checkreg pc 0101; checkreg ac 0
|
||||
setreg ac 0; setreg l 0; setmem 0100 [XOR *0110]; setmem 0110 0120; setmem 0120 1; setreg pc 0100; RUN; checkcycles 3; checkreg pc 0101; checkreg ac 1
|
||||
setreg ac 1; setreg l 0; setmem 0100 [XOR *0110]; setmem 0110 0120; setmem 0120 0; setreg pc 0100; RUN; checkcycles 3; checkreg pc 0101; checkreg ac 1
|
||||
setreg ac 1; setreg l 0; setmem 0100 [XOR *0110]; setmem 0110 0120; setmem 0120 1; setreg pc 0100; RUN; checkcycles 3; checkreg pc 0101; checkreg ac 0
|
||||
setreg ac 0177777; setreg l 1; setmem 0100 [XOR *0110]; setmem 0110 0120; setmem 0120 1; setreg pc 0100; RUN; checkcycles 3; checkreg pc 0101; checkreg ac 0177776
|
||||
setreg ac 0125252; setreg l 0; setmem 0100 [XOR *0110]; setmem 0110 0120; setmem 0120 0052525; setreg pc 0100; RUN; checkcycles 3; checkreg pc 0101; checkreg ac 0177777
|
||||
setreg ac 0000777; setreg l 0; setmem 0100 [XOR *0110]; setmem 0110 0120; setmem 0120 0177000; setreg pc 0100; RUN; checkcycles 3; checkreg pc 0101; checkreg ac 0177777
|
||||
|
||||
setreg ac 0; setreg l 0; setmem 0100 [XOR *010]; setmem 010 0120; setmem 0121 0; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 0; checkmem 010 0121
|
||||
setreg ac 0; setreg l 0; setmem 0100 [XOR *010]; setmem 010 0120; setmem 0121 1; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 1; checkmem 010 0121
|
||||
setreg ac 1; setreg l 0; setmem 0100 [XOR *010]; setmem 010 0120; setmem 0121 0; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 1; checkmem 010 0121
|
||||
setreg ac 1; setreg l 0; setmem 0100 [XOR *010]; setmem 010 0120; setmem 0121 1; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 0; checkmem 010 0121
|
||||
setreg ac 0177777; setreg l 1; setmem 0100 [XOR *010]; setmem 010 0120; setmem 0121 1; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 0177776; checkmem 010 0121
|
||||
setreg ac 0125252; setreg l 0; setmem 0100 [XOR *010]; setmem 010 0120; setmem 0121 0052525; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 0177777; checkmem 010 0121
|
||||
setreg ac 0000777; setreg l 0; setmem 0100 [XOR *010]; setmem 010 0120; setmem 0121 0177000; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 0177777; checkmem 010 0121
|
||||
setreg ac 0; setreg l 0; setmem 0100 [XOR *010]; setmem 010 0120; setmem 0121 0; setreg pc 0100; RUN; checkcycles 3; checkreg pc 0101; checkreg ac 0; checkmem 010 0121
|
||||
setreg ac 0; setreg l 0; setmem 0100 [XOR *010]; setmem 010 0120; setmem 0121 1; setreg pc 0100; RUN; checkcycles 3; checkreg pc 0101; checkreg ac 1; checkmem 010 0121
|
||||
setreg ac 1; setreg l 0; setmem 0100 [XOR *010]; setmem 010 0120; setmem 0121 0; setreg pc 0100; RUN; checkcycles 3; checkreg pc 0101; checkreg ac 1; checkmem 010 0121
|
||||
setreg ac 1; setreg l 0; setmem 0100 [XOR *010]; setmem 010 0120; setmem 0121 1; setreg pc 0100; RUN; checkcycles 3; checkreg pc 0101; checkreg ac 0; checkmem 010 0121
|
||||
setreg ac 0177777; setreg l 1; setmem 0100 [XOR *010]; setmem 010 0120; setmem 0121 1; setreg pc 0100; RUN; checkcycles 3; checkreg pc 0101; checkreg ac 0177776; checkmem 010 0121
|
||||
setreg ac 0125252; setreg l 0; setmem 0100 [XOR *010]; setmem 010 0120; setmem 0121 0052525; setreg pc 0100; RUN; checkcycles 3; checkreg pc 0101; checkreg ac 0177777; checkmem 010 0121
|
||||
setreg ac 0000777; setreg l 0; setmem 0100 [XOR *010]; setmem 010 0120; setmem 0121 0177000; setreg pc 0100; RUN; checkcycles 3; checkreg pc 0101; checkreg ac 0177777; checkmem 010 0121
|
||||
|
||||
# LAC
|
||||
setreg ac 1; setmem 0100 [LAC 0110]; setmem 0110 0; RUN 0100; checkcycles 2; checkreg pc 0101; checkreg ac 0
|
||||
setmem 0100 [LAC 0110]; setmem 0110 1; RUN 0100; checkcycles 2; checkreg pc 0101; checkreg ac 1
|
||||
setmem 0100 [LAC 0110]; setmem 0110 0177777; RUN 0100; checkcycles 2; checkreg pc 0101; checkreg ac 0177777
|
||||
setreg ac 1; setmem 0100 [LAC 0110]; setmem 0110 0; setreg pc 0100; RUN; checkcycles 2; checkreg pc 0101; checkreg ac 0
|
||||
setmem 0100 [LAC 0110]; setmem 0110 1; setreg pc 0100; RUN; checkcycles 2; checkreg pc 0101; checkreg ac 1
|
||||
setmem 0100 [LAC 0110]; setmem 0110 0177777; setreg pc 0100; RUN; checkcycles 2; checkreg pc 0101; checkreg ac 0177777
|
||||
|
||||
setreg ac 1; setmem 0100 [LAC *0110]; setmem 0110 0120; setmem 0120 0; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 0
|
||||
setmem 0100 [LAC *0110]; setmem 0110 0120; setmem 0120 1; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 1
|
||||
setmem 0100 [LAC *0110]; setmem 0110 0120; setmem 0120 0177777; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 0177777
|
||||
setreg ac 1; setmem 0100 [LAC *0110]; setmem 0110 0120; setmem 0120 0; setreg pc 0100; RUN; checkcycles 3; checkreg pc 0101; checkreg ac 0
|
||||
setmem 0100 [LAC *0110]; setmem 0110 0120; setmem 0120 1; setreg pc 0100; RUN; checkcycles 3; checkreg pc 0101; checkreg ac 1
|
||||
setmem 0100 [LAC *0110]; setmem 0110 0120; setmem 0120 0177777; setreg pc 0100; RUN; checkcycles 3; checkreg pc 0101; checkreg ac 0177777
|
||||
|
||||
setreg ac 1; setmem 0100 [LAC *010]; setmem 010 0120; setmem 0121 0; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 0; checkmem 010 0121
|
||||
setmem 0100 [LAC *010]; setmem 010 0120; setmem 0121 1; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 1; checkmem 010 0121
|
||||
setmem 0100 [LAC *010]; setmem 010 0120; setmem 0121 0177777; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 0177777; checkmem 010 0121
|
||||
setreg ac 1; setmem 0100 [LAC *010]; setmem 010 0120; setmem 0121 0; setreg pc 0100; RUN; checkcycles 3; checkreg pc 0101; checkreg ac 0; checkmem 010 0121
|
||||
setmem 0100 [LAC *010]; setmem 010 0120; setmem 0121 1; setreg pc 0100; RUN; checkcycles 3; checkreg pc 0101; checkreg ac 1; checkmem 010 0121
|
||||
setmem 0100 [LAC *010]; setmem 010 0120; setmem 0121 0177777; setreg pc 0100; RUN; checkcycles 3; checkreg pc 0101; checkreg ac 0177777; checkmem 010 0121
|
||||
|
||||
# ADD
|
||||
setreg ac 0; setmem 0100 [ADD 0110]; setmem 0110 0; RUN 0100; checkcycles 2; checkreg pc 0101; checkreg ac 0
|
||||
setreg ac 1; setmem 0100 [ADD 0110]; setmem 0110 0; RUN 0100; checkcycles 2; checkreg pc 0101; checkreg ac 1
|
||||
setreg ac 0; setmem 0100 [ADD 0110]; setmem 0110 1; RUN 0100; checkcycles 2; checkreg pc 0101; checkreg ac 1
|
||||
setreg ac 1; setmem 0100 [ADD 0110]; setmem 0110 1; RUN 0100; checkcycles 2; checkreg pc 0101; checkreg ac 2
|
||||
setreg ac 0; setmem 0100 [ADD 0110]; setmem 0110 0177777; RUN 0100; checkcycles 2; checkreg pc 0101; checkreg ac 0177777
|
||||
setreg ac 1; setreg l 0; setmem 0100 [ADD 0110]; setmem 0110 0177777; RUN 0100; checkcycles 2; checkreg pc 0101; checkreg ac 0; checkreg l 1
|
||||
setreg ac 1; setreg l 1; setmem 0100 [ADD 0110]; setmem 0110 0177777; RUN 0100; checkcycles 2; checkreg pc 0101; checkreg ac 0; checkreg l 0
|
||||
setreg ac 2; setreg l 0; setmem 0100 [ADD 0110]; setmem 0110 0177777; RUN 0100; checkcycles 2; checkreg pc 0101; checkreg ac 1; checkreg l 1
|
||||
setreg ac 2; setreg l 1; setmem 0100 [ADD 0110]; setmem 0110 0177777; RUN 0100; checkcycles 2; checkreg pc 0101; checkreg ac 1; checkreg l 0
|
||||
setreg ac 2; setreg l 1; setmem 0100 [ADD 0110]; setmem 0110 0177775; RUN 0100; checkcycles 2; checkreg pc 0101; checkreg ac 0177777; checkreg l 1
|
||||
setreg ac 0; setmem 0100 [ADD 0110]; setmem 0110 0; setreg pc 0100; RUN; checkcycles 2; checkreg pc 0101; checkreg ac 0
|
||||
setreg ac 1; setmem 0100 [ADD 0110]; setmem 0110 0; setreg pc 0100; RUN; checkcycles 2; checkreg pc 0101; checkreg ac 1
|
||||
setreg ac 0; setmem 0100 [ADD 0110]; setmem 0110 1; setreg pc 0100; RUN; checkcycles 2; checkreg pc 0101; checkreg ac 1
|
||||
setreg ac 1; setmem 0100 [ADD 0110]; setmem 0110 1; setreg pc 0100; RUN; checkcycles 2; checkreg pc 0101; checkreg ac 2
|
||||
setreg ac 0; setmem 0100 [ADD 0110]; setmem 0110 0177777; setreg pc 0100; RUN; checkcycles 2; checkreg pc 0101; checkreg ac 0177777
|
||||
setreg ac 1; setreg l 0; setmem 0100 [ADD 0110]; setmem 0110 0177777; setreg pc 0100; RUN; checkcycles 2; checkreg pc 0101; checkreg ac 0; checkreg l 1
|
||||
setreg ac 1; setreg l 1; setmem 0100 [ADD 0110]; setmem 0110 0177777; setreg pc 0100; RUN; checkcycles 2; checkreg pc 0101; checkreg ac 0; checkreg l 0
|
||||
setreg ac 2; setreg l 0; setmem 0100 [ADD 0110]; setmem 0110 0177777; setreg pc 0100; RUN; checkcycles 2; checkreg pc 0101; checkreg ac 1; checkreg l 1
|
||||
setreg ac 2; setreg l 1; setmem 0100 [ADD 0110]; setmem 0110 0177777; setreg pc 0100; RUN; checkcycles 2; checkreg pc 0101; checkreg ac 1; checkreg l 0
|
||||
setreg ac 2; setreg l 1; setmem 0100 [ADD 0110]; setmem 0110 0177775; setreg pc 0100; RUN; checkcycles 2; checkreg pc 0101; checkreg ac 0177777; checkreg l 1
|
||||
|
||||
setreg ac 0; setmem 0100 [ADD *0110]; setmem 0110 0120; setmem 0120 0; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 0
|
||||
setreg ac 1; setmem 0100 [ADD *0110]; setmem 0110 0120; setmem 0120 0; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 1
|
||||
setreg ac 0; setmem 0100 [ADD *0110]; setmem 0110 0120; setmem 0120 1; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 1
|
||||
setreg ac 1; setmem 0100 [ADD *0110]; setmem 0110 0120; setmem 0120 1; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 2
|
||||
setreg ac 0; setmem 0100 [ADD *0110]; setmem 0110 0120; setmem 0120 0177777; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 0177777
|
||||
setreg ac 1; setmem 0100 [ADD *0110]; setmem 0110 0120; setmem 0120 0177777; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 0; checkreg l 1
|
||||
setreg ac 1; setreg l 1; setmem 0100 [ADD *0110]; setmem 0110 0120; setmem 0120 0177777; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 0; checkreg l 0
|
||||
setreg ac 2; setmem 0100 [ADD *0110]; setmem 0110 0120; setmem 0120 0177777; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 1; checkreg l 1
|
||||
setreg ac 2; setreg l 1; setmem 0100 [ADD *0110]; setmem 0110 0120; setmem 0120 0177777; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 1; checkreg l 0
|
||||
setreg ac 2; setreg l 1; setmem 0100 [ADD *0110]; setmem 0110 0120; setmem 0120 0177775; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 0177777; checkreg l 1
|
||||
setreg ac 0; setmem 0100 [ADD *0110]; setmem 0110 0120; setmem 0120 0; setreg pc 0100; RUN; checkcycles 3; checkreg pc 0101; checkreg ac 0
|
||||
setreg ac 1; setmem 0100 [ADD *0110]; setmem 0110 0120; setmem 0120 0; setreg pc 0100; RUN; checkcycles 3; checkreg pc 0101; checkreg ac 1
|
||||
setreg ac 0; setmem 0100 [ADD *0110]; setmem 0110 0120; setmem 0120 1; setreg pc 0100; RUN; checkcycles 3; checkreg pc 0101; checkreg ac 1
|
||||
setreg ac 1; setmem 0100 [ADD *0110]; setmem 0110 0120; setmem 0120 1; setreg pc 0100; RUN; checkcycles 3; checkreg pc 0101; checkreg ac 2
|
||||
setreg ac 0; setmem 0100 [ADD *0110]; setmem 0110 0120; setmem 0120 0177777; setreg pc 0100; RUN; checkcycles 3; checkreg pc 0101; checkreg ac 0177777
|
||||
setreg ac 1; setmem 0100 [ADD *0110]; setmem 0110 0120; setmem 0120 0177777; setreg pc 0100; RUN; checkcycles 3; checkreg pc 0101; checkreg ac 0; checkreg l 1
|
||||
setreg ac 1; setreg l 1; setmem 0100 [ADD *0110]; setmem 0110 0120; setmem 0120 0177777; setreg pc 0100; RUN; checkcycles 3; checkreg pc 0101; checkreg ac 0; checkreg l 0
|
||||
setreg ac 2; setmem 0100 [ADD *0110]; setmem 0110 0120; setmem 0120 0177777; setreg pc 0100; RUN; checkcycles 3; checkreg pc 0101; checkreg ac 1; checkreg l 1
|
||||
setreg ac 2; setreg l 1; setmem 0100 [ADD *0110]; setmem 0110 0120; setmem 0120 0177777; setreg pc 0100; RUN; checkcycles 3; checkreg pc 0101; checkreg ac 1; checkreg l 0
|
||||
setreg ac 2; setreg l 1; setmem 0100 [ADD *0110]; setmem 0110 0120; setmem 0120 0177775; setreg pc 0100; RUN; checkcycles 3; checkreg pc 0101; checkreg ac 0177777; checkreg l 1
|
||||
|
||||
setreg ac 0; setmem 0100 [ADD *010]; setmem 010 0120; setmem 0121 0; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 0; checkmem 010 0121
|
||||
setreg ac 1; setmem 0100 [ADD *010]; setmem 010 0120; setmem 0121 0; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 1; checkmem 010 0121
|
||||
setreg ac 0; setmem 0100 [ADD *010]; setmem 010 0120; setmem 0121 1; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 1; checkmem 010 0121
|
||||
setreg ac 1; setmem 0100 [ADD *010]; setmem 010 0120; setmem 0121 1; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 2; checkmem 010 0121
|
||||
setreg ac 0; setmem 0100 [ADD *010]; setmem 010 0120; setmem 0121 0177777; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 0177777; checkmem 010 0121
|
||||
setreg ac 1; setmem 0100 [ADD *010]; setmem 010 0120; setmem 0121 0177777; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 0; checkreg l 1; checkmem 010 0121
|
||||
setreg ac 1; setreg l 1; setmem 0100 [ADD *010]; setmem 010 0120; setmem 0121 0177777; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 0; checkreg l 0; checkmem 010 0121
|
||||
setreg ac 2; setmem 0100 [ADD *010]; setmem 010 0120; setmem 0121 0177777; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 1; checkreg l 1; checkmem 010 0121
|
||||
setreg ac 2; setreg l 1; setmem 0100 [ADD *010]; setmem 010 0120; setmem 0121 0177777; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 1; checkreg l 0; checkmem 010 0121
|
||||
setreg ac 2; setreg l 1; setmem 0100 [ADD *010]; setmem 010 0120; setmem 0121 0177775; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 0177777; checkreg l 1; checkmem 010 0121
|
||||
setreg ac 0; setmem 0100 [ADD *010]; setmem 010 0120; setmem 0121 0; setreg pc 0100; RUN; checkcycles 3; checkreg pc 0101; checkreg ac 0; checkmem 010 0121
|
||||
setreg ac 1; setmem 0100 [ADD *010]; setmem 010 0120; setmem 0121 0; setreg pc 0100; RUN; checkcycles 3; checkreg pc 0101; checkreg ac 1; checkmem 010 0121
|
||||
setreg ac 0; setmem 0100 [ADD *010]; setmem 010 0120; setmem 0121 1; setreg pc 0100; RUN; checkcycles 3; checkreg pc 0101; checkreg ac 1; checkmem 010 0121
|
||||
setreg ac 1; setmem 0100 [ADD *010]; setmem 010 0120; setmem 0121 1; setreg pc 0100; RUN; checkcycles 3; checkreg pc 0101; checkreg ac 2; checkmem 010 0121
|
||||
setreg ac 0; setmem 0100 [ADD *010]; setmem 010 0120; setmem 0121 0177777; setreg pc 0100; RUN; checkcycles 3; checkreg pc 0101; checkreg ac 0177777; checkmem 010 0121
|
||||
setreg ac 1; setmem 0100 [ADD *010]; setmem 010 0120; setmem 0121 0177777; setreg pc 0100; RUN; checkcycles 3; checkreg pc 0101; checkreg ac 0; checkreg l 1; checkmem 010 0121
|
||||
setreg ac 1; setreg l 1; setmem 0100 [ADD *010]; setmem 010 0120; setmem 0121 0177777; setreg pc 0100; RUN; checkcycles 3; checkreg pc 0101; checkreg ac 0; checkreg l 0; checkmem 010 0121
|
||||
setreg ac 2; setmem 0100 [ADD *010]; setmem 010 0120; setmem 0121 0177777; setreg pc 0100; RUN; checkcycles 3; checkreg pc 0101; checkreg ac 1; checkreg l 1; checkmem 010 0121
|
||||
setreg ac 2; setreg l 1; setmem 0100 [ADD *010]; setmem 010 0120; setmem 0121 0177777; setreg pc 0100; RUN; checkcycles 3; checkreg pc 0101; checkreg ac 1; checkreg l 0; checkmem 010 0121
|
||||
setreg ac 2; setreg l 1; setmem 0100 [ADD *010]; setmem 010 0120; setmem 0121 0177775; setreg pc 0100; RUN; checkcycles 3; checkreg pc 0101; checkreg ac 0177777; checkreg l 1; checkmem 010 0121
|
||||
|
||||
# SUB
|
||||
setreg ac 0; setreg l 0; setmem 0100 [SUB 0110]; setmem 0110 0; RUN 0100; checkcycles 2; checkreg pc 0101; checkreg ac 0
|
||||
setreg ac 0; setreg l 1; setmem 0100 [SUB 0110]; setmem 0110 0; RUN 0100; checkcycles 2; checkreg pc 0101; checkreg ac 0
|
||||
setreg ac 0; setreg l 0; setmem 0100 [SUB 0110]; setmem 0110 1; RUN 0100; checkcycles 2; checkreg pc 0101; checkreg ac 0177777
|
||||
setreg ac 0; setreg l 1; setmem 0100 [SUB 0110]; setmem 0110 1; RUN 0100; checkcycles 2; checkreg pc 0101; checkreg ac 0177777
|
||||
setreg ac 1; setreg l 0; setmem 0100 [SUB 0110]; setmem 0110 0; RUN 0100; checkcycles 2; checkreg pc 0101; checkreg ac 1
|
||||
setreg ac 1; setreg l 1; setmem 0100 [SUB 0110]; setmem 0110 0; RUN 0100; checkcycles 2; checkreg pc 0101; checkreg ac 1
|
||||
setreg ac 0; setreg l 0; setmem 0100 [SUB 0110]; setmem 0110 0177777; RUN 0100; checkcycles 2; checkreg pc 0101; checkreg ac 1
|
||||
setreg ac 0; setreg l 1; setmem 0100 [SUB 0110]; setmem 0110 0177777; RUN 0100; checkcycles 2; checkreg pc 0101; checkreg ac 1
|
||||
setreg ac 0; setreg l 0; setmem 0100 [SUB 0110]; setmem 0110 0; setreg pc 0100; RUN; checkcycles 2; checkreg pc 0101; checkreg ac 0
|
||||
setreg ac 0; setreg l 1; setmem 0100 [SUB 0110]; setmem 0110 0; setreg pc 0100; RUN; checkcycles 2; checkreg pc 0101; checkreg ac 0
|
||||
setreg ac 0; setreg l 0; setmem 0100 [SUB 0110]; setmem 0110 1; setreg pc 0100; RUN; checkcycles 2; checkreg pc 0101; checkreg ac 0177777
|
||||
setreg ac 0; setreg l 1; setmem 0100 [SUB 0110]; setmem 0110 1; setreg pc 0100; RUN; checkcycles 2; checkreg pc 0101; checkreg ac 0177777
|
||||
setreg ac 1; setreg l 0; setmem 0100 [SUB 0110]; setmem 0110 0; setreg pc 0100; RUN; checkcycles 2; checkreg pc 0101; checkreg ac 1
|
||||
setreg ac 1; setreg l 1; setmem 0100 [SUB 0110]; setmem 0110 0; setreg pc 0100; RUN; checkcycles 2; checkreg pc 0101; checkreg ac 1
|
||||
setreg ac 0; setreg l 0; setmem 0100 [SUB 0110]; setmem 0110 0177777; setreg pc 0100; RUN; checkcycles 2; checkreg pc 0101; checkreg ac 1
|
||||
setreg ac 0; setreg l 1; setmem 0100 [SUB 0110]; setmem 0110 0177777; setreg pc 0100; RUN; checkcycles 2; checkreg pc 0101; checkreg ac 1
|
||||
|
||||
setreg ac 0; setreg l 0; setmem 0100 [SUB *0110]; setmem 0110 0120; setmem 0120 0; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 0
|
||||
setreg ac 0; setreg l 1; setmem 0100 [SUB *0110]; setmem 0110 0120; setmem 0120 0; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 0
|
||||
setreg ac 0; setreg l 0; setmem 0100 [SUB *0110]; setmem 0110 0120; setmem 0120 1; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 0177777
|
||||
setreg ac 0; setreg l 1; setmem 0100 [SUB *0110]; setmem 0110 0120; setmem 0120 1; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 0177777
|
||||
setreg ac 1; setreg l 0; setmem 0100 [SUB *0110]; setmem 0110 0120; setmem 0120 0; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 1
|
||||
setreg ac 1; setreg l 1; setmem 0100 [SUB *0110]; setmem 0110 0120; setmem 0120 0; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 1
|
||||
setreg ac 0; setreg l 0; setmem 0100 [SUB *0110]; setmem 0110 0120; setmem 0120 0177777; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 1
|
||||
setreg ac 0; setreg l 1; setmem 0100 [SUB *0110]; setmem 0110 0120; setmem 0120 0177777; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 1
|
||||
setreg ac 0; setreg l 0; setmem 0100 [SUB *0110]; setmem 0110 0120; setmem 0120 0; setreg pc 0100; RUN; checkcycles 3; checkreg pc 0101; checkreg ac 0
|
||||
setreg ac 0; setreg l 1; setmem 0100 [SUB *0110]; setmem 0110 0120; setmem 0120 0; setreg pc 0100; RUN; checkcycles 3; checkreg pc 0101; checkreg ac 0
|
||||
setreg ac 0; setreg l 0; setmem 0100 [SUB *0110]; setmem 0110 0120; setmem 0120 1; setreg pc 0100; RUN; checkcycles 3; checkreg pc 0101; checkreg ac 0177777
|
||||
setreg ac 0; setreg l 1; setmem 0100 [SUB *0110]; setmem 0110 0120; setmem 0120 1; setreg pc 0100; RUN; checkcycles 3; checkreg pc 0101; checkreg ac 0177777
|
||||
setreg ac 1; setreg l 0; setmem 0100 [SUB *0110]; setmem 0110 0120; setmem 0120 0; setreg pc 0100; RUN; checkcycles 3; checkreg pc 0101; checkreg ac 1
|
||||
setreg ac 1; setreg l 1; setmem 0100 [SUB *0110]; setmem 0110 0120; setmem 0120 0; setreg pc 0100; RUN; checkcycles 3; checkreg pc 0101; checkreg ac 1
|
||||
setreg ac 0; setreg l 0; setmem 0100 [SUB *0110]; setmem 0110 0120; setmem 0120 0177777; setreg pc 0100; RUN; checkcycles 3; checkreg pc 0101; checkreg ac 1
|
||||
setreg ac 0; setreg l 1; setmem 0100 [SUB *0110]; setmem 0110 0120; setmem 0120 0177777; setreg pc 0100; RUN; checkcycles 3; checkreg pc 0101; checkreg ac 1
|
||||
|
||||
setreg ac 0; setreg l 0; setmem 0100 [SUB *010]; setmem 010 0120; setmem 0121 0; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 0; checkmem 010 0121
|
||||
setreg ac 0; setreg l 1; setmem 0100 [SUB *010]; setmem 010 0120; setmem 0121 0; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 0; checkmem 010 0121
|
||||
setreg ac 0; setreg l 0; setmem 0100 [SUB *010]; setmem 010 0120; setmem 0121 1; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 0177777; checkmem 010 0121
|
||||
setreg ac 0; setreg l 1; setmem 0100 [SUB *010]; setmem 010 0120; setmem 0121 1; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 0177777; checkmem 010 0121
|
||||
setreg ac 1; setreg l 0; setmem 0100 [SUB *010]; setmem 010 0120; setmem 0121 0; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 1; checkmem 010 0121
|
||||
setreg ac 1; setreg l 1; setmem 0100 [SUB *010]; setmem 010 0120; setmem 0121 0; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 1; checkmem 010 0121
|
||||
setreg ac 0; setreg l 0; setmem 0100 [SUB *010]; setmem 010 0120; setmem 0121 0177777; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 1; checkmem 010 0121
|
||||
setreg ac 0; setreg l 1; setmem 0100 [SUB *010]; setmem 010 0120; setmem 0121 0177777; RUN 0100; checkcycles 3; checkreg pc 0101; checkreg ac 1; checkmem 010 0121
|
||||
setreg ac 0; setreg l 0; setmem 0100 [SUB *010]; setmem 010 0120; setmem 0121 0; setreg pc 0100; RUN; checkcycles 3; checkreg pc 0101; checkreg ac 0; checkmem 010 0121
|
||||
setreg ac 0; setreg l 1; setmem 0100 [SUB *010]; setmem 010 0120; setmem 0121 0; setreg pc 0100; RUN; checkcycles 3; checkreg pc 0101; checkreg ac 0; checkmem 010 0121
|
||||
setreg ac 0; setreg l 0; setmem 0100 [SUB *010]; setmem 010 0120; setmem 0121 1; setreg pc 0100; RUN; checkcycles 3; checkreg pc 0101; checkreg ac 0177777; checkmem 010 0121
|
||||
setreg ac 0; setreg l 1; setmem 0100 [SUB *010]; setmem 010 0120; setmem 0121 1; setreg pc 0100; RUN; checkcycles 3; checkreg pc 0101; checkreg ac 0177777; checkmem 010 0121
|
||||
setreg ac 1; setreg l 0; setmem 0100 [SUB *010]; setmem 010 0120; setmem 0121 0; setreg pc 0100; RUN; checkcycles 3; checkreg pc 0101; checkreg ac 1; checkmem 010 0121
|
||||
setreg ac 1; setreg l 1; setmem 0100 [SUB *010]; setmem 010 0120; setmem 0121 0; setreg pc 0100; RUN; checkcycles 3; checkreg pc 0101; checkreg ac 1; checkmem 010 0121
|
||||
setreg ac 0; setreg l 0; setmem 0100 [SUB *010]; setmem 010 0120; setmem 0121 0177777; setreg pc 0100; RUN; checkcycles 3; checkreg pc 0101; checkreg ac 1; checkmem 010 0121
|
||||
setreg ac 0; setreg l 1; setmem 0100 [SUB *010]; setmem 010 0120; setmem 0121 0177777; setreg pc 0100; RUN; checkcycles 3; checkreg pc 0101; checkreg ac 1; checkmem 010 0121
|
||||
|
||||
# SAM
|
||||
setreg ac 1; setmem 0100 [SAM 0110]; setmem 0110 0; RUN 0100; checkcycles 2; checkreg pc 0101
|
||||
setreg ac 0; setmem 0100 [SAM 0110]; setmem 0110 0; RUN 0100; checkcycles 2; checkreg pc 0102
|
||||
setreg ac 0177777; setmem 0100 [SAM 0110]; setmem 0110 0177776; RUN 0100; checkcycles 2; checkreg pc 0101
|
||||
setreg ac 0177776; setmem 0100 [SAM 0110]; setmem 0110 0177776; RUN 0100; checkcycles 2; checkreg pc 0102
|
||||
setreg ac 1; setmem 0100 [SAM 0110]; setmem 0110 0; setreg pc 0100; RUN; checkcycles 2; checkreg pc 0101
|
||||
setreg ac 0; setmem 0100 [SAM 0110]; setmem 0110 0; setreg pc 0100; RUN; checkcycles 2; checkreg pc 0102
|
||||
setreg ac 0177777; setmem 0100 [SAM 0110]; setmem 0110 0177776; setreg pc 0100; RUN; checkcycles 2; checkreg pc 0101
|
||||
setreg ac 0177776; setmem 0100 [SAM 0110]; setmem 0110 0177776; setreg pc 0100; RUN; checkcycles 2; checkreg pc 0102
|
||||
|
||||
setreg ac 1; setmem 0100 [SAM *0110]; setmem 0110 0120; setmem 0120 0; RUN 0100; checkcycles 3; checkreg pc 0101
|
||||
setreg ac 0; setmem 0100 [SAM *0110]; setmem 0110 0120; setmem 0120 0; RUN 0100; checkcycles 3; checkreg pc 0102
|
||||
setreg ac 0177777; setmem 0100 [SAM *0110]; setmem 0110 0120; setmem 0120 0177776; RUN 0100; checkcycles 3; checkreg pc 0101
|
||||
setreg ac 0177776; setmem 0100 [SAM *0110]; setmem 0110 0120; setmem 0120 0177776; RUN 0100; checkcycles 3; checkreg pc 0102
|
||||
setreg ac 1; setmem 0100 [SAM *0110]; setmem 0110 0120; setmem 0120 0; setreg pc 0100; RUN; checkcycles 3; checkreg pc 0101
|
||||
setreg ac 0; setmem 0100 [SAM *0110]; setmem 0110 0120; setmem 0120 0; setreg pc 0100; RUN; checkcycles 3; checkreg pc 0102
|
||||
setreg ac 0177777; setmem 0100 [SAM *0110]; setmem 0110 0120; setmem 0120 0177776; setreg pc 0100; RUN; checkcycles 3; checkreg pc 0101
|
||||
setreg ac 0177776; setmem 0100 [SAM *0110]; setmem 0110 0120; setmem 0120 0177776; setreg pc 0100; RUN; checkcycles 3; checkreg pc 0102
|
||||
|
||||
setreg ac 1; setmem 0100 [SAM *010]; setmem 010 0120; setmem 0121 0; RUN 0100; checkcycles 3; checkreg pc 0101; checkmem 010 0121
|
||||
setreg ac 0; setmem 0100 [SAM *010]; setmem 010 0120; setmem 0121 0; RUN 0100; checkcycles 3; checkreg pc 0102; checkmem 010 0121
|
||||
setreg ac 0177777; setmem 0100 [SAM *010]; setmem 010 0120; setmem 0121 0177776; RUN 0100; checkcycles 3; checkreg pc 0101; checkmem 010 0121
|
||||
setreg ac 0177776; setmem 0100 [SAM *010]; setmem 010 0120; setmem 0121 0177776; RUN 0100; checkcycles 3; checkreg pc 0102; checkmem 010 0121
|
||||
setreg ac 1; setmem 0100 [SAM *010]; setmem 010 0120; setmem 0121 0; setreg pc 0100; RUN; checkcycles 3; checkreg pc 0101; checkmem 010 0121
|
||||
setreg ac 0; setmem 0100 [SAM *010]; setmem 010 0120; setmem 0121 0; setreg pc 0100; RUN; checkcycles 3; checkreg pc 0102; checkmem 010 0121
|
||||
setreg ac 0177777; setmem 0100 [SAM *010]; setmem 010 0120; setmem 0121 0177776; setreg pc 0100; RUN; checkcycles 3; checkreg pc 0101; checkmem 010 0121
|
||||
setreg ac 0177776; setmem 0100 [SAM *010]; setmem 010 0120; setmem 0121 0177776; setreg pc 0100; RUN; checkcycles 3; checkreg pc 0102; checkmem 010 0121
|
||||
|
||||
# HLT
|
||||
setmem 0100 [HLT]; RUN 0100; checkcycles 1; checkrun off; checkreg pc 0101
|
||||
setmem 0100 [HLT]; setreg pc 0100; RUN; checkcycles 1; checkcpu off; checkreg pc 0101
|
||||
|
||||
# NOP
|
||||
setmem 0100 [NOP]; RUN 0100; checkcycles 1; checkrun on; checkreg pc 0101
|
||||
setmem 0100 [NOP]; setreg pc 0100; RUN; checkcycles 1; checkcpu on; checkreg pc 0101
|
||||
|
||||
# CLA
|
||||
setreg ac 0; setmem 0100 [CLA]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0
|
||||
setreg ac 1; setmem 0100 [CLA]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0
|
||||
setreg ac 0177777; setmem 0100 [CLA]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0
|
||||
setreg ac 0; setmem 0100 [CLA]; setreg pc 0100; RUN; checkcycles 1; checkreg pc 0101; checkreg ac 0
|
||||
setreg ac 1; setmem 0100 [CLA]; setreg pc 0100; RUN; checkcycles 1; checkreg pc 0101; checkreg ac 0
|
||||
setreg ac 0177777; setmem 0100 [CLA]; setreg pc 0100; RUN; checkcycles 1; checkreg pc 0101; checkreg ac 0
|
||||
|
||||
# CMA
|
||||
setreg ac 0; setmem 0100 [CMA]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0177777
|
||||
setreg ac 1; setmem 0100 [CMA]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0177776
|
||||
setreg ac 0177777; setmem 0100 [CMA]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0
|
||||
setreg ac 0; setmem 0100 [CMA]; setreg pc 0100; RUN; checkcycles 1; checkreg pc 0101; checkreg ac 0177777
|
||||
setreg ac 1; setmem 0100 [CMA]; setreg pc 0100; RUN; checkcycles 1; checkreg pc 0101; checkreg ac 0177776
|
||||
setreg ac 0177777; setmem 0100 [CMA]; setreg pc 0100; RUN; checkcycles 1; checkreg pc 0101; checkreg ac 0
|
||||
|
||||
# STA
|
||||
setreg ac 0; setmem 0100 [STA]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0177777
|
||||
setreg ac 0177777; setmem 0100 [STA]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0177777
|
||||
setreg ac 0; setmem 0100 [STA]; setreg pc 0100; RUN; checkcycles 1; checkreg pc 0101; checkreg ac 0177777
|
||||
setreg ac 0177777; setmem 0100 [STA]; setreg pc 0100; RUN; checkcycles 1; checkreg pc 0101; checkreg ac 0177777
|
||||
|
||||
# IAC
|
||||
setreg ac 0; setmem 0100 [IAC]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 1
|
||||
setreg ac 1; setmem 0100 [IAC]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 2
|
||||
setreg ac 0; setmem 0100 [IAC]; setreg pc 0100; RUN; checkcycles 1; checkreg pc 0101; checkreg ac 1
|
||||
setreg ac 1; setmem 0100 [IAC]; setreg pc 0100; RUN; checkcycles 1; checkreg pc 0101; checkreg ac 2
|
||||
# bug in microcode, MainCPU.py, line 333
|
||||
setreg ac 0177777; setreg l 0; setmem 0100 [IAC]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0; checkreg l 1
|
||||
setreg ac 0177777; setreg l 1; setmem 0100 [IAC]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0; checkreg l 0
|
||||
setreg ac 0177777; setreg l 0; setmem 0100 [IAC]; setreg pc 0100; RUN; checkcycles 1; checkreg pc 0101; checkreg ac 0; checkreg l 1
|
||||
setreg ac 0177777; setreg l 1; setmem 0100 [IAC]; setreg pc 0100; RUN; checkcycles 1; checkreg pc 0101; checkreg ac 0; checkreg l 0
|
||||
|
||||
# CIA
|
||||
setreg ac 0; setreg l 0; setmem 0100 [CIA]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0; checkreg l 1
|
||||
setreg ac 0; setreg l 1; setmem 0100 [CIA]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0; checkreg l 0
|
||||
setreg ac 1; setreg l 0; setmem 0100 [CIA]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0177777; checkreg l 0
|
||||
setreg ac 1; setreg l 1; setmem 0100 [CIA]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0177777; checkreg l 1
|
||||
setreg ac 0177777; setreg l 0; setmem 0100 [CIA]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 1; checkreg l 0
|
||||
setreg ac 0177777; setreg l 1; setmem 0100 [CIA]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 1; checkreg l 1
|
||||
setreg ac 0; setreg l 0; setmem 0100 [CIA]; setreg pc 0100; RUN; checkcycles 1; checkreg pc 0101; checkreg ac 0; checkreg l 1
|
||||
setreg ac 0; setreg l 1; setmem 0100 [CIA]; setreg pc 0100; RUN; checkcycles 1; checkreg pc 0101; checkreg ac 0; checkreg l 0
|
||||
setreg ac 1; setreg l 0; setmem 0100 [CIA]; setreg pc 0100; RUN; checkcycles 1; checkreg pc 0101; checkreg ac 0177777; checkreg l 0
|
||||
setreg ac 1; setreg l 1; setmem 0100 [CIA]; setreg pc 0100; RUN; checkcycles 1; checkreg pc 0101; checkreg ac 0177777; checkreg l 1
|
||||
setreg ac 0177777; setreg l 0; setmem 0100 [CIA]; setreg pc 0100; RUN; checkcycles 1; checkreg pc 0101; checkreg ac 1; checkreg l 0
|
||||
setreg ac 0177777; setreg l 1; setmem 0100 [CIA]; setreg pc 0100; RUN; checkcycles 1; checkreg pc 0101; checkreg ac 1; checkreg l 1
|
||||
|
||||
# CLL
|
||||
setreg l 0; setmem 0100 [CLL]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg l 0
|
||||
setreg l 1; setmem 0100 [CLL]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg l 0
|
||||
setreg l 0; setmem 0100 [CLL]; setreg pc 0100; RUN; checkcycles 1; checkreg pc 0101; checkreg l 0
|
||||
setreg l 1; setmem 0100 [CLL]; setreg pc 0100; RUN; checkcycles 1; checkreg pc 0101; checkreg l 0
|
||||
|
||||
# CML
|
||||
setreg l 0; setmem 0100 [CML]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg l 1
|
||||
setreg l 1; setmem 0100 [CML]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg l 0
|
||||
setreg l 0; setmem 0100 [CML]; setreg pc 0100; RUN; checkcycles 1; checkreg pc 0101; checkreg l 1
|
||||
setreg l 1; setmem 0100 [CML]; setreg pc 0100; RUN; checkcycles 1; checkreg pc 0101; checkreg l 0
|
||||
|
||||
# CAL
|
||||
setreg ac 0177777; setreg l 1; setmem 0100 [CAL]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0; checkreg l 0
|
||||
setreg ac 0; setreg l 0; setmem 0100 [CAL]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0; checkreg l 0
|
||||
setreg ac 0177777; setreg l 1; setmem 0100 [CAL]; setreg pc 0100; RUN; checkcycles 1; checkreg pc 0101; checkreg ac 0; checkreg l 0
|
||||
setreg ac 0; setreg l 0; setmem 0100 [CAL]; setreg pc 0100; RUN; checkcycles 1; checkreg pc 0101; checkreg ac 0; checkreg l 0
|
||||
|
||||
# STL
|
||||
setreg l 0; setmem 0100 [STL]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg l 1
|
||||
setreg l 1; setmem 0100 [STL]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg l 1
|
||||
setreg l 0; setmem 0100 [STL]; setreg pc 0100; RUN; checkcycles 1; checkreg pc 0101; checkreg l 1
|
||||
setreg l 1; setmem 0100 [STL]; setreg pc 0100; RUN; checkcycles 1; checkreg pc 0101; checkreg l 1
|
||||
|
||||
# ODA
|
||||
setreg ds 0; setreg ac 0; setmem 0100 [ODA]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0
|
||||
setreg ds 0177777; setreg ac 0; setmem 0100 [ODA]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0177777
|
||||
setreg ds 0; setreg ac 0177777; setmem 0100 [ODA]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0177777
|
||||
setreg ds 0777; setreg ac 0177070; setmem 0100 [ODA]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0177777
|
||||
setreg ds 0; setreg ac 0; setmem 0100 [ODA]; setreg pc 0100; RUN; checkcycles 1; checkreg pc 0101; checkreg ac 0
|
||||
setreg ds 0177777; setreg ac 0; setmem 0100 [ODA]; setreg pc 0100; RUN; checkcycles 1; checkreg pc 0101; checkreg ac 0177777
|
||||
setreg ds 0; setreg ac 0177777; setmem 0100 [ODA]; setreg pc 0100; RUN; checkcycles 1; checkreg pc 0101; checkreg ac 0177777
|
||||
setreg ds 0777; setreg ac 0177070; setmem 0100 [ODA]; setreg pc 0100; RUN; checkcycles 1; checkreg pc 0101; checkreg ac 0177777
|
||||
|
||||
# LDA
|
||||
setreg ds 0; setreg ac 0; setmem 0100 [LDA]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0
|
||||
setreg ds 0; setreg ac 0177777; setmem 0100 [LDA]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0
|
||||
setreg ds 1; setreg ac 0; setmem 0100 [LDA]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 1
|
||||
setreg ds 0177000; setreg ac 0177777; setmem 0100 [LDA]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0177000
|
||||
setreg ds 0177777; setreg ac 1; setmem 0100 [LDA]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0177777
|
||||
setreg ds 0; setreg ac 0; setmem 0100 [LDA]; setreg pc 0100; RUN; checkcycles 1; checkreg pc 0101; checkreg ac 0
|
||||
setreg ds 0; setreg ac 0177777; setmem 0100 [LDA]; setreg pc 0100; RUN; checkcycles 1; checkreg pc 0101; checkreg ac 0
|
||||
setreg ds 1; setreg ac 0; setmem 0100 [LDA]; setreg pc 0100; RUN; checkcycles 1; checkreg pc 0101; checkreg ac 1
|
||||
setreg ds 0177000; setreg ac 0177777; setmem 0100 [LDA]; setreg pc 0100; RUN; checkcycles 1; checkreg pc 0101; checkreg ac 0177000
|
||||
setreg ds 0177777; setreg ac 1; setmem 0100 [LDA]; setreg pc 0100; RUN; checkcycles 1; checkreg pc 0101; checkreg ac 0177777
|
||||
|
||||
# SAL
|
||||
setreg ac 0; setreg l 0; setmem 0100 [SAL 1]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0
|
||||
setreg ac 0; setreg l 1; setmem 0100 [SAL 1]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0
|
||||
setreg ac 0177777; setreg l 0; setmem 0100 [SAL 1]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0177776
|
||||
setreg ac 0177777; setreg l 1; setmem 0100 [SAL 1]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0177776
|
||||
setreg ac 0100001; setmem 0100 [SAL 1]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0100002
|
||||
setreg ac 0; setreg l 0; setmem 0100 [SAL 1]; setreg pc 0100; RUN; checkcycles 1; checkreg pc 0101; checkreg ac 0
|
||||
setreg ac 0; setreg l 1; setmem 0100 [SAL 1]; setreg pc 0100; RUN; checkcycles 1; checkreg pc 0101; checkreg ac 0
|
||||
setreg ac 0177777; setreg l 0; setmem 0100 [SAL 1]; setreg pc 0100; RUN; checkcycles 1; checkreg pc 0101; checkreg ac 0177776
|
||||
setreg ac 0177777; setreg l 1; setmem 0100 [SAL 1]; setreg pc 0100; RUN; checkcycles 1; checkreg pc 0101; checkreg ac 0177776
|
||||
setreg ac 0100001; setmem 0100 [SAL 1]; setreg pc 0100; RUN; checkcycles 1; checkreg pc 0101; checkreg ac 0100002
|
||||
|
||||
setreg ac 0; setreg l 0; setmem 0100 [SAL 2]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0
|
||||
setreg ac 0; setreg l 1; setmem 0100 [SAL 2]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0
|
||||
setreg ac 0177777; setreg l 0; setmem 0100 [SAL 2]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0177774
|
||||
setreg ac 0177777; setreg l 1; setmem 0100 [SAL 2]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0177774
|
||||
setreg ac 0100001; setmem 0100 [SAL 2]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0100004
|
||||
setreg ac 0; setreg l 0; setmem 0100 [SAL 2]; setreg pc 0100; RUN; checkcycles 1; checkreg pc 0101; checkreg ac 0
|
||||
setreg ac 0; setreg l 1; setmem 0100 [SAL 2]; setreg pc 0100; RUN; checkcycles 1; checkreg pc 0101; checkreg ac 0
|
||||
setreg ac 0177777; setreg l 0; setmem 0100 [SAL 2]; setreg pc 0100; RUN; checkcycles 1; checkreg pc 0101; checkreg ac 0177774
|
||||
setreg ac 0177777; setreg l 1; setmem 0100 [SAL 2]; setreg pc 0100; RUN; checkcycles 1; checkreg pc 0101; checkreg ac 0177774
|
||||
setreg ac 0100001; setmem 0100 [SAL 2]; setreg pc 0100; RUN; checkcycles 1; checkreg pc 0101; checkreg ac 0100004
|
||||
|
||||
setreg ac 0; setreg l 0; setmem 0100 [SAL 3]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0
|
||||
setreg ac 0; setreg l 1; setmem 0100 [SAL 3]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0
|
||||
setreg ac 0177777; setreg l 0; setmem 0100 [SAL 3]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0177770
|
||||
setreg ac 0177777; setreg l 1; setmem 0100 [SAL 3]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0177770
|
||||
setreg ac 0100001; setmem 0100 [SAL 3]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0100010
|
||||
setreg ac 0; setreg l 0; setmem 0100 [SAL 3]; setreg pc 0100; RUN; checkcycles 1; checkreg pc 0101; checkreg ac 0
|
||||
setreg ac 0; setreg l 1; setmem 0100 [SAL 3]; setreg pc 0100; RUN; checkcycles 1; checkreg pc 0101; checkreg ac 0
|
||||
setreg ac 0177777; setreg l 0; setmem 0100 [SAL 3]; setreg pc 0100; RUN; checkcycles 1; checkreg pc 0101; checkreg ac 0177770
|
||||
setreg ac 0177777; setreg l 1; setmem 0100 [SAL 3]; setreg pc 0100; RUN; checkcycles 1; checkreg pc 0101; checkreg ac 0177770
|
||||
setreg ac 0100001; setmem 0100 [SAL 3]; setreg pc 0100; RUN; checkcycles 1; checkreg pc 0101; checkreg ac 0100010
|
||||
|
||||
# SAR
|
||||
setreg ac 0; setreg l 0; setmem 0100 [SAR 1]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0
|
||||
setreg ac 0; setreg l 1; setmem 0100 [SAR 1]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0
|
||||
setreg ac 0177777; setreg l 0; setmem 0100 [SAR 1]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0177777
|
||||
setreg ac 0177777; setreg l 1; setmem 0100 [SAR 1]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0177777
|
||||
setreg ac 1; setreg l 0; setmem 0100 [SAR 1]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0
|
||||
setreg ac 3; setreg l 0; setmem 0100 [SAR 1]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 1
|
||||
setreg ac 0100001; setreg l 0; setmem 0100 [SAR 1]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0140000
|
||||
setreg ac 0; setreg l 0; setmem 0100 [SAR 1]; setreg pc 0100; RUN; checkcycles 1; checkreg pc 0101; checkreg ac 0
|
||||
setreg ac 0; setreg l 1; setmem 0100 [SAR 1]; setreg pc 0100; RUN; checkcycles 1; checkreg pc 0101; checkreg ac 0
|
||||
setreg ac 0177777; setreg l 0; setmem 0100 [SAR 1]; setreg pc 0100; RUN; checkcycles 1; checkreg pc 0101; checkreg ac 0177777
|
||||
setreg ac 0177777; setreg l 1; setmem 0100 [SAR 1]; setreg pc 0100; RUN; checkcycles 1; checkreg pc 0101; checkreg ac 0177777
|
||||
setreg ac 1; setreg l 0; setmem 0100 [SAR 1]; setreg pc 0100; RUN; checkcycles 1; checkreg pc 0101; checkreg ac 0
|
||||
setreg ac 3; setreg l 0; setmem 0100 [SAR 1]; setreg pc 0100; RUN; checkcycles 1; checkreg pc 0101; checkreg ac 1
|
||||
setreg ac 0100001; setreg l 0; setmem 0100 [SAR 1]; setreg pc 0100; RUN; checkcycles 1; checkreg pc 0101; checkreg ac 0140000
|
||||
|
||||
setreg ac 0; setreg l 0; setmem 0100 [SAR 2]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0
|
||||
setreg ac 0; setreg l 1; setmem 0100 [SAR 2]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0
|
||||
setreg ac 0177777; setreg l 0; setmem 0100 [SAR 2]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0177777
|
||||
setreg ac 0177777; setreg l 1; setmem 0100 [SAR 2]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0177777
|
||||
setreg ac 03; setreg l 0; setmem 0100 [SAR 2]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0
|
||||
setreg ac 07; setreg l 0; setmem 0100 [SAR 2]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 1
|
||||
setreg ac 0100001; setreg l 0; setmem 0100 [SAR 2]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0160000
|
||||
setreg ac 0; setreg l 0; setmem 0100 [SAR 2]; setreg pc 0100; RUN; checkcycles 1; checkreg pc 0101; checkreg ac 0
|
||||
setreg ac 0; setreg l 1; setmem 0100 [SAR 2]; setreg pc 0100; RUN; checkcycles 1; checkreg pc 0101; checkreg ac 0
|
||||
setreg ac 0177777; setreg l 0; setmem 0100 [SAR 2]; setreg pc 0100; RUN; checkcycles 1; checkreg pc 0101; checkreg ac 0177777
|
||||
setreg ac 0177777; setreg l 1; setmem 0100 [SAR 2]; setreg pc 0100; RUN; checkcycles 1; checkreg pc 0101; checkreg ac 0177777
|
||||
setreg ac 03; setreg l 0; setmem 0100 [SAR 2]; setreg pc 0100; RUN; checkcycles 1; checkreg pc 0101; checkreg ac 0
|
||||
setreg ac 07; setreg l 0; setmem 0100 [SAR 2]; setreg pc 0100; RUN; checkcycles 1; checkreg pc 0101; checkreg ac 1
|
||||
setreg ac 0100001; setreg l 0; setmem 0100 [SAR 2]; setreg pc 0100; RUN; checkcycles 1; checkreg pc 0101; checkreg ac 0160000
|
||||
|
||||
setreg ac 0; setreg l 0; setmem 0100 [SAR 3]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0
|
||||
setreg ac 0; setreg l 1; setmem 0100 [SAR 3]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0
|
||||
setreg ac 0177777; setreg l 0; setmem 0100 [SAR 3]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0177777
|
||||
setreg ac 0177777; setreg l 1; setmem 0100 [SAR 3]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0177777
|
||||
setreg ac 07; setreg l 0; setmem 0100 [SAR 3]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0
|
||||
setreg ac 017; setreg l 0; setmem 0100 [SAR 3]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 1
|
||||
setreg ac 0100001; setreg l 0; setmem 0100 [SAR 3]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0170000
|
||||
setreg ac 0; setreg l 0; setmem 0100 [SAR 3]; setreg pc 0100; RUN; checkcycles 1; checkreg pc 0101; checkreg ac 0
|
||||
setreg ac 0; setreg l 1; setmem 0100 [SAR 3]; setreg pc 0100; RUN; checkcycles 1; checkreg pc 0101; checkreg ac 0
|
||||
setreg ac 0177777; setreg l 0; setmem 0100 [SAR 3]; setreg pc 0100; RUN; checkcycles 1; checkreg pc 0101; checkreg ac 0177777
|
||||
setreg ac 0177777; setreg l 1; setmem 0100 [SAR 3]; setreg pc 0100; RUN; checkcycles 1; checkreg pc 0101; checkreg ac 0177777
|
||||
setreg ac 07; setreg l 0; setmem 0100 [SAR 3]; setreg pc 0100; RUN; checkcycles 1; checkreg pc 0101; checkreg ac 0
|
||||
setreg ac 017; setreg l 0; setmem 0100 [SAR 3]; setreg pc 0100; RUN; checkcycles 1; checkreg pc 0101; checkreg ac 1
|
||||
setreg ac 0100001; setreg l 0; setmem 0100 [SAR 3]; setreg pc 0100; RUN; checkcycles 1; checkreg pc 0101; checkreg ac 0170000
|
||||
|
||||
# RAL
|
||||
setreg ac 0; setreg l 0; setmem 0100 [RAL 1]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0
|
||||
setreg ac 0; setreg l 1; setmem 0100 [RAL 1]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 1; checkreg l 0
|
||||
setreg ac 1; setreg l 0; setmem 0100 [RAL 1]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 2; checkreg l 0
|
||||
setreg ac 0177777; setreg l 0; setmem 0100 [RAL 1]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0177776; checkreg l 1
|
||||
setreg ac 0; setreg l 0; setmem 0100 [RAL 1]; setreg pc 0100; RUN; checkcycles 1; checkreg pc 0101; checkreg ac 0
|
||||
setreg ac 0; setreg l 1; setmem 0100 [RAL 1]; setreg pc 0100; RUN; checkcycles 1; checkreg pc 0101; checkreg ac 1; checkreg l 0
|
||||
setreg ac 1; setreg l 0; setmem 0100 [RAL 1]; setreg pc 0100; RUN; checkcycles 1; checkreg pc 0101; checkreg ac 2; checkreg l 0
|
||||
setreg ac 0177777; setreg l 0; setmem 0100 [RAL 1]; setreg pc 0100; RUN; checkcycles 1; checkreg pc 0101; checkreg ac 0177776; checkreg l 1
|
||||
|
||||
setreg ac 0; setreg l 0; setmem 0100 [RAL 2]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0
|
||||
setreg ac 0; setreg l 1; setmem 0100 [RAL 2]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 2; checkreg l 0
|
||||
setreg ac 1; setreg l 0; setmem 0100 [RAL 2]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 4; checkreg l 0
|
||||
setreg ac 0177777; setreg l 0; setmem 0100 [RAL 2]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0177775; checkreg l 1
|
||||
setreg ac 0; setreg l 0; setmem 0100 [RAL 2]; setreg pc 0100; RUN; checkcycles 1; checkreg pc 0101; checkreg ac 0
|
||||
setreg ac 0; setreg l 1; setmem 0100 [RAL 2]; setreg pc 0100; RUN; checkcycles 1; checkreg pc 0101; checkreg ac 2; checkreg l 0
|
||||
setreg ac 1; setreg l 0; setmem 0100 [RAL 2]; setreg pc 0100; RUN; checkcycles 1; checkreg pc 0101; checkreg ac 4; checkreg l 0
|
||||
setreg ac 0177777; setreg l 0; setmem 0100 [RAL 2]; setreg pc 0100; RUN; checkcycles 1; checkreg pc 0101; checkreg ac 0177775; checkreg l 1
|
||||
|
||||
setreg ac 0; setreg l 0; setmem 0100 [RAL 3]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0
|
||||
setreg ac 0; setreg l 1; setmem 0100 [RAL 3]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 4; checkreg l 0
|
||||
setreg ac 1; setreg l 0; setmem 0100 [RAL 3]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 010; checkreg l 0
|
||||
setreg ac 0177777; setreg l 0; setmem 0100 [RAL 3]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0177773; checkreg l 1
|
||||
setreg ac 0; setreg l 0; setmem 0100 [RAL 3]; setreg pc 0100; RUN; checkcycles 1; checkreg pc 0101; checkreg ac 0
|
||||
setreg ac 0; setreg l 1; setmem 0100 [RAL 3]; setreg pc 0100; RUN; checkcycles 1; checkreg pc 0101; checkreg ac 4; checkreg l 0
|
||||
setreg ac 1; setreg l 0; setmem 0100 [RAL 3]; setreg pc 0100; RUN; checkcycles 1; checkreg pc 0101; checkreg ac 010; checkreg l 0
|
||||
setreg ac 0177777; setreg l 0; setmem 0100 [RAL 3]; setreg pc 0100; RUN; checkcycles 1; checkreg pc 0101; checkreg ac 0177773; checkreg l 1
|
||||
|
||||
# RAR
|
||||
setreg ac 0; setreg l 0; setmem 0100 [RAR 1]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0
|
||||
setreg ac 0; setreg l 1; setmem 0100 [RAR 1]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0100000; checkreg l 0
|
||||
setreg ac 1; setreg l 0; setmem 0100 [RAR 1]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0; checkreg l 1
|
||||
setreg ac 0177777; setreg l 0; setmem 0100 [RAR 1]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0077777; checkreg l 1
|
||||
setreg ac 0; setreg l 0; setmem 0100 [RAR 1]; setreg pc 0100; RUN; checkcycles 1; checkreg pc 0101; checkreg ac 0
|
||||
setreg ac 0; setreg l 1; setmem 0100 [RAR 1]; setreg pc 0100; RUN; checkcycles 1; checkreg pc 0101; checkreg ac 0100000; checkreg l 0
|
||||
setreg ac 1; setreg l 0; setmem 0100 [RAR 1]; setreg pc 0100; RUN; checkcycles 1; checkreg pc 0101; checkreg ac 0; checkreg l 1
|
||||
setreg ac 0177777; setreg l 0; setmem 0100 [RAR 1]; setreg pc 0100; RUN; checkcycles 1; checkreg pc 0101; checkreg ac 0077777; checkreg l 1
|
||||
|
||||
setreg ac 0; setreg l 0; setmem 0100 [RAR 2]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0
|
||||
setreg ac 0; setreg l 1; setmem 0100 [RAR 2]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0040000; checkreg l 0
|
||||
setreg ac 1; setreg l 0; setmem 0100 [RAR 2]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0100000; checkreg l 0
|
||||
setreg ac 0177777; setreg l 0; setmem 0100 [RAR 2]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0137777; checkreg l 1
|
||||
setreg ac 0; setreg l 0; setmem 0100 [RAR 2]; setreg pc 0100; RUN; checkcycles 1; checkreg pc 0101; checkreg ac 0
|
||||
setreg ac 0; setreg l 1; setmem 0100 [RAR 2]; setreg pc 0100; RUN; checkcycles 1; checkreg pc 0101; checkreg ac 0040000; checkreg l 0
|
||||
setreg ac 1; setreg l 0; setmem 0100 [RAR 2]; setreg pc 0100; RUN; checkcycles 1; checkreg pc 0101; checkreg ac 0100000; checkreg l 0
|
||||
setreg ac 0177777; setreg l 0; setmem 0100 [RAR 2]; setreg pc 0100; RUN; checkcycles 1; checkreg pc 0101; checkreg ac 0137777; checkreg l 1
|
||||
|
||||
setreg ac 0; setreg l 0; setmem 0100 [RAR 3]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0
|
||||
setreg ac 0; setreg l 1; setmem 0100 [RAR 3]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0020000; checkreg l 0
|
||||
setreg ac 1; setreg l 0; setmem 0100 [RAR 3]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0040000; checkreg l 0
|
||||
setreg ac 0177777; setreg l 0; setmem 0100 [RAR 3]; RUN 0100; checkcycles 1; checkreg pc 0101; checkreg ac 0157777; checkreg l 1
|
||||
setreg ac 0; setreg l 0; setmem 0100 [RAR 3]; setreg pc 0100; RUN; checkcycles 1; checkreg pc 0101; checkreg ac 0
|
||||
setreg ac 0; setreg l 1; setmem 0100 [RAR 3]; setreg pc 0100; RUN; checkcycles 1; checkreg pc 0101; checkreg ac 0020000; checkreg l 0
|
||||
setreg ac 1; setreg l 0; setmem 0100 [RAR 3]; setreg pc 0100; RUN; checkcycles 1; checkreg pc 0101; checkreg ac 0040000; checkreg l 0
|
||||
setreg ac 0177777; setreg l 0; setmem 0100 [RAR 3]; setreg pc 0100; RUN; checkcycles 1; checkreg pc 0101; checkreg ac 0157777; checkreg l 1
|
||||
|
||||
# ASZ
|
||||
setreg ac 1; setmem 0100 [ASZ]; RUN 0100; checkcycles 1; checkreg pc 0101
|
||||
setreg ac 0; setmem 0100 [ASZ]; RUN 0100; checkcycles 1; checkreg pc 0102
|
||||
setreg ac 0177777; setmem 0100 [ASZ]; RUN 0100; checkcycles 1; checkreg pc 0101
|
||||
setreg ac 1; setmem 0100 [ASZ]; setreg pc 0100; RUN; checkcycles 1; checkreg pc 0101
|
||||
setreg ac 0; setmem 0100 [ASZ]; setreg pc 0100; RUN; checkcycles 1; checkreg pc 0102
|
||||
setreg ac 0177777; setmem 0100 [ASZ]; setreg pc 0100; RUN; checkcycles 1; checkreg pc 0101
|
||||
|
||||
# ASN
|
||||
setreg ac 1; setmem 0100 [ASN]; RUN 0100; checkcycles 1; checkreg pc 0102
|
||||
setreg ac 0; setmem 0100 [ASN]; RUN 0100; checkcycles 1; checkreg pc 0101
|
||||
setreg ac 0177777; setmem 0100 [ASN]; RUN 0100; checkcycles 1; checkreg pc 0102
|
||||
setreg ac 1; setmem 0100 [ASN]; setreg pc 0100; RUN; checkcycles 1; checkreg pc 0102
|
||||
setreg ac 0; setmem 0100 [ASN]; setreg pc 0100; RUN; checkcycles 1; checkreg pc 0101
|
||||
setreg ac 0177777; setmem 0100 [ASN]; setreg pc 0100; RUN; checkcycles 1; checkreg pc 0102
|
||||
|
||||
# ASP
|
||||
setreg ac 1; setmem 0100 [ASP]; RUN 0100; checkcycles 1; checkreg pc 0102
|
||||
setreg ac 0; setmem 0100 [ASP]; RUN 0100; checkcycles 1; checkreg pc 0102
|
||||
setreg ac 0177777; setmem 0100 [ASP]; RUN 0100; checkcycles 1; checkreg pc 0101
|
||||
setreg ac 1; setmem 0100 [ASP]; setreg pc 0100; RUN; checkcycles 1; checkreg pc 0102
|
||||
setreg ac 0; setmem 0100 [ASP]; setreg pc 0100; RUN; checkcycles 1; checkreg pc 0102
|
||||
setreg ac 0177777; setmem 0100 [ASP]; setreg pc 0100; RUN; checkcycles 1; checkreg pc 0101
|
||||
|
||||
# ASM
|
||||
setreg ac 1; setmem 0100 [ASM]; RUN 0100; checkcycles 1; checkreg pc 0101
|
||||
setreg ac 0; setmem 0100 [ASM]; RUN 0100; checkcycles 1; checkreg pc 0101
|
||||
setreg ac 0177777; setmem 0100 [ASM]; RUN 0100; checkcycles 1; checkreg pc 0102
|
||||
setreg ac 1; setmem 0100 [ASM]; setreg pc 0100; RUN; checkcycles 1; checkreg pc 0101
|
||||
setreg ac 0; setmem 0100 [ASM]; setreg pc 0100; RUN; checkcycles 1; checkreg pc 0101
|
||||
setreg ac 0177777; setmem 0100 [ASM]; setreg pc 0100; RUN; checkcycles 1; checkreg pc 0102
|
||||
|
||||
# LSZ
|
||||
setreg l 0; setmem 0100 [LSZ]; RUN 0100; checkcycles 1; checkreg pc 0102
|
||||
setreg l 1; setmem 0100 [LSZ]; RUN 0100; checkcycles 1; checkreg pc 0101
|
||||
setreg l 0; setmem 0100 [LSZ]; setreg pc 0100; RUN; checkcycles 1; checkreg pc 0102
|
||||
setreg l 1; setmem 0100 [LSZ]; setreg pc 0100; RUN; checkcycles 1; checkreg pc 0101
|
||||
|
||||
# LSN
|
||||
setreg l 0; setmem 0100 [LSN]; RUN 0100; checkcycles 1; checkreg pc 0101
|
||||
setreg l 1; setmem 0100 [LSN]; RUN 0100; checkcycles 1; checkreg pc 0102
|
||||
setreg l 0; setmem 0100 [LSN]; setreg pc 0100; RUN; checkcycles 1; checkreg pc 0101
|
||||
setreg l 1; setmem 0100 [LSN]; setreg pc 0100; RUN; checkcycles 1; checkreg pc 0102
|
||||
|
||||
# not tested here, interacting with other hardware
|
||||
# DON
|
||||
@@ -377,7 +377,17 @@ setreg l 1; setmem 0100 [LSN]; RUN 0100; checkcycles 1; checkreg pc 0102
|
||||
# SSF
|
||||
# SSN
|
||||
# HSF
|
||||
setreg ac 0; setreg pc 0100; mount ptr test.ptr;
|
||||
setmem 0100 [HON|HSF|JMP 0101|LAW 0|HRB|NOP|HSN|JMP 0106|JMP 0101];
|
||||
rununtil 0105; checkreg ac 0; checkreg pc 0105
|
||||
rununtil 0105; checkreg ac 1; checkreg pc 0105
|
||||
rununtil 0105; checkreg ac 2; checkreg pc 0105;
|
||||
# HSN
|
||||
setreg ac 0; setreg pc 0100; mount ptr test.ptr;
|
||||
setmem 0100 [HON|HSF|JMP 0101|LAW 0|HRB|NOP|HSN|JMP 0106|JMP 0101];
|
||||
rununtil 0105; checkreg ac 0; checkreg pc 0105
|
||||
rununtil 0105; checkreg ac 1; checkreg pc 0105
|
||||
rununtil 0105; checkreg ac 2; checkreg pc 0105;
|
||||
#
|
||||
# DLA
|
||||
# CTB
|
||||
@@ -392,6 +402,12 @@ setreg l 1; setmem 0100 [LSN]; RUN 0100; checkcycles 1; checkreg pc 0102
|
||||
# TCF
|
||||
# TPC
|
||||
# HRB
|
||||
# HSF
|
||||
setreg ac 0; setreg pc 0100; mount ptr test.ptr;
|
||||
setmem 0100 [HON|HSF|JMP 0101|LAW 0|HRB|NOP|HSN|JMP 0106|JMP 0101];
|
||||
rununtil 0105; checkreg ac 0; checkreg pc 0105
|
||||
rununtil 0105; checkreg ac 1; checkreg pc 0105
|
||||
rununtil 0105; checkreg ac 2; checkreg pc 0105;
|
||||
# HOF
|
||||
# HON
|
||||
# STB
|
||||
@@ -399,4 +415,13 @@ setreg l 1; setmem 0100 [LSN]; RUN 0100; checkcycles 1; checkreg pc 0102
|
||||
# IOS
|
||||
# PSF
|
||||
# PPC
|
||||
setreg ac 0; setreg pc 0100; mount ptp test.ptp;
|
||||
setmem 0100 [LAW 0|PSF|JMP 0101|PPC|IAC|JMP 0101];
|
||||
rununtil 0104; checkreg ac 0;
|
||||
rununtil 0104; checkreg ac 1;
|
||||
rununtil 0104; checkreg ac 2; checkreg pc 0104
|
||||
checkfile test.ptp test.ptr
|
||||
# and lots of IOT instructions
|
||||
|
||||
# check multiple assemblerinstructions in DSL
|
||||
setmem 0100 [LAW 1|HLT]; setreg pc 0100; RUNUNTIL 0102; checkcycles 2; checkreg pc 0102; checkreg ac 1
|
||||
|
||||
@@ -2,7 +2,7 @@ DEVFILES = cpu.o dcpu.o ptr.o ptp.o memory.o kb.o ttyin.o ttyout.o trace.o error
|
||||
OFILES = vimlac.o $(DEVFILES)
|
||||
|
||||
#CFLAGS=-fPIC -O2 -Wall -ansi -pedantic -std=c99 -g
|
||||
CFLAGS=-O2 -Wall -ansi -pedantic -std=c99 -g -Wformat-security
|
||||
CFLAGS=-O2 -Wall -ansi -pedantic -std=c99 -g
|
||||
|
||||
test_cpu: test_cpu.c $(DEVFILES) Makefile
|
||||
gcc -o test_cpu ${CFLAGS} $(DEVFILES) test_cpu.c
|
||||
|
||||
@@ -100,6 +100,13 @@ typedef struct _Assoc
|
||||
} Assoc;
|
||||
|
||||
|
||||
typedef struct _Opcode
|
||||
{
|
||||
WORD opcode;
|
||||
struct _Opcode *next;
|
||||
} Opcode;
|
||||
|
||||
|
||||
bool DisplayOn = false;
|
||||
int UsedCycles = 0;
|
||||
WORD RegAllValue = 0;
|
||||
@@ -124,14 +131,7 @@ Description : Show progress while we process tests.
|
||||
void
|
||||
show_progress(int lnum)
|
||||
{
|
||||
// static int count = 0;
|
||||
// int index = count++ % NUMELTS(Progress);
|
||||
// char *p = Progress[index];
|
||||
char p[32];
|
||||
|
||||
sprintf(p, "\b\b\b\b\b\b\b\bTest %03d\r", lnum);
|
||||
|
||||
printf(p);
|
||||
printf("\b\b\b\b\b\b\b\bTest %03d\r", lnum);
|
||||
fflush(stdout);
|
||||
}
|
||||
|
||||
@@ -209,6 +209,36 @@ dump_cmd(Command *cmd)
|
||||
printf("~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~\n");
|
||||
}
|
||||
|
||||
/******************************************************************************
|
||||
Description : Split a string into head/tail using delimiter char.
|
||||
Parameters : str string to split
|
||||
: delim character to split string on
|
||||
Returns : Pointer to tail string, NULL if no tail.
|
||||
Comments : The input string is destroyed in-situ.
|
||||
: Usage something like:
|
||||
: char *str = "abc|rst|xyz";
|
||||
: char *new_str;
|
||||
: while (new_str = split(str, '|')
|
||||
: {
|
||||
: process(str); // do something with head
|
||||
: str = new_str; // move to tail, repeat
|
||||
: }
|
||||
******************************************************************************/
|
||||
char *
|
||||
split(char *str, char delim)
|
||||
{
|
||||
char *result = strchr(str, delim);
|
||||
|
||||
if (result != NULL)
|
||||
{
|
||||
*result = '\0';
|
||||
++result;
|
||||
}
|
||||
|
||||
return result;
|
||||
}
|
||||
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// The following routines wrap the 'plist' functions so we are handling data
|
||||
// formats useful to the test code. We want to handle WORD values and WORD
|
||||
@@ -365,7 +395,8 @@ setd(char *state, char *var2)
|
||||
/******************************************************************************
|
||||
Description : Set a memory cell to a value;
|
||||
Parameters : addr - address of memory cell (string)
|
||||
: fld2 - value to put into cell (string)
|
||||
: fld2 - string conatining one or more values to put into memory
|
||||
: (eg, "123|234|345" or "12345")
|
||||
Returns : The number of errors encountered (0 or 1).
|
||||
Comments : Sets globals used to check after execution.
|
||||
******************************************************************************/
|
||||
@@ -373,11 +404,17 @@ int
|
||||
setmem(char *addr, char *fld2)
|
||||
{
|
||||
WORD address = str2word(addr);
|
||||
WORD value = str2word(fld2);
|
||||
char *new_fld2;
|
||||
|
||||
mem_put(address, false, value);
|
||||
while ((new_fld2 = split(fld2, '|')))
|
||||
{
|
||||
WORD value = str2word(fld2);
|
||||
|
||||
save_mem_plist(address, value);
|
||||
mem_put(address, false, value);
|
||||
save_mem_plist(address, value);
|
||||
++address;
|
||||
fld2 = new_fld2;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
@@ -683,37 +720,74 @@ usage(char *msg)
|
||||
Description : Function to return the imlac binary opcode of an instruction.
|
||||
Parameters : addr - address of the instruction
|
||||
: opcode - string containing the instruction
|
||||
Returns :
|
||||
Returns : A linked list of binary opcodes.
|
||||
Comments : We already have an assembler, so we just reuse it. Generate an
|
||||
: ASM file, assemble it and pick out the opcode from the LST file.
|
||||
: ASM file, assemble it and pick out the opcodes from the LST file.
|
||||
******************************************************************************/
|
||||
WORD
|
||||
assemble(WORD addr, char *opcode)
|
||||
Opcode *
|
||||
assemble(WORD addr, char *opcodes)
|
||||
{
|
||||
FILE *fd;
|
||||
char buffer[128];
|
||||
WORD result;
|
||||
Opcode *result = NULL;
|
||||
Opcode *last_result = NULL;
|
||||
char *strcopy = new_String(opcodes);
|
||||
char *old_strcopy = strcopy;
|
||||
char *new_strcopy;
|
||||
int num_opcodes = 0;
|
||||
|
||||
// create the ASM file
|
||||
fd = fopen(AsmFilename, "wb");
|
||||
fprintf(fd, "\torg\t%07o\n", addr);
|
||||
fprintf(fd, "\t%s\n", opcode);
|
||||
while ((new_strcopy = split(strcopy, '|')))
|
||||
{
|
||||
fprintf(fd, "\t%s\n", strcopy);
|
||||
++num_opcodes;
|
||||
strcopy = new_strcopy;
|
||||
}
|
||||
fprintf(fd, "\tend\n");
|
||||
fclose(fd);
|
||||
free(old_strcopy);
|
||||
|
||||
// assemble the file
|
||||
sprintf(buffer, "../iasm/iasm -l %s %s", LstFilename, AsmFilename);
|
||||
if (system(buffer) == -1)
|
||||
error("Error doing: %s", buffer);
|
||||
|
||||
// read LST file for opcode on second line
|
||||
// read LST file for opcodes on second and subsequent
|
||||
fd = fopen(LstFilename, "rb");
|
||||
|
||||
// skip first line - ORG
|
||||
if (fgets(buffer, sizeof(buffer), fd) == NULL)
|
||||
error("Error reading %s", LstFilename);
|
||||
if (fgets(buffer, sizeof(buffer), fd) == NULL)
|
||||
error("Error reading %s", LstFilename);
|
||||
if (sscanf(buffer, "%o", &result) != 1)
|
||||
error("Badly formatted assembler output: %s", buffer);
|
||||
|
||||
while (num_opcodes)
|
||||
{
|
||||
Opcode *new_opcode = malloc(sizeof(Opcode));
|
||||
|
||||
// get next line of assembler listing
|
||||
if (fgets(buffer, sizeof(buffer), fd) == NULL)
|
||||
error("Error reading %s", LstFilename);
|
||||
|
||||
// read first word value
|
||||
if (sscanf(buffer, "%o", &new_opcode->opcode) != 1)
|
||||
error("Badly formatted assembler output: %s", buffer);
|
||||
|
||||
// add binary opcode to end of result list
|
||||
if (result == NULL)
|
||||
{
|
||||
result = last_result = new_opcode;
|
||||
}
|
||||
else
|
||||
{
|
||||
last_result->next = new_opcode;
|
||||
last_result = new_opcode;
|
||||
}
|
||||
|
||||
new_opcode->next = NULL;
|
||||
--num_opcodes;
|
||||
}
|
||||
|
||||
fclose(fd);
|
||||
|
||||
return result;
|
||||
@@ -760,8 +834,9 @@ parse_one_cmd(char *scan)
|
||||
char *field1 = NULL;
|
||||
char *field2 = NULL;
|
||||
char *orig2 = NULL;
|
||||
char tmpbuff[16];
|
||||
char tmpbuff[256];
|
||||
|
||||
printf("parse_one_cmd: scan->%s\n", scan);
|
||||
|
||||
// find start and end of opcode
|
||||
while (*scan && isspace(*scan)) // skip leading space
|
||||
@@ -773,9 +848,12 @@ parse_one_cmd(char *scan)
|
||||
if (*scan)
|
||||
*(scan++) = '\0';
|
||||
|
||||
printf("parse_one_cmd: opcode->%s\n", opcode);
|
||||
|
||||
// start/end of field1 (if there)
|
||||
while (*scan && isspace(*scan)) // skip leading space
|
||||
++scan;
|
||||
|
||||
if (*scan)
|
||||
{ // we have field1, at least
|
||||
field1 = scan;
|
||||
@@ -784,11 +862,15 @@ parse_one_cmd(char *scan)
|
||||
if (*scan)
|
||||
*(scan++) = '\0';
|
||||
|
||||
// field2
|
||||
printf("parse_one_cmd: field1->%s\n", field1);
|
||||
|
||||
// field2?
|
||||
while (*scan && isspace(*scan)) // skip leading space
|
||||
++scan;
|
||||
|
||||
if (*scan)
|
||||
{
|
||||
// we do have field2
|
||||
field2 = scan;
|
||||
if (*field2 == '[')
|
||||
{ // assembler field
|
||||
@@ -797,10 +879,14 @@ parse_one_cmd(char *scan)
|
||||
while (*scan && !(*scan == ']'))
|
||||
++scan;
|
||||
*scan = '\0';
|
||||
WORD v = str2word(field1);
|
||||
v = assemble(str2word(field1), field2);
|
||||
sprintf(tmpbuff, "%d", v);
|
||||
field2 = tmpbuff;
|
||||
printf("parse_one_cmd: calling assemble(%s, %s)\n", field1, field2);
|
||||
Opcode *v = assemble(str2word(field1), field2); // destroys field2
|
||||
while (v)
|
||||
{
|
||||
sprintf(tmpbuff+strlen(tmpbuff), "|%d", v->opcode);
|
||||
v = v->next;
|
||||
}
|
||||
field2 = tmpbuff+1;
|
||||
}
|
||||
else
|
||||
{
|
||||
@@ -844,6 +930,8 @@ parse_cmds(char *scan)
|
||||
char *end_cmd = NULL;
|
||||
Command *new_cmd = NULL;
|
||||
|
||||
printf("parse_cmds: entered: %s\n", scan);
|
||||
|
||||
// scan the buffer for commands
|
||||
do
|
||||
{
|
||||
@@ -859,7 +947,9 @@ parse_cmds(char *scan)
|
||||
*end_cmd = '\0';
|
||||
}
|
||||
|
||||
printf("Calling parse_one_cmd(%s)\n", scan);
|
||||
new_cmd = parse_one_cmd(scan);
|
||||
printf("After parse_one_cmd()\n");
|
||||
|
||||
if (result == NULL)
|
||||
{
|
||||
@@ -875,6 +965,7 @@ parse_cmds(char *scan)
|
||||
scan = new_scan;
|
||||
} while (scan && *scan);
|
||||
|
||||
printf("parse_cmds: end, returning:\n");
|
||||
|
||||
return result;
|
||||
}
|
||||
@@ -1081,7 +1172,6 @@ int
|
||||
run_one_test(Test *test)
|
||||
{
|
||||
int error = 0;
|
||||
// char buffer[256];
|
||||
|
||||
// set up memory/register value data structures
|
||||
MemValues = PlistCreate();
|
||||
@@ -1104,6 +1194,8 @@ run_one_test(Test *test)
|
||||
char *fld2 = cmd->field2;
|
||||
|
||||
#ifdef JUNK
|
||||
char buffer[256];
|
||||
|
||||
if (fld2)
|
||||
sprintf(buffer, "%s %s %07o%s",
|
||||
opcode, fld1, str2word(fld2), (cmd->orig2) ? cmd->orig2 : "");
|
||||
@@ -1229,7 +1321,7 @@ execute(char *script)
|
||||
// get test commands into massaged form in memory
|
||||
test = parse_script(script);
|
||||
|
||||
#ifdef JUNK
|
||||
//#ifdef JUNK
|
||||
// DEBUG - print contents of 'test'
|
||||
for (Test *tscan = test; tscan != NULL; tscan = tscan->next)
|
||||
{
|
||||
@@ -1241,7 +1333,7 @@ execute(char *script)
|
||||
printf("\n");
|
||||
fflush(stdout);
|
||||
}
|
||||
#endif
|
||||
//#endif
|
||||
|
||||
// execute tests
|
||||
return run(test);
|
||||
|
||||
Reference in New Issue
Block a user