69 Commits

Author	SHA1	Message	Date
Ross Wilson	1bd60ca4ac	Fiddling with DEIM/DSTS interia:wqctions	2018-08-05 15:00:23 +07:00
Ross Wilson	253ec3eeff	Fiddling with DEIM/DSTS interctions	2018-08-04 22:40:31 +07:00
Ross Wilson	0139097a94	Short display test program	2018-08-04 22:40:11 +07:00
Ross Wilson	334e5468f9	Remove most logging	2018-08-04 21:20:50 +07:00
Ross Wilson	9765d14209	Put timestamp into trace and log, reformatted trace output	2018-08-04 18:27:57 +07:00
Ross Wilson	c1d6ad816a	Fixed SDL 'double screen' problem	2018-08-04 14:03:57 +07:00
Ross Wilson	40d4631428	Added debug print	2018-08-03 11:52:17 +07:00
Ross Wilson	fe65fb3a0b	Title and close button, button doesn't work, TWO SCREENS?	2018-08-03 11:48:26 +07:00
Ross Wilson	e45b11c5b1	'display.h' replaces this file	2018-08-03 11:24:38 +07:00
Ross Wilson	c0eb4b03f6	First attempt at SDL screen	2018-08-03 11:00:33 +07:00
Ross Wilson	e04f227251	Modified to use new display.h	2018-08-03 10:53:28 +07:00
Ross Wilson	8559cd6f92	Added the SDL display files	2018-08-03 10:49:14 +07:00
Ross Wilson	2cad74ec6f	Ignore PBM files	2018-08-03 10:48:51 +07:00
Ross Wilson	eef9056f4f	Examining problems with DSTS instruction	2018-07-31 19:32:23 +07:00
Ross Wilson	7068eca126	Display working for some DSTS values	2018-07-30 18:50:24 +07:00
Ross Wilson	c8f8c295a4	Slowly getting bugs out of display	2018-07-29 20:11:33 +07:00
Ross Wilson	6d808fbefd	Putting pymlac trace into vimlac	2018-07-28 19:56:18 +07:00
Ross Wilson	ae6353214b	Ignore the vimlac executable	2018-07-25 18:47:57 +07:00
Ross Wilson	5435989ff3	Added full options help text	2018-07-25 16:28:55 +07:00
Ross Wilson	4f3d0de1bb	Added VIMLAC_VERSION version number	2018-07-25 16:28:43 +07:00
Ross Wilson	6607c7d3a2	Adding command line handling	2018-07-25 15:06:59 +07:00
Ross Wilson	e8aaa30362	Fixed cimpile warnings	2018-07-19 18:45:21 +07:00
Ross Wilson	e896312ac2	Get PTR test working	2016-10-21 18:48:21 +07:00
Ross Wilson	50d48ad34f	Fixed bug in test suite, test.ptr is short	2016-10-21 17:57:57 +07:00
Ross Wilson	2b9bf71448	Move to RST README files	2015-12-01 15:31:08 +07:00
Ross Wilson	c845138bef	Preparing for full emulation	2015-11-06 17:19:19 +07:00
Ross Wilson	6ea6737619	Tests now pass	2015-11-06 14:07:53 +07:00
Ross Wilson	061f235c89	All tests except line 427 OK	2015-11-06 10:58:49 +07:00
Ross Wilson	9b2af3695e	Almost a clean test	2015-11-05 20:27:52 +07:00
Ross Wilson	2bf6e1f7d1	DSL test suite mostly working, 3 errors	2015-11-05 14:53:43 +07:00
Ross Wilson	6d03e33354	Getting ptrptp.c working (and test_cpu.c)	2015-11-04 19:58:22 +07:00
Ross Wilson	147a295cff	Remove old PTR and PTP implementations	2015-11-04 19:39:20 +07:00
Ross Wilson	d95de1af6c	Debugging test on line 380, HON|HSF failing	2015-11-03 20:01:23 +07:00
Ross Wilson	82363e1a5c	Implementing new DSL instructions	2015-11-03 19:54:12 +07:00
Ross Wilson	d9adb7e0a5	Test PTR file	2015-11-03 19:53:45 +07:00
Ross Wilson	0d3e318837	Put bootstrap code into own file	2015-11-03 19:53:29 +07:00
Ross Wilson	388d582c00	Combining PTR and PTP device	2015-11-01 20:03:43 +07:00
Ross Wilson	c7cbd809ad	Implemented the multi-line assemble	2015-11-01 11:23:21 +07:00
Ross Wilson	348e51f073	Better display of progress	2015-10-28 20:14:16 +07:00
Ross Wilson	3c1dd3de0d	Fixed bugs in CPU code	2015-10-26 16:30:36 +07:00
Ross Wilson	f41cc10aca	More debug and found errors in CPU.test	2015-10-25 20:42:11 +07:00
Ross Wilson	05480a8f9c	Stiil debugging CPU	2015-10-25 14:49:17 +07:00
Ross Wilson	b2edc7796c	Made log errors more obvious, fixed setreg bug	2015-10-23 19:14:04 +07:00
Ross Wilson	3e4199634a	Changed 'checkrun' field to on/off	2015-10-23 19:12:37 +07:00
Ross Wilson	dc67bb5624	Reg/Mem checking now working, still crashes	2015-10-23 17:29:09 +07:00
Ross Wilson	60faf9027b	Fixing bugs in test_cpu.c	2015-10-23 13:55:50 +07:00
Ross Wilson	4d636df916	Working on PU test code	2015-10-23 12:21:10 +07:00
Ross Wilson	865c3e8d0d	Added cunit lib	2015-10-23 10:22:24 +07:00
Ross Wilson	bee1b9e88e	Added new tested code	2015-10-23 10:21:55 +07:00
Ross Wilson	2a834ac44f	Still fiddling with bugs	2015-10-20 13:00:41 +07:00