github.com/simh.simh
1
0
Fork 0
mirror of https://github.com/simh/simh.git synced 2026-05-01 05:48:35 +00:00
Code Releases Activity

H316, I7094, NOVA, PDP1, PDP10, PDP8, SDS: Coverity singleton errors

Browse Source 
Most history routines defined a local sim_eval of the proper length, but the
erroneous ones were fixed length machines that defined an integer variable
instead of an integer array of length 1. The VAX used the global sim_eval.
The changes follow the VAX practice.
This commit is contained in:
Bob Supnik
2017-09-07 09:52:00 -07:00
committed by Mark Pizzolato
parent f51b621f62
commit 3f8533d957
7 changed files with 33 additions and 26 deletions
Download Patch File Download Diff File Expand all files Collapse all files

9
H316/h316_cpu.c
View File

@@ -1,6 +1,6 @@
/* h316_cpu.c: Honeywell 316/516 CPU simulator /* h316_cpu.c: Honeywell 316/516 CPU simulator
Copyright (c) 1999-2015, Robert M. Supnik Copyright (c) 1999-2017, Robert M. Supnik
Permission is hereby granted, free of charge, to any person obtaining a Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"), copy of this software and associated documentation files (the "Software"),
@@ -25,6 +25,7 @@
cpu H316/H516 CPU cpu H316/H516 CPU
07-Sep-17 RMS Fixed sim_eval declaration in history routine (COVERITY)
21-May-13 RLA Add IMP/TIP support 21-May-13 RLA Add IMP/TIP support
Move SMK/OTK instructions here (from CLK) Move SMK/OTK instructions here (from CLK)
Make SET CPU DMA work as documented Make SET CPU DMA work as documented
@@ -1757,7 +1758,7 @@ t_stat cpu_show_hist (FILE *st, UNIT *uptr, int32 val, void *desc)
{ {
int32 cr, k, di, op, lnt; int32 cr, k, di, op, lnt;
char *cptr = (char *) desc; char *cptr = (char *) desc;
t_value sim_eval; extern t_value *sim_eval;
t_stat r; t_stat r;
InstHistory *h; InstHistory *h;
static uint8 has_opnd[16] = { static uint8 has_opnd[16] = {
@@ -1786,8 +1787,8 @@ for (k = 0; k < lnt; k++) { /* print specified */
if (h->pc & HIST_EA) if (h->pc & HIST_EA)
fprintf (st, "%05o ", h->ea); fprintf (st, "%05o ", h->ea);
else fprintf (st, " "); else fprintf (st, " ");
sim_eval = h->ir; sim_eval[0] = h->ir;
if ((fprint_sym (st, h->pc & X_AMASK, &sim_eval, if ((fprint_sym (st, h->pc & X_AMASK, sim_eval,
&cpu_unit, SWMASK ('M'))) > 0) &cpu_unit, SWMASK ('M'))) > 0)
fprintf (st, "(undefined) %06o", h->ir); fprintf (st, "(undefined) %06o", h->ir);
op = I_GETOP (h->ir) & 017; /* base op */ op = I_GETOP (h->ir) & 017; /* base op */

11
I7094/i7094_cpu.c
View File

@@ -1,6 +1,6 @@
/* i7094_cpu.c: IBM 7094 CPU simulator /* i7094_cpu.c: IBM 7094 CPU simulator
Copyright (c) 2003-2011, Robert M. Supnik Copyright (c) 2003-2017, Robert M. Supnik
Permission is hereby granted, free of charge, to any person obtaining a Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"), copy of this software and associated documentation files (the "Software"),
@@ -25,6 +25,7 @@
cpu 7094 central processor cpu 7094 central processor
07-Sep-17 RMS Fixed sim_eval declaration in history routine (COVERITY)
31-Dec-11 RMS Select traps have priority over protect traps 31-Dec-11 RMS Select traps have priority over protect traps
Added SRI, SPI Added SRI, SPI
Fixed user mode and relocation from CTSS RPQ documentation Fixed user mode and relocation from CTSS RPQ documentation
@@ -2400,9 +2401,9 @@ t_stat cpu_fprint_one_inst (FILE *st, uint32 pc, uint32 rpt, uint32 ea,
t_uint64 ir, t_uint64 ac, t_uint64 mq, t_uint64 si, t_uint64 opnd) t_uint64 ir, t_uint64 ac, t_uint64 mq, t_uint64 si, t_uint64 opnd)
{ {
int32 ch; int32 ch;
t_value sim_eval; extern t_value *sim_eval;
sim_eval = ir; sim_eval[0] = ir;
if (pc & HIST_PC) { /* instruction? */ if (pc & HIST_PC) { /* instruction? */
fputs ("CPU ", st); fputs ("CPU ", st);
fprintf (st, "%05o ", (int)(pc & AMASK)); fprintf (st, "%05o ", (int)(pc & AMASK));
@@ -2420,7 +2421,7 @@ if (pc & HIST_PC) { /* instruction? */
if (ir & INST_T_DEC) if (ir & INST_T_DEC)
fprintf (st, " "); fprintf (st, " ");
else fprintf (st, "%05o ", ea); else fprintf (st, "%05o ", ea);
if (fprint_sym (st, pc & AMASK, &sim_eval, &cpu_unit, SWMASK ('M')) > 0) { if (fprint_sym (st, pc & AMASK, sim_eval, &cpu_unit, SWMASK ('M')) > 0) {
fputs ("(undefined) ", st); fputs ("(undefined) ", st);
fprint_val (st, ir, 8, 36, PV_RZRO); fprint_val (st, ir, 8, 36, PV_RZRO);
} }
@@ -2436,7 +2437,7 @@ else if ((ch = HIST_CH (pc))) { /* channel? */
fprintf (st, "%05o ", (int)(pc & AMASK)); fprintf (st, "%05o ", (int)(pc & AMASK));
fputs (" ", st); fputs (" ", st);
fprintf (st, "%05o ", (int)(ea & AMASK)); fprintf (st, "%05o ", (int)(ea & AMASK));
if (fprint_sym (st, pc & AMASK, &sim_eval, &cpu_unit, if (fprint_sym (st, pc & AMASK, sim_eval, &cpu_unit,
(ch_dev[ch - 1].flags & DEV_7909)? SWMASK ('N'): SWMASK ('I')) > 0) { (ch_dev[ch - 1].flags & DEV_7909)? SWMASK ('N'): SWMASK ('I')) > 0) {
fputs ("(undefined) ", st); fputs ("(undefined) ", st);
fprint_val (st, ir, 8, 36, PV_RZRO); fprint_val (st, ir, 8, 36, PV_RZRO);

9
NOVA/nova_cpu.c
View File

@@ -1,6 +1,6 @@
/* nova_cpu.c: NOVA CPU simulator /* nova_cpu.c: NOVA CPU simulator
Copyright (c) 1993-2013, Robert M. Supnik Copyright (c) 1993-2017, Robert M. Supnik
Permission is hereby granted, free of charge, to any person obtaining a Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"), copy of this software and associated documentation files (the "Software"),
@@ -25,6 +25,7 @@
cpu Nova central processor cpu Nova central processor
07-Sep-17 RMS Fixed sim_eval declaration in history routine (COVERITY)
17-Mar-13 RMS Added clarifying brances to IND_STEP macro (Dave Bryan) 17-Mar-13 RMS Added clarifying brances to IND_STEP macro (Dave Bryan)
04-Jul-07 BKR DEV_SET/CLR macros now used, 04-Jul-07 BKR DEV_SET/CLR macros now used,
support for non-existant devices added support for non-existant devices added
@@ -1372,7 +1373,7 @@ return ( SCPE_OK ) ;
int hist_fprintf( FILE * fp, int itemNum, Hist_entry * hptr ) int hist_fprintf( FILE * fp, int itemNum, Hist_entry * hptr )
{ {
t_value sim_eval ; extern t_value *sim_eval ;
if ( hptr ) if ( hptr )
{ {
@@ -1394,8 +1395,8 @@ if ( hptr )
fprintf( fp, "%06o %06o ", SP, FP ) ; fprintf( fp, "%06o %06o ", SP, FP ) ;
} }
sim_eval = (hptr->ir & 0xFFFF) ; sim_eval[0] = (hptr->ir & 0xFFFF) ;
if ( (fprint_sym(fp, (hptr->pc & AMASK), &sim_eval, &cpu_unit, SWMASK ('M'))) > 0 ) if ( (fprint_sym(fp, (hptr->pc & AMASK), sim_eval, &cpu_unit, SWMASK ('M'))) > 0 )
{ {
fprintf( fp, "(undefined) %04o", (hptr->ir & 0xFFFF) ) ; fprintf( fp, "(undefined) %04o", (hptr->ir & 0xFFFF) ) ;
} }

9
PDP1/pdp1_cpu.c
View File

@@ -1,6 +1,6 @@
/* pdp1_cpu.c: PDP-1 CPU simulator /* pdp1_cpu.c: PDP-1 CPU simulator
Copyright (c) 1993-2015, Robert M. Supnik Copyright (c) 1993-2017, Robert M. Supnik
Permission is hereby granted, free of charge, to any person obtaining a Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"), copy of this software and associated documentation files (the "Software"),
@@ -25,6 +25,7 @@
cpu PDP-1 central processor cpu PDP-1 central processor
07-Sep-17 RMS Fixed sim_eval declaration in history routine (COVERITY)
27-Mar-15 RMS Backported changes from GitHub master 27-Mar-15 RMS Backported changes from GitHub master
21-Mar-12 RMS Fixed & vs && in Ea_ch (Michael Bloom) 21-Mar-12 RMS Fixed & vs && in Ea_ch (Michael Bloom)
30-May-07 RMS Fixed typo in SBS clear (Norm Lastovica) 30-May-07 RMS Fixed typo in SBS clear (Norm Lastovica)
@@ -1665,7 +1666,7 @@ t_stat cpu_show_hist (FILE *st, UNIT *uptr, int32 val, void *desc)
int32 ov, pf, op, k, di, lnt; int32 ov, pf, op, k, di, lnt;
char *cptr = (char *) desc; char *cptr = (char *) desc;
t_stat r; t_stat r;
t_value sim_eval; extern t_value *sim_eval;
InstHistory *h; InstHistory *h;
if (hst_lnt == 0) /* enabled? */ if (hst_lnt == 0) /* enabled? */
@@ -1691,8 +1692,8 @@ for (k = 0; k < lnt; k++) { /* print specified */
if ((op < 032) && (op != 007)) /* mem ref instr */ if ((op < 032) && (op != 007)) /* mem ref instr */
fprintf (st, "%06o ", h->ea); fprintf (st, "%06o ", h->ea);
else fprintf (st, " "); else fprintf (st, " ");
sim_eval = h->ir; sim_eval[0] = h->ir;
if ((fprint_sym (st, h->pc & AMASK, &sim_eval, &cpu_unit, SWMASK ('M'))) > 0) if ((fprint_sym (st, h->pc & AMASK, sim_eval, &cpu_unit, SWMASK ('M'))) > 0)
fprintf (st, "(undefined) %06o", h->ir); fprintf (st, "(undefined) %06o", h->ir);
else if (op < 030) /* mem ref instr */ else if (op < 030) /* mem ref instr */
fprintf (st, " [%06o]", h->opnd); fprintf (st, " [%06o]", h->opnd);

7
PDP10/pdp10_cpu.c
View File

@@ -25,6 +25,7 @@
cpu KS10 central processor cpu KS10 central processor
07-Sep-17 RMS Fixed sim_eval declaration in history routine (COVERITY)
14-Jan-17 RMS Fixed bugs in 1-proceed 14-Jan-17 RMS Fixed bugs in 1-proceed
09-Feb-16 RMS Fixed nested indirects and executes (Tim Litt) 09-Feb-16 RMS Fixed nested indirects and executes (Tim Litt)
25-Mar-12 RMS Added missing parameters to prototypes (Mark Pizzolato) 25-Mar-12 RMS Added missing parameters to prototypes (Mark Pizzolato)
@@ -2478,7 +2479,7 @@ t_stat cpu_show_hist (FILE *st, UNIT *uptr, int32 val, void *desc)
int32 k, di, lnt; int32 k, di, lnt;
char *cptr = (char *) desc; char *cptr = (char *) desc;
t_stat r; t_stat r;
t_value sim_eval; extern t_value *sim_eval;
InstHistory *h; InstHistory *h;
if (hst_lnt == 0) /* enabled? */ if (hst_lnt == 0) /* enabled? */
@@ -2500,8 +2501,8 @@ for (k = 0; k < lnt; k++) { /* print specified */
fprint_val (st, h->ac, 8, 36, PV_RZRO); fprint_val (st, h->ac, 8, 36, PV_RZRO);
fputs (" ", st); fputs (" ", st);
fprintf (st, "%06o ", h->ea); fprintf (st, "%06o ", h->ea);
sim_eval = h->ir; sim_eval[0] = h->ir;
if ((fprint_sym (st, h->pc & AMASK, &sim_eval, &cpu_unit, SWMASK ('M'))) > 0) { if ((fprint_sym (st, h->pc & AMASK, sim_eval, &cpu_unit, SWMASK ('M'))) > 0) {
fputs ("(undefined) ", st); fputs ("(undefined) ", st);
fprint_val (st, h->ir, 8, 36, PV_RZRO); fprint_val (st, h->ir, 8, 36, PV_RZRO);
} }

7
PDP8/pdp8_cpu.c
View File

@@ -25,6 +25,7 @@
cpu central processor cpu central processor
07-Sep-17 RMS Fixed sim_eval declaration in history routine (COVERITY)
09-Mar-17 RMS Fixed PCQ_ENTRY for interrupts (COVERITY) 09-Mar-17 RMS Fixed PCQ_ENTRY for interrupts (COVERITY)
13-Feb-17 RMS RESET clear L'AC, per schematics 13-Feb-17 RMS RESET clear L'AC, per schematics
28-Jan-17 RMS Renamed switch register variable to SR, per request 28-Jan-17 RMS Renamed switch register variable to SR, per request
@@ -1576,7 +1577,7 @@ t_stat cpu_show_hist (FILE *st, UNIT *uptr, int32 val, void *desc)
int32 l, k, di, lnt; int32 l, k, di, lnt;
char *cptr = (char *) desc; char *cptr = (char *) desc;
t_stat r; t_stat r;
t_value sim_eval; extern t_value *sim_eval;
InstHistory *h; InstHistory *h;
if (hst_lnt == 0) /* enabled? */ if (hst_lnt == 0) /* enabled? */
@@ -1599,8 +1600,8 @@ for (k = 0; k < lnt; k++) { /* print specified */
if (h->ir < 06000) if (h->ir < 06000)
fprintf (st, "%05o ", h->ea); fprintf (st, "%05o ", h->ea);
else fprintf (st, " "); else fprintf (st, " ");
sim_eval = h->ir; sim_eval[0] = h->ir;
if ((fprint_sym (st, h->pc & ADDRMASK, &sim_eval, &cpu_unit, SWMASK ('M'))) > 0) if ((fprint_sym (st, h->pc & ADDRMASK, sim_eval, &cpu_unit, SWMASK ('M'))) > 0)
fprintf (st, "(undefined) %04o", h->ir); fprintf (st, "(undefined) %04o", h->ir);
if (h->ir < 04000) if (h->ir < 04000)
fprintf (st, " [%04o]", h->opnd); fprintf (st, " [%04o]", h->opnd);

7
SDS/sds_cpu.c
View File

@@ -26,6 +26,7 @@
cpu central processor cpu central processor
rtc real time clock rtc real time clock
07-Sep-17 RMS Fixed sim_eval declaration in history routine (COVERITY)
09-Mar-17 RMS trap_P not set if mem mgt trap during fetch (COVERITY) 09-Mar-17 RMS trap_P not set if mem mgt trap during fetch (COVERITY)
28-Apr-07 RMS Removed clock initialization 28-Apr-07 RMS Removed clock initialization
29-Dec-06 RMS Fixed breakpoint variable declarations 29-Dec-06 RMS Fixed breakpoint variable declarations
@@ -1746,7 +1747,7 @@ t_stat cpu_show_hist (FILE *st, UNIT *uptr, int32 val, void *desc)
int32 ov, k, di, lnt; int32 ov, k, di, lnt;
char *cptr = (char *) desc; char *cptr = (char *) desc;
t_stat r; t_stat r;
t_value sim_eval; extern t_value *sim_eval;
InstHistory *h; InstHistory *h;
static char *cyc[] = { " ", " ", "INT", "TRP" }; static char *cyc[] = { " ", " ", "INT", "TRP" };
static char *modes = "NMU?"; static char *modes = "NMU?";
@@ -1772,8 +1773,8 @@ for (k = 0; k < lnt; k++) { /* print specified */
if (h->ea & HIST_NOEA) if (h->ea & HIST_NOEA)
fprintf (st, " "); fprintf (st, " ");
else fprintf (st, "%05o ", h->ea); else fprintf (st, "%05o ", h->ea);
sim_eval = h->ir; sim_eval[0] = h->ir;
if ((fprint_sym (st, h->pc, &sim_eval, &cpu_unit, SWMASK ('M'))) > 0) if ((fprint_sym (st, h->pc, sim_eval, &cpu_unit, SWMASK ('M'))) > 0)
fprintf (st, "(undefined) %08o", h->ir); fprintf (st, "(undefined) %08o", h->ir);
fputc ('\n', st); /* end line */ fputc ('\n', st); /* end line */
} /* end else instruction */ } /* end else instruction */