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VAX: Correctly process long interval timer delays and fudge TODR reads from ROM
This commit is contained in:
Mark Pizzolato
@@ -211,10 +211,6 @@ static BITFIELD tmr_csr_bits[] = {
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};
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/* SSC timer intervals */
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#define TMR_INC 10000U /* usec/interval */
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/* SSC timer vector */
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#define TMR_VEC_MASK 0x000003FC /* vector */
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@@ -248,6 +244,7 @@ uint32 tmr_tir[2] = { 0 }; /* curr interval */
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uint32 tmr_tnir[2] = { 0 }; /* next interval */
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int32 tmr_tivr[2] = { 0 }; /* vector */
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t_bool tmr_inst[2] = { 0 }; /* wait instructions vs usecs */
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uint32 tmr_inst_remain[2] = { 0 }; /* wait instructions remaining */
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int32 ssc_adsm[2] = { 0 }; /* addr strobes */
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int32 ssc_adsk[2] = { 0 };
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int32 cdg_dat[CDASIZE >> 2]; /* cache data */
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@@ -295,6 +292,7 @@ int32 tmr_tir_rd (int32 tmr);
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void tmr_csr_wr (int32 tmr, int32 val);
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int32 tmr_csr_rd (int32 tmr);
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void tmr_sched (int32 tmr);
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void tmr_sched_inst (int32 tmr, uint32 usecs);
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void tmr_incr (int32 tmr, uint32 inc);
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int32 tmr0_inta (void);
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int32 tmr1_inta (void);
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@@ -484,11 +482,13 @@ REG sysd_reg[] = {
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{ HRDATAD (TNIR0, tmr_tnir[0], 32, "SSC timer 0 next interval register") },
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{ HRDATAD (TIVEC0, tmr_tivr[0], 9, "SSC timer 0 interrupt vector register") },
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{ FLDATAD (TINST0, tmr_inst[0], 0, "SSC timer 0 last wait instructions") },
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{ FLDATAD (TINSTR0, tmr_inst_remain[0], 0, "SSC timer 0 wait instructions remaining") },
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{ HRDATADF (TCSR1, tmr_csr[1], 32, "SSC timer 1 control/status register", tmr_csr_bits) },
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{ HRDATAD (TIR1, tmr_tir[1], 32, "SSC timer 1 interval register") },
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{ HRDATAD (TNIR1, tmr_tnir[1], 32, "SSC timer 1 next interval register") },
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{ HRDATAD (TIVEC1, tmr_tivr[1], 9, "SSC timer 1 interrupt vector register") },
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{ FLDATAD (TINST1, tmr_inst[1], 0, "SSC timer 1 last wait instructions") },
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{ FLDATAD (TINSTR1, tmr_inst_remain[1], 0, "SSC timer 1 wait instructions remaining") },
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{ HRDATAD (ADSM0, ssc_adsm[0], 32, "SSC address match 0 address") },
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{ HRDATAD (ADSK0, ssc_adsk[0], 32, "SSC address match 0 mask") },
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{ HRDATAD (ADSM1, ssc_adsm[1], 32, "SSC address match 1 address") },
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@@ -892,6 +892,8 @@ switch (rg) {
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case MT_TODR: /* TODR */
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val = todr_rd ();
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if (ADDR_IS_ROM(fault_PC)) /* running from ROM */
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val = 1 + (sim_grtime () / 10000); /* instruction count presuming 1 usec per instruction 10 ms tick (non-zero) */
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sim_debug (DBG_TODR, &sysd_dev, "ReadIPR() = 0x%X\n", val);
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break;
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@@ -1483,7 +1485,7 @@ switch (rg) {
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that ROM based code execute instructions at 1 instruction per usec.
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To accommodate this, we not only throttle memory accesses to ROM space,
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but we also use instruction based delays when the interval timers are
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programmed from the ROM for short duration delays.
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programmed from the ROM.
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*/
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int32 tmr_tir_rd (int32 tmr)
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@@ -1491,22 +1493,26 @@ int32 tmr_tir_rd (int32 tmr)
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if (tmr_csr[tmr] & TMR_CSR_RUN) { /* running? then interpolate */
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uint32 usecs_remaining, cur_tir;
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const char *tmr_units = NULL;
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const char *tmr_how = NULL;
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if ((ADDR_IS_ROM(fault_PC)) && /* running from ROM and */
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(tmr_inst[tmr])) { /* waiting instructions? */
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usecs_remaining = sim_activate_time (&sysd_dev.units[tmr]) - 1;
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usecs_remaining += tmr_inst_remain[tmr];
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tmr_units = "Instructions";
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tmr_how = "";
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}
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else {
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usecs_remaining = (uint32)(0xFFFFFFFFLL & (t_uint64)sim_activate_time_usecs (&sysd_dev.units[tmr]));
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tmr_units = "Microseconds";
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tmr_how = ", Interpolated while running";
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}
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cur_tir = ~usecs_remaining + 1;
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sim_debug (DBG_REGR, &sysd_dev, "tmr_tir_rd(tmr=%d) - 0x%X %s - %u usecs, Interpolated while running\n", tmr, cur_tir, tmr_units, usecs_remaining);
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sim_debug (DBG_REGR, &sysd_dev, "tmr_tir_rd(tmr=%d) - %u(0x%X) %s - %u(0x%X) usecs%s\n", tmr, cur_tir, cur_tir, tmr_units, usecs_remaining, usecs_remaining, tmr_how);
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return cur_tir;
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}
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sim_debug (DBG_REGR, &sysd_dev, "tmr_tir_rd(tmr=%d) - 0x%X\n", tmr, tmr_tir[tmr]);
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sim_debug (DBG_REGR, &sysd_dev, "tmr_tir_rd(tmr=%d) - %u(0x%X)\n", tmr, tmr_tir[tmr], tmr_tir[tmr]);
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return tmr_tir[tmr];
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}
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@@ -1533,6 +1539,7 @@ if ((val & TMR_CSR_RUN) == 0) { /* clearing run? */
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if (tmr_csr[tmr] & TMR_CSR_RUN) /* run 1 -> 0? */
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tmr_tir[tmr] = tmr_tir_rd (tmr); /* update itr */
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sim_cancel (&sysd_unit[tmr]); /* cancel timer */
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tmr_inst_remain[tmr] = 0;
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}
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tmr_csr[tmr] = tmr_csr[tmr] & ~(val & TMR_CSR_W1C); /* W1C csr */
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tmr_csr[tmr] = (tmr_csr[tmr] & ~TMR_CSR_RW) | /* new r/w */
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@@ -1544,8 +1551,10 @@ if (val & TMR_CSR_XFR) { /* xfr set? */
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sim_debug (DBG_REGW, &sysd_dev, "tmr_csr_wr(tmr=%d) - XFR set TIR=0x%X\n", tmr, tmr_tir[tmr]);
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}
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if (val & TMR_CSR_RUN) { /* run? */
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if (val & TMR_CSR_XFR) /* new tir? */
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if (val & TMR_CSR_XFR) { /* new tir? */
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sim_cancel (&sysd_unit[tmr]); /* stop prev */
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tmr_inst_remain[tmr] = 0;
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}
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if (!sim_is_active (&sysd_unit[tmr])) /* not running? */
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tmr_sched (tmr); /* activate */
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}
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@@ -1572,7 +1581,10 @@ t_stat tmr_svc (UNIT *uptr)
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int32 tmr = uptr - sysd_dev.units; /* get timer # */
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uint32 delta_usecs = ~tmr_tir[tmr] + 1;
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tmr_incr (tmr, delta_usecs); /* incr timer */
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if (tmr_inst_remain[tmr])
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tmr_sched_inst (tmr, tmr_inst_remain[tmr]); /* schedule remaining usecs */
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else
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tmr_incr (tmr, delta_usecs); /* incr timer */
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return SCPE_OK;
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}
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@@ -1611,16 +1623,28 @@ else {
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/* Timer scheduling */
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void tmr_sched_inst (int32 tmr, uint32 usecs)
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{
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if (usecs & 0x80000000) { /* High bit set? */
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sim_activate_abs (&sysd_unit[tmr], usecs >> 1);
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tmr_inst_remain[tmr] = usecs - (usecs >> 1);
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sim_debug (DBG_SCHD, &sysd_dev, "tmr_sched_inst(tmr=%d) - scheduling for %u instructions with %u remaining\n", tmr, (usecs >> 1), tmr_inst_remain[tmr]);
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}
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else {
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sim_activate_abs (&sysd_unit[tmr], usecs);
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tmr_inst_remain[tmr] = 0;
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}
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}
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void tmr_sched (int32 tmr)
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{
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uint32 usecs_sched = tmr_tir[tmr] ? (~tmr_tir[tmr] + 1) : 0xFFFFFFFF;
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double usecs_sched_d = tmr_tir[tmr] ? (double)(~tmr_tir[tmr] + 1) : (1.0 + (double)0xFFFFFFFFu);
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sim_cancel (&sysd_unit[tmr]); /* Make sure not active */
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if ((ADDR_IS_ROM(fault_PC)) && /* running from ROM and */
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(usecs_sched < TMR_INC)) { /* short delay? */
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if (ADDR_IS_ROM(fault_PC)) { /* running from ROM */
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tmr_inst[tmr] = TRUE; /* wait for instructions */
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sim_activate (&sysd_unit[tmr], usecs_sched);
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tmr_sched_inst (tmr, usecs_sched);
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sim_debug (DBG_SCHD, &sysd_dev, "tmr_sched(tmr=%d) - after %u instructions - activate after: %.0f usecs\n", tmr, usecs_sched, sim_activate_time_usecs (&sysd_unit[tmr]));
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}
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else {
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@@ -1763,6 +1787,7 @@ if (sim_switches & SWMASK ('P')) sysd_powerup (); /* powerup? */
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for (i = 0; i < 2; i++) {
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tmr_csr[i] = tmr_tnir[i] = tmr_tir[i] = 0;
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tmr_inst[i] = FALSE;
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tmr_inst_remain[i] = 0;
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sim_cancel (&sysd_unit[i]);
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}
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csi_csr = 0;
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