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Code Releases Activity

I650: Fix Coverity Warning

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This commit is contained in:
Roberto Sancho Villa
2018-05-07 23:30:02 +02:00
parent cc0e993978
commit 7a8d61746d
1 changed files with 3 additions and 3 deletions
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6
I650/i650_cpu.c
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@@ -924,7 +924,7 @@ sim_instr(void)
break; break;
} }
// should wait for drum to fetch inst? // should wait for drum to fetch inst?
if (AR < (int)MEMSIZE) { if (AR < MEMSIZE) {
if ((AR % 50) != DrumAddr) continue; // yes if ((AR % 50) != DrumAddr) continue; // yes
} }
CpuStepsUsed = 0; // init inst execution CpuStepsUsed = 0; // init inst execution
@@ -938,7 +938,7 @@ sim_instr(void)
WaitForInterlock = 0; WaitForInterlock = 0;
} }
// should wait for drum to fetch data? // should wait for drum to fetch data?
if ((bReadData) && (AR >= 0) && (AR < (int)MEMSIZE)) { if ((bReadData) && (AR < MEMSIZE)) {
if ((AR % 50) != DrumAddr) continue; // yes if ((AR % 50) != DrumAddr) continue; // yes
} }
MachineCycle = 3; // exec instr MachineCycle = 3; // exec instr
@@ -946,7 +946,7 @@ sim_instr(void)
// should wait for cpu to exec the inst? // should wait for cpu to exec the inst?
if (CpuStepsUsed > 0) {CpuStepsUsed--; continue;} // yes if (CpuStepsUsed > 0) {CpuStepsUsed--; continue;} // yes
// should wait for drum to store data? // should wait for drum to store data?
if ((bWriteDrum) && (AR >= 0) && (AR < (int)MEMSIZE)) { if ((bWriteDrum) && (AR < MEMSIZE)) {
if ((AR % 50) != DrumAddr) continue; // yes if ((AR % 50) != DrumAddr) continue; // yes
} }
MachineCycle = 5; // terminate the instr execution MachineCycle = 5; // terminate the instr execution