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All VAXen: Properly set the interrupt latency based on the TODR updates

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The interval timer is not a calibrated clock and thus should not be the
basis for reasonably expected instruction execution rate computations.
This commit is contained in:
Mark Pizzolato 2023-06-27 13:01:18 -10:00
parent 008ecc4e8b
commit a7c789caec
10 changed files with 49 additions and 79 deletions
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14
VAX/vax4nn_stddev.c
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@ -392,14 +392,11 @@ return;
t_stat clk_svc (UNIT *uptr)
{
int32 t;
if (clk_csr & CSR_IE)
tmr_int = 1;
t = sim_rtcn_calb (clk_tps, TMR_CLK); /* calibrate clock */
tmr_poll = sim_rtcn_calb (clk_tps, TMR_CLK); /* calibrate clock */
sim_activate_after (uptr, 1000000/clk_tps); /* reactivate unit */
tmr_poll = t; /* set tmr poll */
tmxr_poll = t * TMXR_MULT; /* set mux poll */
tmxr_poll = tmr_poll * TMXR_MULT; /* set mux poll */
AIO_SET_INTERRUPT_LATENCY(tmr_poll*clk_tps); /* set interrrupt latency */
return SCPE_OK;
}
@ -408,14 +405,11 @@ return SCPE_OK;
t_stat clk_reset (DEVICE *dptr)
{
int32 t;
clk_csr = 0;
tmr_int = 0;
t = sim_rtcn_init_unit (&clk_unit, clk_unit.wait, TMR_CLK);/* init 100Hz timer */
tmr_poll = sim_rtcn_init_unit (&clk_unit, clk_unit.wait, TMR_CLK);/* init 100Hz timer */
sim_activate_after (&clk_unit, 1000000/clk_tps); /* activate 100Hz unit */
tmr_poll = t; /* set tmr poll */
tmxr_poll = t * TMXR_MULT; /* set mux poll */
tmxr_poll = tmr_poll * TMXR_MULT; /* set mux poll */
return SCPE_OK;
}

14
VAX/vax4xx_stddev.c
View File

@ -509,14 +509,11 @@ return;
t_stat clk_svc (UNIT *uptr)
{
int32 t;
if (clk_csr & CSR_IE)
tmr_int = 1;
t = sim_rtcn_calb (clk_tps, TMR_CLK); /* calibrate clock */
tmr_poll = sim_rtcn_calb (clk_tps, TMR_CLK); /* calibrate clock */
sim_activate_after (uptr, 1000000/clk_tps); /* reactivate unit */
tmr_poll = t; /* set tmr poll */
tmxr_poll = t * TMXR_MULT; /* set mux poll */
tmxr_poll = tmr_poll * TMXR_MULT; /* set mux poll */
AIO_SET_INTERRUPT_LATENCY(tmr_poll*clk_tps); /* set interrrupt latency */
return SCPE_OK;
}
@ -525,14 +522,11 @@ return SCPE_OK;
t_stat clk_reset (DEVICE *dptr)
{
int32 t;
clk_csr = 0;
tmr_int = 0;
t = sim_rtcn_init_unit (&clk_unit, clk_unit.wait, TMR_CLK);/* init 100Hz timer */
tmr_poll = sim_rtcn_init_unit (&clk_unit, clk_unit.wait, TMR_CLK);/* init 100Hz timer */
sim_activate_after (&clk_unit, 1000000/clk_tps); /* activate 100Hz unit */
tmr_poll = t; /* set tmr poll */
tmxr_poll = t * TMXR_MULT; /* set mux poll */
tmxr_poll = tmr_poll * TMXR_MULT; /* set mux poll */
return SCPE_OK;
}

14
VAX/vax610_stddev.c
View File

@ -436,14 +436,11 @@ return "console terminal output";
t_stat clk_svc (UNIT *uptr)
{
int32 t;
if (clk_csr & CSR_IE)
SET_INT (CLK);
t = sim_rtcn_calb (clk_tps, TMR_CLK); /* calibrate clock */
tmr_poll = sim_rtcn_calb (clk_tps, TMR_CLK); /* calibrate clock */
sim_activate_after (uptr, 1000000/clk_tps); /* reactivate unit */
tmr_poll = t; /* set tmr poll */
tmxr_poll = t * TMXR_MULT; /* set mux poll */
tmxr_poll = tmr_poll * TMXR_MULT; /* set mux poll */
AIO_SET_INTERRUPT_LATENCY(tmr_poll*clk_tps); /* set interrrupt latency */
return SCPE_OK;
}
@ -452,14 +449,11 @@ return SCPE_OK;
t_stat clk_reset (DEVICE *dptr)
{
int32 t;
clk_csr = 0;
CLR_INT (CLK);
t = sim_rtcn_init_unit (&clk_unit, clk_unit.wait, TMR_CLK);/* init 100Hz timer */
tmr_poll = sim_rtcn_init_unit (&clk_unit, clk_unit.wait, TMR_CLK);/* init 100Hz timer */
sim_activate_after (&clk_unit, 1000000/clk_tps); /* activate 100Hz unit */
tmr_poll = t; /* set tmr poll */
tmxr_poll = t * TMXR_MULT; /* set mux poll */
tmxr_poll = tmr_poll * TMXR_MULT; /* set mux poll */
return SCPE_OK;
}

14
VAX/vax630_stddev.c
View File

@ -379,14 +379,11 @@ return "console terminal output";
t_stat clk_svc (UNIT *uptr)
{
int32 t;
if (clk_csr & CSR_IE)
SET_INT (CLK);
t = sim_rtcn_calb (clk_tps, TMR_CLK); /* calibrate clock */
tmr_poll = sim_rtcn_calb (clk_tps, TMR_CLK); /* calibrate clock */
sim_activate_after (uptr, 1000000/clk_tps); /* reactivate unit */
tmr_poll = t; /* set tmr poll */
tmxr_poll = t * TMXR_MULT; /* set mux poll */
tmxr_poll = tmr_poll * TMXR_MULT; /* set mux poll */
AIO_SET_INTERRUPT_LATENCY(tmr_poll*clk_tps); /* set interrrupt latency */
return SCPE_OK;
}
@ -395,14 +392,11 @@ return SCPE_OK;
t_stat clk_reset (DEVICE *dptr)
{
int32 t;
clk_csr = 0;
CLR_INT (CLK);
t = sim_rtcn_init_unit (&clk_unit, clk_unit.wait, TMR_CLK);/* init 100Hz timer */
tmr_poll = sim_rtcn_init_unit (&clk_unit, clk_unit.wait, TMR_CLK);/* init 100Hz timer */
sim_activate_after (&clk_unit, 1000000/clk_tps); /* activate 100Hz unit */
tmr_poll = t; /* set tmr poll */
tmxr_poll = t * TMXR_MULT; /* set mux poll */
tmxr_poll = tmr_poll * TMXR_MULT; /* set mux poll */
return SCPE_OK;
}

12
VAX/vax730_stddev.c
View File

@ -568,7 +568,7 @@ tmxr_set_console_units (&tti_unit, &tto_unit);
tti_buf = 0;
tti_csr = 0;
tti_int = 0;
sim_activate (&tti_unit, tmr_poll);
sim_activate (&tti_unit, tmxr_poll);
return SCPE_OK;
}
@ -735,7 +735,6 @@ tmr_nicr = val;
t_stat tmr_svc (UNIT *uptr)
{
sim_debug (TMR_DB_TICK, &tmr_dev, "tmr_svc()\n");
tmxr_poll = tmr_poll * TMXR_MULT; /* set mux poll */
if (tmr_iccs & TMR_CSR_DON) /* done? set err */
tmr_iccs = tmr_iccs | TMR_CSR_ERR;
else
@ -748,7 +747,6 @@ if (tmr_iccs & TMR_CSR_IE) { /* ie? set int req */
}
else
tmr_int = 0;
AIO_SET_INTERRUPT_LATENCY(tmr_poll*clk_tps); /* set interrrupt latency */
return SCPE_OK;
}
@ -779,14 +777,16 @@ if ((clk_unit.filebuf == NULL) || /* make sure the TODR is
todr_resync ();
sim_activate_after (&clk_unit, 10000);
tmr_poll = sim_rtcn_init_unit (&clk_unit, CLK_DELAY, TMR_CLK); /* init timer */
tmxr_poll = tmr_poll * TMXR_MULT; /* set mux poll */
return SCPE_OK;
}
t_stat clk_svc (UNIT *uptr)
{
tmr_poll = sim_rtcn_calb (100, TMR_CLK);
sim_activate_after (uptr, 10000);
tmxr_poll = tmr_poll * TMXR_MULT; /* set mux poll */
tmr_poll = sim_rtcn_calb (clk_tps, TMR_CLK);
sim_activate_after (uptr, 1000000 / clk_tps); /* 10000 usecs */
tmxr_poll = tmr_poll * TMXR_MULT; /* set mux poll */
AIO_SET_INTERRUPT_LATENCY(tmr_poll*100); /* set interrrupt latency */
return SCPE_OK;
}

10
VAX/vax750_stddev.c
View File

@ -730,7 +730,6 @@ tmr_nicr = val;
t_stat tmr_svc (UNIT *uptr)
{
sim_debug (TMR_DB_TICK, &tmr_dev, "tmr_svc()\n");
tmxr_poll = tmr_poll * TMXR_MULT; /* set mux poll */
if (tmr_iccs & TMR_CSR_DON) /* done? set err */
tmr_iccs = tmr_iccs | TMR_CSR_ERR;
else
@ -743,7 +742,6 @@ if (tmr_iccs & TMR_CSR_IE) { /* ie? set int req */
}
else
tmr_int = 0;
AIO_SET_INTERRUPT_LATENCY(tmr_poll*clk_tps); /* set interrrupt latency */
return SCPE_OK;
}
@ -774,14 +772,16 @@ if ((clk_unit.filebuf == NULL) || /* make sure the TODR is
todr_resync ();
sim_activate_after (&clk_unit, 10000);
tmr_poll = sim_rtcn_init_unit (&clk_unit, CLK_DELAY, TMR_CLK); /* init timer */
tmxr_poll = tmr_poll * TMXR_MULT; /* set mux poll */
return SCPE_OK;
}
t_stat clk_svc (UNIT *uptr)
{
tmr_poll = sim_rtcn_calb (100, TMR_CLK);
sim_activate_after (uptr, 10000);
tmxr_poll = tmr_poll * TMXR_MULT; /* set mux poll */
tmr_poll = sim_rtcn_calb (clk_tps, TMR_CLK);
sim_activate_after (uptr, 1000000 / clk_tps); /* 10000 usecs */
tmxr_poll = tmr_poll * TMXR_MULT; /* set mux poll */
AIO_SET_INTERRUPT_LATENCY(tmr_poll*100); /* set interrrupt latency */
return SCPE_OK;
}

11
VAX/vax780_stddev.c
View File

@ -549,7 +549,7 @@ tmxr_set_console_units (&tti_unit, &tto_unit);
tti_buf = 0;
tti_csr = 0;
tti_int = 0;
sim_activate (&tti_unit, tmr_poll);
sim_activate (&tti_unit, tmxr_poll);
return SCPE_OK;
}
@ -730,7 +730,6 @@ if (tmr_iccs & TMR_CSR_IE) { /* ie? set int req */
}
else
tmr_int = 0;
AIO_SET_INTERRUPT_LATENCY(tmr_poll*clk_tps); /* set interrrupt latency */
return SCPE_OK;
}
@ -761,14 +760,16 @@ if ((clk_unit.filebuf == NULL) || /* make sure the TODR is
todr_resync ();
sim_activate_after (&clk_unit, 10000);
tmr_poll = sim_rtcn_init_unit (&clk_unit, CLK_DELAY, TMR_CLK); /* init timer */
tmxr_poll = tmr_poll * TMXR_MULT; /* set mux poll */
return SCPE_OK;
}
t_stat clk_svc (UNIT *uptr)
{
tmr_poll = sim_rtcn_calb (100, TMR_CLK);
sim_activate_after (uptr, 10000);
tmxr_poll = tmr_poll * TMXR_MULT; /* set mux poll */
tmr_poll = sim_rtcn_calb (clk_tps, TMR_CLK);
sim_activate_after (uptr, 1000000 / clk_tps); /* 10000 usecs */
tmxr_poll = tmr_poll * TMXR_MULT; /* set mux poll */
AIO_SET_INTERRUPT_LATENCY(tmr_poll*100); /* set interrrupt latency */
return SCPE_OK;
}

12
VAX/vax820_stddev.c
View File

@ -559,7 +559,7 @@ tmxr_set_console_units (&tti_unit, &tto_unit[0]);
tti_buf = 0;
tti_csr = 0;
tti_int = 0;
sim_activate (&tti_unit, tmr_poll);
sim_activate (&tti_unit, tmxr_poll);
return SCPE_OK;
}
@ -733,7 +733,6 @@ tmr_nicr = val;
t_stat tmr_svc (UNIT *uptr)
{
sim_debug (TMR_DB_TICK, &tmr_dev, "tmr_svc()\n");
tmxr_poll = tmr_poll * TMXR_MULT; /* set mux poll */
if (tmr_iccs & TMR_CSR_DON) /* done? set err */
tmr_iccs = tmr_iccs | TMR_CSR_ERR;
else
@ -746,7 +745,6 @@ if (tmr_iccs & TMR_CSR_IE) { /* ie? set int req */
}
else
tmr_int = 0;
AIO_SET_INTERRUPT_LATENCY(tmr_poll*clk_tps); /* set interrrupt latency */
return SCPE_OK;
}
@ -781,14 +779,16 @@ else
wtc_set_invalid ();
sim_activate_after (&clk_unit, 10000);
tmr_poll = sim_rtcn_init_unit (&clk_unit, CLK_DELAY, TMR_CLK); /* init timer */
tmxr_poll = tmr_poll * TMXR_MULT; /* set mux poll */
return SCPE_OK;
}
t_stat clk_svc (UNIT *uptr)
{
tmr_poll = sim_rtcn_calb (100, TMR_CLK);
sim_activate_after (uptr, 10000);
tmxr_poll = tmr_poll * TMXR_MULT; /* set mux poll */
tmr_poll = sim_rtcn_calb (clk_tps, TMR_CLK);
sim_activate_after (uptr, 1000000 / clk_tps); /* 10000 usecs */
tmxr_poll = tmr_poll * TMXR_MULT; /* set mux poll */
AIO_SET_INTERRUPT_LATENCY(tmr_poll*100); /* set interrrupt latency */
return SCPE_OK;
}

11
VAX/vax860_stddev.c
View File

@ -658,7 +658,7 @@ tmxr_set_console_units (tti_unit, tto_unit);
tti_buf = 0;
tti_csr = 0;
tti_int = 0;
sim_activate (&tti_unit[ID_CT], tmr_poll);
sim_activate (&tti_unit[ID_CT], tmxr_poll);
return SCPE_OK;
}
@ -839,7 +839,6 @@ tmr_nicr = val;
t_stat tmr_svc (UNIT *uptr)
{
sim_debug (TMR_DB_TICK, &tmr_dev, "tmr_svc()\n");
tmxr_poll = tmr_poll * TMXR_MULT; /* set mux poll */
if (tmr_iccs & TMR_CSR_DON) /* done? set err */
tmr_iccs = tmr_iccs | TMR_CSR_ERR;
else
@ -852,7 +851,6 @@ if (tmr_iccs & TMR_CSR_IE) { /* ie? set int req */
}
else
tmr_int = 0;
AIO_SET_INTERRUPT_LATENCY(tmr_poll*clk_tps); /* set interrrupt latency */
return SCPE_OK;
}
@ -888,9 +886,10 @@ return SCPE_OK;
t_stat clk_svc (UNIT *uptr)
{
tmr_poll = sim_rtcn_calb (100, TMR_CLK);
sim_activate_after (uptr, 10000);
tmxr_poll = tmr_poll * TMXR_MULT; /* set mux poll */
tmr_poll = sim_rtcn_calb (clk_tps, TMR_CLK);
sim_activate_after (uptr, 1000000 / clk_tps); /* 10000 usecs */
tmxr_poll = tmr_poll * TMXR_MULT; /* set mux poll */
AIO_SET_INTERRUPT_LATENCY(tmr_poll*100); /* set interrrupt latency */
return SCPE_OK;
}

16
VAX/vax_stddev.c
View File

@ -371,7 +371,7 @@ tmxr_set_console_units (&tti_unit, &tto_unit);
tti_unit.buf = 0;
tti_csr = 0;
CLR_INT (TTI);
sim_activate (&tti_unit, tmr_poll);
sim_activate (&tti_unit, tmxr_poll);
return SCPE_OK;
}
@ -454,14 +454,11 @@ return "console terminal output";
t_stat clk_svc (UNIT *uptr)
{
int32 t;
if (clk_csr & CSR_IE)
SET_INT (CLK);
t = sim_rtcn_calb (clk_tps, TMR_CLK); /* calibrate clock */
tmr_poll = sim_rtcn_calb (clk_tps, TMR_CLK); /* calibrate clock */
sim_activate_after (&clk_unit, 1000000/clk_tps); /* reactivate unit */
tmr_poll = t; /* set tmr poll */
tmxr_poll = t * TMXR_MULT; /* set mux poll */
tmxr_poll = tmr_poll * TMXR_MULT; /* set mux poll */
if (!todr_blow && todr_reg) /* if running? */
todr_reg = todr_reg + 1; /* incr TODR */
AIO_SET_INTERRUPT_LATENCY(tmr_poll*clk_tps); /* set interrrupt latency */
@ -569,15 +566,12 @@ return SCPE_OK;
t_stat clk_reset (DEVICE *dptr)
{
int32 t;
clk_csr = 0;
CLR_INT (CLK);
if (!sim_is_running) { /* RESET (not IORESET)? */
t = sim_rtcn_init_unit (&clk_unit, clk_unit.wait, TMR_CLK);/* init 100Hz timer */
tmr_poll = sim_rtcn_init_unit (&clk_unit, clk_unit.wait, TMR_CLK);/* init 100Hz timer */
sim_activate_after (&clk_unit, 1000000/clk_tps); /* activate 100Hz unit */
tmr_poll = t; /* set tmr poll */
tmxr_poll = t * TMXR_MULT; /* set mux poll */
tmxr_poll = tmr_poll * TMXR_MULT; /* set mux poll */
}
if ((clk_unit.filebuf == NULL) || /* make sure the TODR is initialized */
(sim_switches & SWMASK ('P'))) {