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VAX: Fix for unaligned memory reference to IO and Register Space (from Bob Supnik)
Design Notes for Fixing VAX Unaligned Access to IO and Register Space
Problem Statement: VAX unaligned accesses are handled by reading the
surrounding longword (or longwords) and
a) for reads, extracting the addressed addressed word or longword
b) for writes, inserting the addressed word or longword and then
writing the surrounding longword (or longwords) back
This is correct for all memory cases. On the 11/780, the unaligned
access to register or IO space causes an error, as it should. On
CVAX, it causes incorrect behavior, by either performing too many
QBus references, or performing read-modify-writes instead of pure
writes, or accessing the wrong Qbus locations.
The problem cannot be trivially solved with address manipulation.
The core issues is that on CVAX, unaligned access is done to
exactly as many bytes as are required, using a base longword
address and a byte mask. There are five cases, corresponding to
word and longword lengths, and byte offsets 1, 2 (longword only),
and 3. Further, behavior is different for reads and writes, because
the Qbus always performs word operations on reads, leaving it to
the processor to extract a byte if needed.
Conceptual design: Changes in vax_mmu.c:
Unaligned access is done with two separate physical addresses, pa
and pa1, because if the access crosses a page boundary, pa1 may
not be contiguous with pa. It's worth noting that in an unaligned
access, the low part of the data begins at pa (complete with byte
offset), but the high parts begins at pa1 & ~03 (always in the
low-order end of the second longword).
To handle unaligned data, we will add two routines for read and
write unaligned:
data = ReadU (pa, len);
WriteU (pa, len, val);
Note that the length can be 1, 2, or 3 bytes. For ReadU, data is
return right-aligned and masked. For WriteU, val is expected to
be right-aligned and masked.
The read-unaligned flows are changed as follows:
if (mapen && ((off + lnt) > VA_PAGSIZE)) { /* cross page? */
vpn = VA_GETVPN (va + lnt); /* vpn 2nd page */
tbi = VA_GETTBI (vpn);
xpte = (va & VA_S0)? stlb[tbi]: ptlb[tbi]; /* access tlb */
if (((xpte.pte & acc) == 0) || (xpte.tag != vpn) ||
((acc & TLB_WACC) && ((xpte.pte & TLB_M) == 0)))
xpte = fill (va + lnt, lnt, acc, NULL); /* fill if needed */
pa1 = ((xpte.pte & TLB_PFN) | VA_GETOFF (va + 4)) & ~03;
}
else pa1 = ((pa + 4) & PAMASK) & ~03; /* not cross page */
bo = pa & 3;
if (lnt >= L_LONG) { /* lw unaligned? */
sc = bo << 3;
wl = ReadU (pa, L_LONG - bo); /* read both fragments */
wh = ReadU (pa1, bo); /* extract */
return ((wl | (wh << (32 - sc))) & LMASK);
}
else if (bo == 1) /* read within lw */
return ReadU (pa, L_WORD);
else {
wl = ReadU (pa, L_BYTE); /* word cross lw */
wh = ReadU (pa1, L_BYTE); /* read, extract */
return (wl | (wh << 8));
}
These are not very different, but they do reflect that ReadU returns
right-aligned and properly masked data, rather than the encapsulating
longword.
The write-unaligned flows change rather more drastically:
if (mapen && ((off + lnt) > VA_PAGSIZE)) {
vpn = VA_GETVPN (va + 4);
tbi = VA_GETTBI (vpn);
xpte = (va & VA_S0)? stlb[tbi]: ptlb[tbi]; /* access tlb */
if (((xpte.pte & acc) == 0) || (xpte.tag != vpn) ||
((xpte.pte & TLB_M) == 0))
xpte = fill (va + lnt, lnt, acc, NULL);
pa1 = ((xpte.pte & TLB_PFN) | VA_GETOFF (va + 4)) & ~03;
}
else pa1 = ((pa + 4) & PAMASK) & ~03;
bo = pa & 3;
if (lnt >= L_LONG) {
sc = bo << 3;
WriteU (pa, L_LONG - bo, val & insert[L_LONG - bo]);
WriteU (pa, bo, (val >> (32 - sc)) & insert[bo]);
}
else if (bo == 1) /* read within lw */
WriteU (pa, L_WORD, val & WMASK);
else { /* word cross lw */
WriteU (pa, L_BYTE, val & BMASK);
WriteU (pa, L_BYTE, (val >> 8) & BMASK);
}
return;
}
Note that all the burden here has been thrown on the WriteU routine.
-------------
ReadU is the simpler of the two routines that needs to be written.
It will handle memory reads and defer register and IO space to
model-specific unaligned handlers.
int32 ReadU (uint32 pa, int32 lnt)
{
int32 dat;
int32 sc = (pa & 3) << 3;
if (ADDR_IS_MEM (pa))
dat = M[pa >> 2];
else {
mchk = REF_V;
if (ADDR_IS_IO (pa))
dat = ReadIOU (pa, lnt);
else dat = ReadRegU (pa, lnt);
}
return ((dat >> sc) & insert[lnt]);
}
Note that the ReadIOU and ReadRegU return a "full longword," just
like their aligned counterparts, and ReadU right-aligns the result,
just as ReadB, ReadW, and ReadL do.
WriteU must handle the memory read-modify-write sequence. However,
it defers register and IO space to model-specific unaligned handlers.
void WriteU (uint32 pa, int32 lnt, int32 val)
{
if (ADDR_IS_MEM (pa)) {
int32 bo = pa & 3;
int32 sc = bo << 3;
M[pa >> 2] = (M[pa >> 2] & ~(insert[len] << sc) | (val << sc);
}
else if ADDR_IS_IO (pa)
WriteIOU (pa, lnt, val);
else WriteRegU (pa, lnt, val);
return;
}
--------------
For the 11/780, ReadIOU, ReadRegU, WriteIOU, and WriteRegU all do the
same thing: they throw an SBI machine check. We can write explicit
routines to do this (and remove the unaligned checks from all the
normal adapter flows), or leave things as they are and simply define
the four routines as macros that go to the normal routines. So there's
very little to do.
On CVAX, I suspect that ReadRegU and WriteRegU behave like the
normal routines. The CVAX specs don't say much, but CMCTL (the memory
controller) notes that it ignores the byte mask and treats every
access as an aligned longword access. I suspect this is true for
the other CVAX support chips, but I no longer have chip specs.
The Qbus, on the other hand... that's a fun one. Note that all of
these cases are presented to the existing aligned IO routine:
bo = 0, byte, word, or longword length
bo = 2, word
bo = 1, 2, 3, byte length
All the other cases are going to end up at ReadIOU and WriteIOU,
and they must turn the request into the exactly correct number of
Qbus accesses AND NO MORE, because Qbus reads can have side-effects,
and word read-modify-write is NOT the same as a byte write.
The read cases are:
bo = 0, byte or word - read one word
bo = 1, byte - read one word
bo = 2, byte or word - read one word
bo = 3, byte - read one word
bo = 0, triword - read two words
bo = 1, word or triword - read two words
ReadIOU is very similar to the existing ReadIO:
int32 ReadIOU (uint32 pa, int32 lnt)
{
int32 iod;
iod = ReadQb (pa); /* wd from Qbus */
if ((lnt + (pa & 1)) <= 2) /* byte or word & even */
iod = iod << ((pa & 2)? 16: 0); /* one op */
else iod = (ReadQb (pa + 2) << 16) | iod; /* two ops, get 2nd wd */
SET_IRQL;
return iod;
}
The write cases are:
bo = x, lnt = byte - write one byte
bo = 0 or 2, lnt = word - write one word
bo = 1, lnt = word - write two bytes
bo = 0, lnt = triword - write word, byte
bo = 1, lnt = triword - write byte, word
WriteIOU is similar to the existing WriteIO:
void WriteIO (uint32 pa, int32 val, int32 lnt)
{
switch (lnt) {
case L_BYTE: /* byte */
WriteQb (pa, val & BMASK, WRITEB);
break;
case L_WORD: /* word */
if (pa & 1) { /* odd addr? */
WriteQb (pa, val & BMASK, WRITEB);
WriteQb (pa + 1, (val >> 8) & BMASK, WRITEB);
}
else WriteQb (pa, val, WRITE);
break;
case 3: /* triword */
if (pa & 1) { /* odd addr? */
WriteQb (pa, val & BMASK, WRITEB);
WriteQb (pa + 1, (val >> 8) & WMASK, WRITE);
}
else {
WriteQb (pa, val & WMASK, WRITE);
WriteQb (pa + 2, (val >> 16) & BMASK, WRITEB);
}
break;
}
SET_IRQL;
return;
}
-----------------
I think this handles all the cases.
/Bob Supnik
This commit is contained in:
Mark Pizzolato
parent
0774109897
commit
d31e9148e6
@ -686,7 +686,7 @@ static const uint16 boot_rom[] = {
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t_stat rs_boot (int32 unitno, DEVICE *dptr)
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{
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int32 i;
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size_t i;
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extern uint16 *M;
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UNIT *uptr = rs_dev.units + unitno;
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@ -1,6 +1,6 @@
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/* vax780_defs.h: VAX 780 model-specific definitions file
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Copyright (c) 2004-2011, Robert M Supnik
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Copyright (c) 2004-2013, Robert M Supnik
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and associated documentation files (the "Software"),
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@ -23,6 +23,7 @@
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used in advertising or otherwise to promote the sale, use or other dealings
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in this Software without prior written authorization from Robert M Supnik.
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29-Nov-13 RMS Added system-specific unaligned routines
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12-Dec-12 RMS Fixed IO base address for RQB, RQC, RQD
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05-Nov-11 RMS Added VEC_QMODE definition
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19-Nov-08 RMS Moved I/O support routines to I/O library
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@ -448,6 +449,14 @@ t_stat show_nexus (FILE *st, UNIT *uptr, int32 val, void *desc);
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void sbi_set_errcnf (void);
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int32 clk_cosched (int32 wait);
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/* Function prototypes for system-specific unaligned support
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11/780 treats unaligned like aligned */
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#define ReadIOU(p,l) ReadIO (p,l)
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#define ReadRegU(p,l) ReadReg (p,l)
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#define WriteIOU(p,v,l) WriteIO (p, v, l)
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#define WriteRegU(p,v,l) WriteReg (p, v, l)
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#include "pdp11_io_lib.h"
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#endif
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97
VAX/vax_io.c
97
VAX/vax_io.c
@ -1,6 +1,6 @@
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/* vax_io.c: VAX 3900 Qbus IO simulator
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Copyright (c) 1998-2012, Robert M Supnik
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Copyright (c) 1998-2013, Robert M Supnik
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and associated documentation files (the "Software"),
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@ -25,6 +25,7 @@
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qba Qbus adapter
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20-Dec-13 RMS Added unaligned access routines
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25-Mar-12 RMS Added parameter to int_ack prototype (Mark Pizzolata)
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28-May-08 RMS Inlined physical memory routines
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25-Jan-08 RMS Fixed declarations (Mark Pizzolato)
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@ -229,7 +230,7 @@ mem_err = 1;
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return;
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}
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/* ReadIO - read I/O space
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/* ReadIO - read I/O space - aligned access
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Inputs:
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pa = physical address
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@ -250,7 +251,49 @@ SET_IRQL;
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return iod;
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}
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/* WriteIO - write I/O space
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/* ReadIOU - read I/O space - unaligned access
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Inputs:
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pa = physical address
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lnt = length (1, 2, 3 bytes)
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Output:
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data, not shifted
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Note that all of these cases are presented to the existing aligned IO routine:
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bo = 0, byte, word, or longword length
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bo = 2, word
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bo = 1, 2, 3, byte length
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All the other cases are end up at ReadIOU and WriteIOU, and they must turn
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the request into the exactly correct number of Qbus accesses AND NO MORE,
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because Qbus reads can have side-effects, and word read-modify-write is NOT
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the same as a byte write.
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Note that the sum of the pa offset and the length cannot be greater than 4.
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The read cases are:
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bo = 0, byte or word - read one word
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bo = 0, tribyte - read two words
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bo = 1, byte - read one word
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bo = 1, word or tribyte - read two words
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bo = 2, byte or word - read one word
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bo = 3, byte - read one word
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*/
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int32 ReadIOU (uint32 pa, int32 lnt)
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{
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int32 iod;
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iod = ReadQb (pa); /* wd from Qbus */
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if ((lnt + (pa & 1)) <= 2) /* byte or (word & even) */
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iod = iod << ((pa & 2)? 16: 0); /* one op */
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else iod = (ReadQb (pa + 2) << 16) | iod; /* two ops, get 2nd wd */
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SET_IRQL;
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return iod;
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}
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/* WriteIO - write I/O space - aligned access
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Inputs:
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pa = physical address
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@ -274,6 +317,54 @@ SET_IRQL;
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return;
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}
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/* WriteIOU - write I/O space
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Inputs:
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pa = physical address
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val = data to write, right justified in 32b longword
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lnt = length (1, 2, or 3 bytes)
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Outputs:
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none
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The write cases are:
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bo = x, lnt = byte - write one byte
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bo = 0 or 2, lnt = word - write one word
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bo = 1, lnt = word - write two bytes
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bo = 0, lnt = tribyte - write word, byte
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bo = 1, lnt = tribyte - write byte, word
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*/
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void WriteIOU (uint32 pa, int32 val, int32 lnt)
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{
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switch (lnt) {
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case L_BYTE: /* byte */
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WriteQb (pa, val & BMASK, WRITEB);
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break;
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case L_WORD: /* word */
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if (pa & 1) { /* odd addr? */
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WriteQb (pa, val & BMASK, WRITEB);
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WriteQb (pa + 1, (val >> 8) & BMASK, WRITEB);
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}
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else WriteQb (pa, val & WMASK, WRITE);
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break;
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case 3: /* tribyte */
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if (pa & 1) { /* odd addr? */
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WriteQb (pa, val & BMASK, WRITEB); /* byte then word */
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WriteQb (pa + 1, (val >> 8) & WMASK, WRITE);
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}
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else { /* even */
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WriteQb (pa, val & WMASK, WRITE); /* word then byte */
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WriteQb (pa + 2, (val >> 16) & BMASK, WRITEB);
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}
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break;
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}
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SET_IRQL;
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return;
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}
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/* Find highest priority outstanding interrupt */
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int32 eval_int (void)
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109
VAX/vax_mmu.c
109
VAX/vax_mmu.c
@ -1,6 +1,6 @@
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/* vax_mmu.c - VAX memory management
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Copyright (c) 1998-2008, Robert M Supnik
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Copyright (c) 1998-2013, Robert M Supnik
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and associated documentation files (the "Software"),
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@ -23,6 +23,7 @@
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used in advertising or otherwise to promote the sale, use or other dealings
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in this Software without prior written authorization from Robert M Supnik.
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29-Nov-13 RMS Reworked unaligned flows
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21-Jul-08 RMS Removed inlining support
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28-May-08 RMS Inlined physical memory routines
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29-Apr-07 RMS Added address masking for system page table reads
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@ -56,7 +57,6 @@ typedef struct {
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} TLBENT;
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extern uint32 *M;
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extern const uint32 align[4];
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extern int32 PSL;
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extern int32 mapen;
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extern int32 p1, p2;
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@ -107,6 +107,8 @@ extern int32 ReadIO (uint32 pa, int32 lnt);
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extern void WriteIO (uint32 pa, int32 val, int32 lnt);
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extern int32 ReadReg (uint32 pa, int32 lnt);
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extern void WriteReg (uint32 pa, int32 val, int32 lnt);
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int32 ReadU (uint32 pa, int32 lnt);
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void WriteU (uint32 pa, int32 val, int32 lnt);
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/* TLB data structures
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@ -192,22 +194,22 @@ if (mapen && ((off + lnt) > VA_PAGSIZE)) { /* cross page? */
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if (((xpte.pte & acc) == 0) || (xpte.tag != vpn) ||
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((acc & TLB_WACC) && ((xpte.pte & TLB_M) == 0)))
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xpte = fill (va + lnt, lnt, acc, NULL); /* fill if needed */
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pa1 = (xpte.pte & TLB_PFN) | VA_GETOFF (va + 4);
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pa1 = ((xpte.pte & TLB_PFN) | VA_GETOFF (va + 4)) & ~03;
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}
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else pa1 = (pa + 4) & PAMASK; /* not cross page */
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else pa1 = ((pa + 4) & PAMASK) & ~03; /* not cross page */
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bo = pa & 3;
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if (lnt >= L_LONG) { /* lw unaligned? */
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sc = bo << 3;
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wl = ReadL (pa); /* read both lw */
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wh = ReadL (pa1); /* extract */
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return ((((wl >> sc) & align[bo]) | (wh << (32 - sc))) & LMASK);
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wl = ReadU (pa, L_LONG - bo); /* read both fragments */
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wh = ReadU (pa1, bo); /* extract */
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return ((wl | (wh << (32 - sc))) & LMASK);
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}
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else if (bo == 1)
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return ((ReadL (pa) >> 8) & WMASK);
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else if (bo == 1) /* read within lw */
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return ReadU (pa, L_WORD);
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else {
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wl = ReadL (pa); /* word cross lw */
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wh = ReadL (pa1); /* read, extract */
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return (((wl >> 24) & 0xFF) | ((wh & 0xFF) << 8));
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wl = ReadU (pa, L_BYTE); /* word cross lw */
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wh = ReadU (pa1, L_BYTE); /* read, extract */
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return (wl | (wh << 8));
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}
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}
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@ -225,7 +227,7 @@ else {
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void Write (uint32 va, int32 val, int32 lnt, int32 acc)
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{
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int32 vpn, off, tbi, pa;
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int32 pa1, bo, sc, wl, wh;
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int32 pa1, bo, sc;
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TLBENT xpte;
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mchk_va = va;
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@ -255,29 +257,20 @@ if (mapen && ((off + lnt) > VA_PAGSIZE)) {
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if (((xpte.pte & acc) == 0) || (xpte.tag != vpn) ||
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((xpte.pte & TLB_M) == 0))
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xpte = fill (va + lnt, lnt, acc, NULL);
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pa1 = (xpte.pte & TLB_PFN) | VA_GETOFF (va + 4);
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pa1 = ((xpte.pte & TLB_PFN) | VA_GETOFF (va + 4)) & ~03;
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}
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else pa1 = (pa + 4) & PAMASK;
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else pa1 = ((pa + 4) & PAMASK) & ~03;
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bo = pa & 3;
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wl = ReadL (pa);
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if (lnt >= L_LONG) {
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sc = bo << 3;
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wh = ReadL (pa1);
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wl = (wl & insert[bo]) | ((val << sc) & LMASK);
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wh = (wh & ~insert[bo]) | ((val >> (32 - sc)) & insert[bo]);
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WriteL (pa, wl);
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WriteL (pa1, wh);
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WriteU (pa, val & insert[L_LONG - bo], L_LONG - bo);
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WriteU (pa1, (val >> (32 - sc)) & insert[bo], bo);
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}
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else if (bo == 1) {
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wl = (wl & 0xFF0000FF) | (val << 8);
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WriteL (pa, wl);
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}
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else {
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wh = ReadL (pa1);
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wl = (wl & 0x00FFFFFF) | ((val & 0xFF) << 24);
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wh = (wh & 0xFFFFFF00) | ((val >> 8) & 0xFF);
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WriteL (pa, wl);
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WriteL (pa1, wh);
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else if (bo == 1) /* read within lw */
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WriteU (pa, val & WMASK, L_WORD);
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else { /* word cross lw */
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WriteU (pa, val & BMASK, L_BYTE);
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WriteU (pa1, (val >> 8) & BMASK, L_BYTE);
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}
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return;
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}
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@ -348,7 +341,8 @@ SIM_INLINE int32 ReadL (uint32 pa)
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if (ADDR_IS_MEM (pa))
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return M[pa >> 2];
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mchk_ref = REF_V;
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if (ADDR_IS_IO (pa)) return ReadIO (pa, L_LONG);
|
||||
if (ADDR_IS_IO (pa))
|
||||
return ReadIO (pa, L_LONG);
|
||||
return ReadReg (pa, L_LONG);
|
||||
}
|
||||
|
||||
@ -363,6 +357,30 @@ if (ADDR_IS_IO (pa))
|
||||
return ReadReg (pa, L_LONG);
|
||||
}
|
||||
|
||||
/* Read unaligned physical (in virtual context)
|
||||
|
||||
Inputs:
|
||||
pa = physical address
|
||||
lnt = length in bytes (1, 2, or 3)
|
||||
Output:
|
||||
returned data
|
||||
*/
|
||||
|
||||
int32 ReadU (uint32 pa, int32 lnt)
|
||||
{
|
||||
int32 dat;
|
||||
int32 sc = (pa & 3) << 3;
|
||||
if (ADDR_IS_MEM (pa))
|
||||
dat = M[pa >> 2];
|
||||
else {
|
||||
mchk_ref = REF_V;
|
||||
if (ADDR_IS_IO (pa))
|
||||
dat = ReadIOU (pa, lnt);
|
||||
else dat = ReadRegU (pa, lnt);
|
||||
}
|
||||
return ((dat >> sc) & insert[lnt]);
|
||||
}
|
||||
|
||||
/* Write aligned physical (in virtual context, unless indicated)
|
||||
|
||||
Inputs:
|
||||
@ -432,6 +450,33 @@ else {
|
||||
return;
|
||||
}
|
||||
|
||||
/* Write unaligned physical (in virtual context)
|
||||
|
||||
Inputs:
|
||||
pa = physical address
|
||||
val = data to be written, right justified in 32b longword
|
||||
lnt = length (1, 2, or 3 bytes)
|
||||
Output:
|
||||
none
|
||||
*/
|
||||
|
||||
void WriteU (uint32 pa, int32 val, int32 lnt)
|
||||
{
|
||||
if (ADDR_IS_MEM (pa)) {
|
||||
int32 bo = pa & 3;
|
||||
int32 sc = bo << 3;
|
||||
M[pa >> 2] = (M[pa >> 2] & ~(insert[lnt] << sc)) | ((val & insert[lnt]) << sc);
|
||||
}
|
||||
else {
|
||||
mchk_ref = REF_V;
|
||||
if ADDR_IS_IO (pa)
|
||||
WriteIOU (pa, val, lnt);
|
||||
else WriteRegU (pa, val, lnt);
|
||||
}
|
||||
return;
|
||||
}
|
||||
|
||||
|
||||
/* TLB fill
|
||||
|
||||
This routine fills the TLB after a tag or access mismatch, or
|
||||
|
||||
@ -1,6 +1,6 @@
|
||||
/* vax_sysdev.c: VAX 3900 system-specific logic
|
||||
|
||||
Copyright (c) 1998-2011, Robert M Supnik
|
||||
Copyright (c) 1998-2013, Robert M Supnik
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a
|
||||
copy of this software and associated documentation files (the "Software"),
|
||||
@ -32,6 +32,7 @@
|
||||
cso console storage output
|
||||
sysd system devices (SSC miscellany)
|
||||
|
||||
20-Dec-13 RMS Added unaligned register space access routines
|
||||
23-Dec-10 RMS Added power clear call to boot routine (Mark Pizzolato)
|
||||
25-Oct-05 RMS Automated CMCTL extended memory
|
||||
16-Aug-05 RMS Fixed C++ declaration and cast problems
|
||||
@ -214,6 +215,9 @@ int32 ssc_adsm[2] = { 0 }; /* addr strobes */
|
||||
int32 ssc_adsk[2] = { 0 };
|
||||
int32 cdg_dat[CDASIZE >> 2]; /* cache data */
|
||||
static uint32 rom_delay = 0;
|
||||
static const int32 insert[4] = {
|
||||
0x00000000, 0x000000FF, 0x0000FFFF, 0x00FFFFFF
|
||||
};
|
||||
|
||||
t_stat rom_ex (t_value *vptr, t_addr exta, UNIT *uptr, int32 sw);
|
||||
t_stat rom_dep (t_value val, t_addr exta, UNIT *uptr, int32 sw);
|
||||
@ -961,6 +965,20 @@ MACH_CHECK (MCHK_READ);
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* ReadRegU - read register space, unaligned
|
||||
|
||||
Inputs:
|
||||
pa = physical address
|
||||
lnt = length in bytes (1, 2, or 3)
|
||||
Output:
|
||||
returned data, not shifted
|
||||
*/
|
||||
|
||||
int32 ReadRegU (uint32 pa, int32 lnt)
|
||||
{
|
||||
return ReadReg (pa & ~03, L_LONG);
|
||||
}
|
||||
|
||||
/* WriteReg - write register space
|
||||
|
||||
Inputs:
|
||||
@ -986,6 +1004,26 @@ MACH_CHECK (MCHK_WRITE);
|
||||
return;
|
||||
}
|
||||
|
||||
/* WriteRegU - write register space, unaligned
|
||||
|
||||
Inputs:
|
||||
pa = physical address
|
||||
val = data to write, right justified in 32b longword
|
||||
lnt = length (1, 2, or 3)
|
||||
Outputs:
|
||||
none
|
||||
*/
|
||||
|
||||
void WriteRegU (uint32 pa, int32 val, int32 lnt)
|
||||
{
|
||||
int32 sc = (pa & 03) << 3;
|
||||
int32 dat = ReadReg (pa & ~03, L_LONG);
|
||||
|
||||
dat = (dat & ~(insert[lnt] << sc)) | ((val & insert[lnt]) << sc);
|
||||
WriteReg (pa & ~03, dat, L_LONG);
|
||||
return;
|
||||
}
|
||||
|
||||
/* CMCTL registers
|
||||
|
||||
CMCTL00 - 15 configure memory banks 00 - 15. Note that they are
|
||||
|
||||
@ -1,6 +1,6 @@
|
||||
/* vaxmod_defs.h: VAX model-specific definitions file
|
||||
|
||||
Copyright (c) 1998-2012, Robert M Supnik
|
||||
Copyright (c) 1998-2013, Robert M Supnik
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a
|
||||
copy of this software and associated documentation files (the "Software"),
|
||||
@ -23,6 +23,7 @@
|
||||
used in advertising or otherwise to promote the sale, use or other dealings
|
||||
in this Software without prior written authorization from Robert M Supnik.
|
||||
|
||||
20-Dec-13 RMS Added prototypes for unaligned IO and register handling
|
||||
12-Dec-12 RMS Fixed IO base address for RQB, RQC, RQD
|
||||
11-Dec-11 RMS Moved all Qbus devices to BR4; deleted RP definitions
|
||||
25-Nov-11 RMS Added VEC_QBUS definition
|
||||
@ -471,4 +472,11 @@ int32 clk_cosched (int32 wait);
|
||||
|
||||
#include "pdp11_io_lib.h"
|
||||
|
||||
/* Function prototypes for system-specific unaligned support */
|
||||
|
||||
int32 ReadIOU (uint32 pa, int32 lnt);
|
||||
int32 ReadRegU (uint32 pa, int32 lnt);
|
||||
void WriteIOU (uint32 pa, int32 val, int32 lnt);
|
||||
void WriteRegU (uint32 pa, int32 val, int32 lnt);
|
||||
|
||||
#endif
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user