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745 Commits

Author SHA1 Message Date
Mark Pizzolato
01bac285ec PDP11, VAX: Minor corrections in TS and RQ device help language 2025-12-03 19:33:06 -10:00
Mark Pizzolato
ab832ce274 TAPE: Better expose the various tape debug options usable from device debug
- Cleanup tape debug options and internal usage
- Add MTSE_DBG_INT for internal API activities
- Make sure SCSI uses the correct debug value for tape debug
2025-12-02 08:19:09 -10:00
Mark Pizzolato
85e1957fd0 ETHER: Coalesce Ethernet devices with consistent hierarchical attach help
Migrate platform dependencies into sim_ether's help rather that
scattered amongst each functional Ethernet device.
2025-10-10 17:53:57 -10:00
Sergey Svishchev
45fe20a34b PDP11: Changes for Terak 8510/a simulator:
Accept devices mapped at IOPAGEBASE -- text buffer/character generator
memory on video board starts at 160000.

Clear invalid PSW bits in trap handler -- system acceptance test writes
PSW 113705 to vector 34 (TRAP instruction).
2025-09-12 10:23:51 -10:00
Mark Pizzolato
b305252bff PDP11, VAX730, VAX750: Fix TU58 device support (TDC and console TD devices)
- Cleanup TD console device attach logic
- Properly initialize the TDC devices

Fix #1220
2025-08-28 08:46:48 -10:00
Mark Pizzolato
fe8f7e4e46 NOVA, PDP18B, PDP8, PDP11: Some of the remaining changes from simh v3.12-5 2025-08-07 16:13:09 -10:00
Bob Supnik
ecc4df6e6d PDP11: MASSBUS controller clear vs rhwc register 2025-07-31 13:30:08 -10:00
David Ellis
e8e900a3cd PDP11: Fix typo in SYSTEM DR register description 2025-07-26 17:12:48 -10:00
Thalia Archibald
4f157b9318 PDP11: Document CIS register-form instructions
Only the string instructions document the registers used by the
register-form instructions. Also document the BCD register-form
instructions. Although, the operands have already been loaded into the
special-purpose instructions before the op switch, I think this
documentation is useful.
2025-06-06 02:56:55 -10:00
Thalia Archibald
f27e40130a PDP11: Fix L2DR and L3DR comments
These instructions are referred to as L2Dr and L3Dr in the PDP-11/24
System Technical Manual (https://www.vt100.net/manx/details/1,23) and
their opcode strings call them L2DR and L3DR. These comments seem to be
a simple typo.
2025-06-06 02:56:55 -10:00
Mark Pizzolato
661be5d1eb Qbus MicroVAXen: Fix Qbus Address reference passed in by some OS boot code
Problem reported in https://github.com/open-simh/simh/issues/409

There are key differences between the MicroVAX I and MicroVAX II.
Specifically, the MicroVAX I is a machine with direct Qbus memory and
no QBA (Qbus Adapter) which is part of all later MicroVAXen and
corresponds to the UBA (Unibus Adapter) on systems with Unibuxes.
Among possibly other things, these Adapters primarily provide the
translation between the CPU's system memory and addresses on the
respective bus (Qbus or Unibus).  These Adapters provide a set of
mapping registers which map the respective bus addresses to desired
locations in CPU memory which allows for "Scatter/Gather" memory
transfers.  The MicroVAX I, having its memory directly on the Qbus,
has no CPU specific way to implement "Scatter/Gather" for I/O device
for memory transfers very much needed in systems with virtual memory.
On this system, the Scatter/Gather functionality is provided directly
within the MSCP controller which is simulated by the pdp11_rq.c
module.

On Qbus MicroVAXen with Qbus Adapters, the boot rom initializes all
the Qbus mapping registers such that Qbus addresses map directly to
CPU RAM addresses.  This simplifies boot code which don't turn on
Virtual Memory (and thus the need for Scatter/Gather) until later stages
of the operating system boot.  The Ultrix boot we're dealing with plays
games with the mapping registers somewhat early in the boot, and
requests a transfer of 0x2000 bytes (words maybe) to an address of
0x010000c8.  Note that this would be the address from the point of
view of the controller on the Qbus.  This value is actually beyond the
end of the 22bit Qbus address space (0x003fffff).  The controller
therefore previously returned a non-existent memory error.

It would seem that instructions performing this I/O request are ones
which were loaded by an earlier read and thus the bug really should
be there, but since this code actually worked on real hardware,
accomodating that behavior belongs in the simulator.  Meanwhile,
when this transfer has happened, the QBA Mapping registers have
been changed from their initial values that mapped 1-1 Qbus addresses
to RAM.  The proper approach is therefore merely to ignore any bits
in the transfer address beyond the 22bits of the Qbus address space.

Interesting that all other operating systems (or boot code) never
presented a buffer address beyond the maximum 22bit Qbus address.
2024-09-02 18:20:35 -10:00
Mark Pizzolato
d2cd594cde PDP11: Integrate RR (RP11) device with full sim_disk capabilities 2024-07-20 15:08:19 -10:00
Tony Lawrence
434a1f807b PDP11: Add RP11 device (RR)
PDP11: RP11: Interrupt on IE+RESET+GO

Recent analysis of the 2.9BSD kernel revealed that RP11 was
expected to interrupt on control RESET function if IE bit was
also set.  Documentation was not very clear of the fact, saying
in one place that RESET+GO does not interrupt (which is not
contradictory with the above because it does not mention IE).

In other place, however, it says that IE always causes interrupt
when DONE is asserted.  Thus, since RESET does assert DONE, an
interrupt should be posted if IE is set.  The autoconfig binary
from 2.9BSD uses this feature of RP11 to check the presence
of the controller.

Formerly RESET was always clearing RPCS with DONE unconditionally,
and that reset IE as well.  This patch makes sure that the IE bit
is preserved, and if set, it posts an interrupt when RESET asserts
DONE.

PDP11: RP11: Make sure to advance DA after every I/O

It looks like disk controllers, which automatically update
disk address (DA) after completion of I/O, are expected to do
so even if there was no data transfer because of I/O errors.
I was studying RSX-11's Error Logger documentation and
examples are clearly offsetting disk addresses backwards
by one when I/O errors are reported by the controller.

Since once the controller has found the DA-specified sector,
the I/O begins regardless of the condition of the sector (bad
or good data) or ability to transfer the contents between the
disk and the memory.  If an error occurs (NXM, for instance)
the operation would stop (with the error reported) at the end
of the sector.  So if, for example, the bus address register
had a bad address from the get-go, no data would be able to
transfer at all, yet DA should still be updated with DA + 1
once the controller asserts the DONE bit.

This patch makes sure that DA is always advanced when I/O has
actually been commenced.

PDP11: RP11: Remove duplicate checks (now only done in svc routine)

PDP11: RP11: Implement delayed CS_DONE for "initiation" commands (SEEK/HOME)

Running earlier XXDP tests revealed that a technique of concurrent command
initiation and continued housekeeping for the command completion was used in
the old code.

For example, code could initiate a SEEK command for a drive, and knowing that
CS_DONE (and thus, an interrupt) is coming in about 16us, it would then go
ahead and clear a flag, which registers that the interrupt has occurred
(expected to be set to 1 by the ISR).  If CS_DONE is set by the implementation
at the function initiation immediately, that would mean that the interrupt
could be triggered before the next instruction, and the flag would be set by
the ISR right away.  The main code, however, would proceed with the the flag
clear as the following instruction, thus, never detecting the interrupt down
the road.

Since this technique was in existence, it is better to introduce a delay for
setting CS_DONE in the "fast" initiation commands like SEEK and HOME, to
accommodate the software that was relying on it.

So far, however, no issues were encountered in testing (except one), where
this delay mattered, but it's hard to tell if it would not be needed at all.

All I/O commands always delay CS_DONE already because they were never supposed
to be immediate.

Since the time for CS_DONE in initiation commands was documented at 16us, the
introduced delay is set to 10 instructions, which usually took more than that
to execute.  But the interrupt flag clear case would be covered, as well as
the counted waits, which used some 25+-iteration tight loops for "drive ready",
before flagging a time-out (so the delay cannot be longer, either).

It also looks like more modern code never used any such tricks, so for it, it
should not matter if CS_DONE was slightly delayed or not.

PDP11: RP11: Major update after XXDP

Having run the device code thru XXDP and some other OS's and scenarios
rigorously, a bunch of discrepancies were found, which need to be addressed
by this rather extensive patch.

1. Each unit must implement its own "drive status" register, to be able to
   track per-drive errors / conditions correctly;
2. Fixed INT_SET() / INT_CLR() in RPCS write function (wrong order of the "if"
   conditions);
3. Some behavior was implemented not exactly how it was expected from the real
   hardware, such as:
   a. Post-I/O register values in RPDA and RPCA (including the corner case of
      pack overflow);
   b. I/O stacking, which wasn't mentioned in any available documentation, but
      only XXDP listings;
   c. RESET/IDLE function must be accepted for a "busy" controller;
   d. HOME function must always execute, even when "device ready" is not set
      (e.g. when SEEK error detected);
   e. SEEK incomplete should not respond with "device ready" (however, the
      condition can be cleared by HOME, d.);
   f. WLOA-induced write-lock violation wasn't reflected in "device status".
4. Some timing was off so that the device worked "too fast" -- this was fixed
   (except for the pathological cases when the races are in the actual test
   code, and cannot be logically fixed);
5. WLOA setup command bug was fixed;
6. Added more code comments found per the above peculiarities.
2024-07-20 15:02:45 -10:00
Bob Supnik
3840fcfe7a PDP11: Fixed disassembly of ASH,ASHC,MUL,DIV
Fix original change from Paul Koning
2024-07-17 10:45:27 -10:00
Tony Lawrence
6dc5ddd509 PDP11: Fixed writes to 11/70 RO registers 2024-07-17 10:23:29 -10:00
Paul Koning
ee34e29511 PDP11: fix disassembly of reg,src instructions
This corrects the disassembly of MUL, DIV, ASH, and ASHC so it works
correctly when the register is not R0.
2023-12-18 10:34:59 -10:00
Mark Pizzolato
6d376b2fd9 ALL simulators with instruction history support: Minor history enhancements
- Issue reasonable error message explaining invalid SET CPU HISTORY=n input
- Let SIGINT (^C) abort SHOW HISTORY output
2023-12-04 10:57:31 -10:00
Christian Gauger-Cosgrove
42d6f414fc PDP11, VAX: Add MSCP RD33 and various SDI ESE SSD disk types to RQ devices 2023-11-16 11:33:52 -10:00
Lars Brinkhoff
04b2795982 PDP11, VAX, KS10: Speed up Chaosnet polling when there is traffic. 2023-11-16 11:19:38 -10:00
Tony Lawrence
7af559c580 PDP11: TA11/TU60 fix identification 2023-11-12 12:58:55 -10:00
Bob Supnik
4c63340ba9 PDP11, PDP10 & VAXen: Fix TS11, RH11/TM02-3, TU45 for proper BOT handling
A user observed that the TS11 would not run XXDP+, even though it ran
fine with the PDP11 operating systems, VMS, and XXDP V2.  I traced this
back to a conceptual error in the implementation of some magtapes,
specifically the TS11, RH11/TM02-3, and the PDP10 TU45.

The issues is that beginning of tape, and being positioned in front of
the first record, are not necessarily the same. Following BOT, tape
drives record a ID burst If high density and an inter-record gap before
the first record. When the first record is read backwards or backspaced
over, the tape ends up at position 0 but should not show BOT.  Most
simulated tape drives did this correctly, but a few used sim_tape_bot()
as a shortcut for BOT, and it's simply not correct.

BOT should be set at ATTACH, by a successful rewind, and by any reverse
operation when the tape is positioned in front of the first record.

BOT should be cleared by any successful movement operation, except
rewind.
2023-11-12 10:04:28 -10:00
Tony Lawrence
abd1834380 PDP11: 11/70 read-only registers must not return NXM on write
17 777 740 - 17 777 742, read-only error address registers,
and 17 777 764, a read-only System ID register,

and are not handled in the CPU70_wr() routine, which means for these
addresses the routine returns NXM, which then translates to "bus timeout"
(no response to address), and then, as a result, trap to vector 4.

That is incorrect, IMO.

These locations are read-only yet the address gets decoded, and even
though writing does not have any effect, the write routine for these
addresses should return SCPE_OK.
2023-10-15 02:44:43 -10:00
Tony Lawrence
5b9a6abb37 PDP11: TS11: Fix help output for BOOT command
The BOOT command for this device was not correctly documented in HELP
(appearing both supported and not) for PDP-11.

This change fixes the issue and syncs HELP output with the actual code
(by using the same #if conditional).
2023-10-06 00:31:29 -10:00
Mark Pizzolato
9b0413045a DISK: Provide disk Geometry (Cylinders, Heads, Sectors) for all disk types
- Display Media-ID and Geometry info for all SHOW <unit> output when attached
- Use real drive Geometry info for all disk types
- Fix RA80 cylinders copied from RM80
- Fix RZ23 cylinders to reflect disk size
- Return correct cylinder info on MSCP error path
2023-09-09 13:02:45 -10:00
Mark Pizzolato
949b56b7a9 Qbus & Unibus VAX & PDP11: Correct controller type KLESI (RC25) to 3, add KDB50 2023-07-20 14:47:25 -10:00
Mark Pizzolato
c739e6195a Qbus VAX and PDP11's: Correct RQ controller model numbers RQDX1 and RUX50 2023-07-09 12:40:46 -10:00
Mark Pizzolato
05e3b20009 Qbus VAX and PDP11's: Add specific support for RQDX1 MSCP controller
- Change default RQ controller type for MicroVAX I simulator to RQDX1
- Validate changes to controller to CPU system bus
2023-07-09 12:19:17 -10:00
Mark Pizzolato
6491cf0371 BuildROMs: Make sure that multiple ROM includes are each numbered _n
The first ROM included will be defined with names:
        BOOT_CODE_SIZE
        BOOT_CODE_CHECKSUM
        BOOT_CODE_FILENAME
        BOOT_CODE_FILEPATH
        BOOT_CODE_ARRAY
 and BOOT_CODE_URL
That first ROM will also have names:
        BOOT_CODE_SIZE_1
        BOOT_CODE_CHECKSUM_1
        BOOT_CODE_FILENAME_1
        BOOT_CODE_FILEPATH_1
        BOOT_CODE_ARRAY_1
 and BOOT_CODE_URL_1
Subsequent included ROM's will have names
        BOOT_CODE_SIZE_n
        BOOT_CODE_CHECKSUM_n
        BOOT_CODE_FILENAME_n
        BOOT_CODE_FILEPATH_n
        BOOT_CODE_ARRAY_n
 and BOOT_CODE_URL_n
where n is 2 thru the max number of supported ROM includes.
2023-07-02 10:52:34 -10:00
Mark Pizzolato
f9a4b8c6b9 PDP11: Properly define the RC and RF devices to allow for varying platters
Leverage drive type flag DETAUTO which defers meta data addition to
happen at detach time.  This allows pre-existing containers to be attached
to larger drives (with more platters) with autosize disabled and then if
autosizing is subsequently enabled before detaching, will thus add correct
meta data when the unit is detached.

Newly created containers will have meta data added at creation time and
updated to reflect data written beyond the original data in the container.
2023-06-29 14:13:16 -10:00
Mark Pizzolato
1e1b97475b PDP11: RK, RX, RY and TD disks let detach_unit handle detaching disks 2023-06-27 11:43:04 -10:00
Mark Pizzolato
dfbd099677 BUILDROMS: Reorganize defines so multiple ROM includes have consistent names 2023-06-17 18:25:51 -10:00
Bob Supnik
c65f0ee485 PDP11: Fix bug in FIS dirty zero check 2023-06-08 01:30:24 -10:00
Mark Pizzolato
2e7a109bb8 PDP11 and Unibus VAXen: Make CH device local variables static
This avoids potential namespace collisions that can interact with libedit
and ncurses on some platforms.
2023-06-08 01:30:24 -10:00
Mark Pizzolato
972cd95914 PDP11: Add extra RPB device as an additional Massbus device
Note: To avoid potential breakage of existing PDP11 configurations in
       the wild, which may expect RP on RHA, TU on RHB and RS on RHC,
       RPB is connected to RHD Massbus adapter.

- More robust recovery when Massbus configuration errors occur
- More complete RH{A,B,C,D} help
2023-05-22 11:36:52 -10:00
Peter Allan
ef0f49204e VAX780: Add an additional Massbus to support RPB 2023-05-22 10:37:26 -10:00
Mark Pizzolato
bdb021e6ac Massbus VAXen and PDP11: Cleanup RP device to allow simple replication
Peter Allan analyzed the source code for the VAX780 simulator and
came up with a somewhat simple strategy to replicate the RP device
source code and to add another controller on an additional Massbus.

That initial strategy includes: Copying the pdp11_rp.c source module to
pdp11_rpb.c and making almost all global variables static as well as all
internal functions used in the RP device. All but the "DEVICE rp_dev",
that is, which now becomes "DEVICE rpb_dev" with a name of "RPB".

The change process was relatively simple although somewhat tedious and
wouldn't easily lend itself to manage future changes that might happen to
pdp11_rp.c.

The changes in this commit cleanup pdp11_rp.c so that changing it to
pdp11_rpb.c only need to affect 3 lines of code which will simplify
future maintenance of these modules.
2023-05-22 10:10:58 -10:00
Mark Pizzolato
d57c67c4f5 PDP11: Change Interrupt names from RP, TU and RS to RHA, RHB and RHC
Interrupts come through the respective Massbus adapters.  This is
consistent with the interrupt naming in the VAX Massbus adapters.
2023-05-19 17:14:58 -10:00
Mark Pizzolato
aa39867349 PDP11, VAX: Remove irrelevant #ifdefs in XQ and XU devices 2023-05-19 16:58:13 -10:00
Lars Brinkhoff
d573965024 VAX: M7452 Unibus window module for VAXstation 100. 2023-05-09 07:07:39 -10:00
Mark Pizzolato
ed5e47ab73 ETHER: Enhance version info and location of Npcap 2023-04-26 10:00:46 -10:00
Paul Koning
11b57201ad PDP11: Support byte write access to DHCSR.
This fixes issue #201, using a fix proposed bu Bjoren Davis.
2023-04-02 12:53:33 -10:00
Mark Pizzolato
829d696c5e Various Simulators: Changed line endings on accessory text files to CRLF
In following simh project standards
2023-03-10 15:32:06 -10:00
Mark Pizzolato
8538161757 PDP11: Remove stray tab characters in DZ, MB & TV 2023-03-04 14:26:04 -10:00
Tony Lawrence
154d83e663 PDP11: Add definitions for unimplemented registers and fixed debug data write 2023-01-21 09:37:14 -10:00
Mark Pizzolato
1baed4f7d4 PDP11: Properly set DC, DL and DLCJ unit relationships to TMXR structures
Fix problem reported on DC device by Alan Kirby
2023-01-18 01:54:37 -10:00
Bob Supnik
9319f6027e PDP11: Fix EXAMINE and DEPOSIT of floating point 2 argument instructions
In https:://github.com/open-simh/simh PR number 154 nickd4 that 2 argument
floating point instructions were displayed with the wrong argument order.

This change fixes BOTH the instruction display and the input activities for
these floating point instructions.
2022-12-31 09:07:40 -10:00
Bob Supnik
7e39e112da PDP11: Fix bug in FUIV operation
Problem reported by James Fehlinger
2022-12-11 09:45:12 -10:00
Walter Mueller
e46fc5cc56 PDP11: Fixing details in processor specific register behaviors, traps & aborts 2022-12-06 11:08:47 -10:00
Tony Lawrence
ff2d849460 PDP11: Fix RK11/RL11 byte/word count mismatch (and cyl upd in RK11) 2022-12-01 21:33:26 -05:00
Tony Lawrence
dc3cd257f8 PDP11: More correction in RK help text (per Paul Koning) 2022-11-17 21:06:39 -05:00