- Some versions of Omni OS no longer include sys/filio.h in sys/ioctl.h
- Add more robust support for locating OS tools in scp.c
- SHOW VERSION output displays SunOS host system specific info
Fix#1238
This is the initial release of the Altair8800 simulator.
Why another Altair simulator? AltairZ80 has been described as a
“software simulator”, where the intent is to run software designed
specifically for executing under a simulator. Altair8800 is intended
to accurately simulate the Altair hardware and execute software
that will run unchanged on real hardware. Software and disk images
can be moved between the Altair8800 simulator and real Altair and
other S-100 hardware without any changes. The Altair8800 simulator
is a tool that can assist with the restoration of vintage Altair
and other S-100 hardware and software along with the development
of new hardware and software. The accomplish this, the following
are major differences between AltairZ80 and Altair8800.
* The monolithic design where devices access other devices directly
through external variables and functions is no longer supported.
All devices exchange data through a new BUS device. Memory and I/O
address decoding and transfers are now handled by the BUS device.
All interrupt requests are handled by the BUS device.
* System RAM was moved from the CPU device to a new RAM device and
managed by the BUS device.
* Banked RAM was moved from the CPU device to a new BRAM device.
* Banked RAM can only be accessed through the BUS device. Memory in
banks that are not currently selected cannot be accessed. The AZ80
“banked” RAM was removed.
* ROMs were moved from the CPU and DSK devices to the new ROM device.
Mike Douglas’ Altmon Monitor is also available through the ROM
device. The custom AltairZ80 ALTAIRROM, which is not compatible
with original Altair disk images, is also available.
* The custom ALTAIRROM boot loader was replaced with the original
MITS Disk Boot Loader as the default ROM.
* The monolithic Multiple-CPU/RAM/ROM/IO/BankedRAM CPU device has
been replaced with a generic CPU device that provides an abstraction
layer between SIMH and the supported CPU architectures (currently
8080 and Z80). All IO is handled through the BUS device. RAM, Banked
RAM, and ROM are each handled by their own independent devices.
* The AltairZ80 SIO device was replaced with the M2SIO0 and M2SIO1
devices. The M2SIO devices fully support TMXR.
* A new SIO device was added to provide generic, programmable, Serial
IO. TMXR is not supported on this device.
* The Altair 8800 did not have PTR or PTP hardware devices. They have
been removed and replaced with the M2SIO1 device. PTR and PTP devices
are defined by software executing on the simulator.
* Contention between multiple enabled serial devices checking the
single host keyboard for input is now handled by the BUS device.
Port 0xFF sense switches was moved to a new SSW device and IMSAI
programmed output was moved to a new PO device.
* The SIMH pseudo device no longer uses the removed PTR and PTP
devices. The SIMH device has its own IO system. To avoid conflicts
with other devices and remain compatible with the R and W utilities
written for AltairZ80, SIMH “borrows” I/O ports 12H and 13H during
file transfers. Only SIMH commands needed to support R and W file
transfers are supported. All other SIMH commands were removed.
* AltairZ80-specific versions of CP/M are not supported by Altair8800.
* PC queue was removed from CPU device and replaced with CPU HISTORY.
* The Altair8800 simulator only supports 16-bit address and 8-bit
data buses. 8086 and 68K CPU architectures were removed.
* All CPU timing (clockFrequency) and “sleeps” (SIO SLEEP) have been
removed. SIMH THROTTLE is fully supported and is the recommended
way to manage simulator speed and host CPU utilization. Executing
“SET THROTTLE 100K/1”, for example, should provide ample speed
without tasking the host CPU.
* HEXLOAD and HEXSAVE commands were added. The LOAD “-h” option has
been removed. Intel Hex and sRecord (coming soon) formats are
supported.
* The WD179X device was converted to an API.
* A new DSK API was added to provide a consistent way to manage soft
sector raw disk images.
* Support for the proprietary IMD disk image format was removed. Only
RAW disk images are supported.
The following devices are supported by this initial release:
BUS - Altair (S-100) Bus
CPU - Intel 8080 / Zilog Z80
RAM - 64K RAM
ROM - ROMs
BRAM - Banked RAM
DSK - MITS 88-DCDD Floppy Disk Controller
M2SIO0 - MITS 88-2SIO Port 0
M2SIO1 - MITS 88-2SIO Port 1
SSW - Sense Switches
PO - Programmed Output
SIO - Generic Serial I/O
SBC200 - SD Systems SBC-200
TARBELL - Tarbell SD and DD Floppy Disk Controller
VFII - SD Systems VersaFloppy II
SIMH - SIMH Pseudo Device
- Invoking make with QUIET=0 (or in an exported environment variable)
will display the full compile and link commands executed.
- Invoking make with BUILD_SEPARATE=0 will cause each simulator
being built to be built with a single compile and link command.
This is how things were previously, but now the default has been
changed to more easily support active simulator development
by compiling files that have changed.
- Silence link time warning on macOS
- cleanup C++ support for ND100 and C++ builds of other simulators
This emulates the classic LINC. The design was settled in 1965,
increasing memory to 2048 words, and adding a Z register, an overflow
flag, and an interrupt facility.
Base vmnet support covers bridged network interfaces and locally
accessible TAP network connections. These reflect the vmnet bridged
and host behaviors which are leveraged under the covers, but configured
using the original sim_ether commands. The resulting bridged case
behaves like the Windows network connections do (with direct access
to and from the local LAN as well as the host system) using the natural
interface name. NAT behaviors are specifically supported using the
original SLiRP code since the vmnet support depends on simulators
primarily getting IPv4 addressing via DHCP, but essentially no simh
simulators actually had OS network code which used DHCP and all
merely used static network address setup. The vmnet (shared/NAT)
support can't be configured to operate with the same DHCP and static
IP addresses provided by the original SLiRP implementation and to
avoid the need to specifically change hard coded simulator IPv4
addresses before things could work.
- Detect which network interfaces are WiFi (when possible) and thus
not useful candidates for bridging.
- Cleanly report when running as root is needed.
- Avoid allowing network connections to interfaces which aren't
actually connected to a network.
- Add support to explicitly set TAP network host side network
interface's IPv4 address and netmask. This optional support is
provided specifically for the Apple vmnet case, but not for other
platforms using TAP network connections due to the various ways
that must be handled with external commands.
- Add host system's IPv4 address, netmask, media type and connection
state to interface descriptions visible via SHOW ETHERNET.
Some system environments may have a significant number of potential
network interfaces, most of which aren't interesting to connect
simulators to. Knowing which interfaces are actually in useful
states helps users select the correct device.
The vmnet aspect of this functionality was originally inspired by
Calvin Buckley's pull request to the open-simh repository. That
solution wouldn't actually operate well certainly for NAT cases due
to the forced DHCP to non-configurable address blocks and the lack
of any way to support static addresses TCP or UDP port mapping.
- Add new CP and CR devices
- COC: Zero delay from SIO to INIT state Detect and UEN on 0xFF order
- COC: Moved SIO int pending test to devices
- DK: Zero delay from SIO to INIT state
- DP: Added case points for RDEES, dp_aio_status
- DP: Zero delay from SIO to INIT state
- defs: Added chaining modifier flag
- defs: Fixed DVT_NODEV definition
- defs: Added chan_chk_dvi definition
- io: Added chaining modifier flag
- LP: Zero delay from SIO to INIT state
- LP: Added INIT test for illegal command
- LP: Moved SIO interrupt test to devices
- MT: Zero delay from SIO to INIT state
- PT: Zero delay from SIO to INIT state
- PT: Moved SIO interrupt test to devices
- RAD: Zero delay from SIO to INIT state
- RAD: Fixed nx unit test
- RAD: Fixed write protect test
- TT: Zero delay from SIO to INIT state
- TT: Moved SIO int pending test to devices
Adds the following devices to AltairZ80:
TUART0: Cromemco FDC controller TUART console port at I/O address 0x00.
TUART1: Cromemco TU-ART port A at I/O address 0x20.
TUART2: Cromemco TU-ART port B at I/I address 0x50.
These devices are fully TMXR capable.
Fix divide of 0 on KS10 processor.
Fix write access for auxiliary processor memory.
Updated support new PIDP10 panel.
Allow eight Unibux ports on the TEN device.
Added GE DATANET-760 device to PDP6
Removed USER mode restriction for idle detection.
Added Data Disc 6600 Television Display System.
Some host systems come with the libpcap shared object installed. If that
is the case, since the default build behavior is to dynamically load libpcap,
builds can now potentially avoid a forced install of the libpcap-devel package.
Josh's Altair/IMSAI Replacement (JAIR) is a single board computer
(SBC) for the S100 bus. I created this device to assist a friend
with getting IMP and CBBS working on his JAIR. Without having a
JAIR myself, AltairZ80 to the rescue!
The following devices are added:
JAIR - The main JAIR board I/O and ROM
JAIRS0 - Serial Port 0 (COM1)
JAIRS1 - Serial Port 1 (COM2)
JAIRP - Parallel Port
This was a bit challenging because the JAIR uses an on-board SD
card with FAT file system to hold its BIOS and CP/M disk images.
The ATTACH command is used to mount SD card images to the
simulator. The simulator emulates the SD card interface for
read/writing SD card sectors. These images are easily mounted on
a Mac making moving files around easy. I do not know about Windows.
These same images can be written to an SD card and used with real
JAIR hardware, which may be useful for JAIR owners.
The serial and parallel ports fully support TMXR. Host serial ports
and sockets may be attached to these devices.
I am working on a GitHub repository containing an SD card image and
init script that will boot CP/M 2.2 on the JAIR simulator.
Is this device one that should be added to AltairZ80?
If running as root on most platforms or running on macOS with Home
Brew package manager, any missing packages for maximal simulator
functionality can be automatically installed during the build.
All options which are currently and previously described in the comments
as allowing {option-name}=1 to enable, are now enabled if {option-name}
is defined to be anything at all,
Note: To avoid potential breakage of existing PDP11 configurations in
the wild, which may expect RP on RHA, TU on RHB and RS on RHC,
RPB is connected to RHD Massbus adapter.
- More robust recovery when Massbus configuration errors occur
- More complete RH{A,B,C,D} help
Removed TQ (TMSCP), TS (TSV11) and VH (DHV11) devices from this
simulator since these devices were never supported in release MicroVAX I
configurations.
Lacking a scatter/gather map, DMA devices needed to be written to
perform DMA into contigous buffers in low memory and then copy data
to user space buffers. The MSCP protocol devices had specific support to
do scatter/gather transfers as part of the protocol. The RL01/RL02 device
driver was modified to perform the appropriate buffer moves most likely
to prove the customer option to adjust their drivers actually worked. In
any case, boot support for RL01/RL02 disks does not exist.
