- The VAX 11/780 runs the VAX Diagnostic Supervisor the EVKAE (Privilege
Architecture Exercisor) tests cleanly.
All other Unibus VAXen execute different instructions in EVKAE
Test 8 (KERNEL STACK NOT VALID) subtest 2 when compared to the 11/780.
On these processors a REI instruction with reserved operands is invoked and
this causes a failure of this subtest for these processors.
We avoid this diagnostic test that fails.
- The VAX 8200 has some issues with the VAX Diagnostic Supervisor.
Specifically, the EVKAA (Hardware Core Instruction) test uses the processor
interval timer to measure the passage of time and expects the interrupts
that are generated to occur at IPL 24 (0x18). Meanwhile, the actual
hardware is documented to generate Interval Timer interrupts at
IPL 22 (0x16). EVKAA fails when interrupts occur at IPL 22(0x16).
If the processor is is built with Interval Timer interrupts at IPL 24(0x18),
then EVKAA passes, but the EVKAE (Privileged Architecture Exercisor)
Interval Timer test fails since the interval timer interrupts occur at
IPL 24(0x18) and not at IPL 22(0x16).
Once operating systems are running, operating system behavior will
generally be unaffected if Interval Timer interrupts occur at a higher
IPL than the OS expects, so the VAX 8200 is built that way and we avoid
the diagnostic that fails.
- The DEC supplied instruction diagnostics actually time the execution of
instructions being tested using the interval timer and the time of day
clock. When instructions take too long, they fail the test. The
VAX 11/730 simulator actually fails some of these instruction tests when
run at precisely .3 the instruction rate of the VAX/11 780. We therefore
adjust the nocalibrate execution rate to 320K vs the VAX 11/780 running
at 1000K.
- Extend maximum instruction history to 2 million
- -O option in history logging to a file allows only capturing at most
the last n instructions written to a log file. Otherwise, the
default is to log all executed instructions to the log file which will
consume prodigious amounts of storage.
- Make time at sim> prompt consistent when in nocalibrate mode.
- Disable asynch operations when in nocalibrate mode so that all events
occur consistently.
- Make sure that all throttling modes produce consistent behavior
related to all timing activities including clock ticks and TMXR port
speed timing.
- Expose all timer and throttling state variables via simh REGisters
- Only allow throttling to start execution one time. Throttling can't
be changed once instruction execution has started.
- Clarification of SHOW CLOCK variable units
- Avoid competing gratuitous keyboard polls with simulators
- Properly enable catchup ticks
- Fix second boot while idling
- Improve calibration while idling
- Report complete timer state when impossible timer conditions exist
that will cause a simulator abort.
- Leave memory 0 after pre-calibration instruction execution rate.
1 - Summarize repeated memory contents so that the memory range with a
given value only emits 2 lines of output
2 - Allow ^C (SIGINT) to potentially abort long running EXAMINE output
Discovered while getting standalone System Exerciser to run:
IO: DVT_NOTDEV macro incorrect, Device mapping algorithm creates false
dispatch points.
This mapped Multi Unit Controller and Single Unit Controller to same
device.
DP, DP, MT, RAD: Test for non-existent device returns wrong status.
DP, DK, MT: TIO status should return non-operational for unattached device.
Changing the CPU type or MEMORY size/configuration causes memory
resources mapped by other devices to be removed. This is not made
clear by "HELP CPU" and the user has no feedback that this is
happening.
This PR does the following:
1) HELP SET CPU shows that SET CPU MEMORY requires a value.
2) Feedback is provided if the value is omitted or not properly formatted.
3) Unmapped memory resources caused by a SET CPU command are displayed
on the SIMH console.
4) Adds a SET CPU RESIZEMEMORY command that resizes system memory
without unmapping other device memory resources.
Josh's Altair/IMSAI Replacement (JAIR) is a single board computer
(SBC) for the S100 bus. I created this device to assist a friend
with getting IMP and CBBS working on his JAIR. Without having a
JAIR myself, AltairZ80 to the rescue!
The following devices are added:
JAIR - The main JAIR board I/O and ROM
JAIRS0 - Serial Port 0 (COM1)
JAIRS1 - Serial Port 1 (COM2)
JAIRP - Parallel Port
This was a bit challenging because the JAIR uses an on-board SD
card with FAT file system to hold its BIOS and CP/M disk images.
The ATTACH command is used to mount SD card images to the
simulator. The simulator emulates the SD card interface for
read/writing SD card sectors. These images are easily mounted on
a Mac making moving files around easy. I do not know about Windows.
These same images can be written to an SD card and used with real
JAIR hardware, which may be useful for JAIR owners.
The serial and parallel ports fully support TMXR. Host serial ports
and sockets may be attached to these devices.
I am working on a GitHub repository containing an SD card image and
init script that will boot CP/M 2.2 on the JAIR simulator.
Is this device one that should be added to AltairZ80?
The Sol-20 provides 1K RAM at C800. This was discovered to be missing
when issuing a "SET CPU 24K" command. Without the CPU providing RAM
at C800, the Sol-20 would not function. This PR corrects the problem
by having the SOL20 device provide its own 1K RAM at C800.
- Make sure that asynchronous mode can't be changed if devices using
sim_ether are already attached.
- Add missing DEV_ETHER type flag for the only sim_ether using device
that didn't already have it.
I7010 updated to pass diagnostics.
I7080 updated to pass diagnostics.
I7090 updated to better pass 9IOT
updated to allow Stress and other applications to run better.
Updated card punch to allow input of card decks for overpunching.
