Mark Emmer 5b479c7ab2 SDS: Do not reload channel interlace register if already alerted ...

From actual monitor code, sequence used to read drum:
             EOD*  10000B   Alert Interlace
GDAC3: EOD    14202    I/O control mode EOD (mode 1)
                                        A=0  High order memory address bits
                                        Hicount=2 (Word count=04000=2KW)
             POT      GDBCL+2  Low-order memory address bits.
             RRF                    (EOD 2226) Read RAD file (mode 0)

Problem is that RRF is clearing the interlace information saved by the previous POT and sets up for a new POT. That is, in sds_io.c, mod 0 of op_eomd always assumes that a POT will follow if the channel is C or greater. Have to add tests of chan_flag.  If interlace is active, do not capture new information from this EOM/EOD.

Also removed superfluous trailing blanks from lines in file.

2014-03-02 22:24:28 -06:00

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