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1295 lines
54 KiB
C
1295 lines
54 KiB
C
/* sds_sbc200.c: SD Systems SBC-200
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Copyright (c) 2025 Patrick A. Linstruth
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and associated documentation files (the "Software"),
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to deal in the Software without restriction, including without limitation
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the rights to use, copy, modify, merge, publish, distribute, sublicense,
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and/or sell copies of the Software, and to permit persons to whom the
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Software is furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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PETER SCHORN BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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Except as contained in this notice, the name of Patrick Linstruth shall not
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be used in advertising or otherwise to promote the sale, use or other dealings
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in this Software without prior written authorization from Patrick Linstruth.
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History:
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07-Nov-2025 Initial version
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*/
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#include "sim_tmxr.h"
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#include "s100_bus.h"
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#include "s100_cpu.h"
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#define SBC200_NAME "SD SYSTEMS SBC-200"
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#define SBC200_SNAME "SBC200"
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#define SBC200_WAIT 250 /* Service Wait Interval */
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#define SBC200_IOBASE 0x78
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#define SBC200_IOSIZE 8
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#define SBC200_MON_BASE 0xe000
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#define SBC200_MON_SIZE 2048
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#define SBC200_MON_MASK (SBC200_MON_SIZE-1)
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#define SBC200_DDB_BASE 0xf000
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#define SBC200_DDB_SIZE 2048
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#define SBC200_DDB_MASK (SBC200_DDB_SIZE-1)
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RES sbc200_iores = { SBC200_IOBASE, SBC200_IOSIZE, 0x0000, 0 };
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RES sbc200_monres = { 0x00, 0, SBC200_MON_BASE, SBC200_MON_SIZE };
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RES sbc200_ddbres = { 0x00, 0, SBC200_DDB_BASE, SBC200_DDB_SIZE };
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#define SBC200_TRDY 0x01 /* Transmit Data Ready */
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#define SBC200_RDRF 0x02 /* Receive Data Register Full */
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#define SBC200_TDRE 0x04 /* Transmit Data Register Empty */
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#define SBC200_PE 0x08 /* Parity Error */
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#define SBC200_OVRN 0x10 /* Overrun */
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#define SBC200_FE 0x20 /* Framing Error */
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#define SBC200_DSR 0x80 /* Data Set Ready */
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#define SBC200_IR 0x40 /* Internal Reset */
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#define SBC200_CLK1 0x01 /* Divide Clock by 1 */
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#define SBC200_CLK16 0x02 /* Divide Clock by 16 */
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#define SBC200_CLK64 0x03 /* Divide Clock by 64 */
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#define SBC200_72E 0xf8 /* 7-2-E */
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#define SBC200_72O 0xd8 /* 7-2-O */
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#define SBC200_72N 0xc8 /* 7-2-O */
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#define SBC200_71E 0x78 /* 7-1-E */
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#define SBC200_71O 0x58 /* 7-1-O */
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#define SBC200_71N 0x48 /* 7-1-O */
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#define SBC200_82E 0xfc /* 8-2-E */
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#define SBC200_82O 0xdc /* 8-2-O */
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#define SBC200_82N 0xcc /* 8-2-O */
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#define SBC200_81E 0x7c /* 8-1-E */
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#define SBC200_81O 0xbc /* 8-1-O */
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#define SBC200_81N 0x4c /* 8-1-N */
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#define SBC200_FMTMSK 0xfc /* Length, Parity, Stop Mask */
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#define SBC200_DTR 0x02 /* RTS Bit Mask */
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#define SBC200_RTS 0x20 /* RTS Bit Mask */
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#define SBC200_RIE 0x80 /* Receive Int Enabled */
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#define SBC200_BAUD 9600 /* Default baud rate */
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/* SBC-200 Monitor 2.1 @ E000 */
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static uint8 sbc200_mon_rom[SBC200_MON_SIZE] = {
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0xc3, 0x0f, 0xe0, 0xc3, 0x79, 0xe0, 0xc3, 0x0f,
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0xe7, 0xc3, 0x17, 0xe7, 0xc3, 0x25, 0xe7, 0xdb,
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0x7f, 0x21, 0x60, 0xff, 0x22, 0xe6, 0xff, 0xaf,
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0x32, 0xc0, 0xff, 0x3e, 0x4e, 0xd3, 0x7d, 0x3e,
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0x37, 0xd3, 0x7d, 0x3e, 0x45, 0xd3, 0x78, 0x0e,
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0x7d, 0x11, 0x01, 0x00, 0xed, 0x78, 0xf2, 0x2c,
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0xe0, 0x13, 0xed, 0x78, 0xfa, 0x31, 0xe0, 0x31,
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0x59, 0xe0, 0xc1, 0xe1, 0x37, 0xed, 0x52, 0x38,
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0xf9, 0xc1, 0x3e, 0x40, 0xd3, 0x7d, 0x78, 0xd3,
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0x7d, 0x3e, 0x37, 0xd3, 0x7d, 0x79, 0xd3, 0x78,
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0x3e, 0x64, 0x06, 0xc8, 0x10, 0xfe, 0x3d, 0x20,
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0xf9, 0x18, 0x1c, 0x16, 0x00, 0x0d, 0x4e, 0x2c,
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0x00, 0x1a, 0x4e, 0x57, 0x00, 0x34, 0x4e, 0xae,
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0x00, 0x68, 0x4e, 0x5c, 0x01, 0xd0, 0x4e, 0xb8,
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0x02, 0x68, 0x4f, 0xff, 0x7f, 0xd0, 0x4f, 0xdb,
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0x7c, 0xaf, 0x32, 0xfa, 0xff, 0x3c, 0x32, 0xc6,
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0xff, 0x31, 0xc0, 0xff, 0xcd, 0x2f, 0xe7, 0x0e,
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0x2e, 0xcd, 0x0c, 0xe0, 0xcd, 0x21, 0xe7, 0xfe,
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0x2e, 0x28, 0xee, 0xc5, 0xcd, 0x39, 0xe7, 0xcd,
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0xb6, 0xe7, 0xc1, 0x79, 0x21, 0x81, 0xe0, 0xe5,
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0x2a, 0xd2, 0xff, 0xed, 0x5b, 0xd0, 0xff, 0xfd,
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0x21, 0xc0, 0xff, 0xfe, 0x42, 0x20, 0x3c, 0xd5,
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0x3a, 0xc0, 0xff, 0xcb, 0x47, 0x28, 0x10, 0xed,
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0x5b, 0xc4, 0xff, 0x21, 0xc1, 0xff, 0x01, 0x03,
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0x00, 0xed, 0xb0, 0xaf, 0x32, 0xc0, 0xff, 0x3a,
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0xc7, 0xff, 0xa7, 0xe1, 0x28, 0x19, 0x22, 0xc4,
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0xff, 0xe5, 0x11, 0xc1, 0xff, 0x01, 0x03, 0x00,
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0xc5, 0xed, 0xb0, 0x21, 0xe8, 0xe0, 0xc1, 0xd1,
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0xed, 0xb0, 0x3e, 0x01, 0x32, 0xc0, 0xff, 0xc9,
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0xc3, 0xd3, 0xe5, 0xfe, 0x47, 0x20, 0x13, 0x3a,
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0xc7, 0xff, 0xa7, 0x28, 0x05, 0xed, 0x53, 0xfe,
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0xff, 0xf1, 0x3e, 0x01, 0x32, 0xc9, 0xff, 0xc3,
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0x14, 0xe6, 0xfe, 0x52, 0x20, 0x06, 0xcd, 0x16,
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0xe1, 0xc3, 0x2d, 0xf0, 0xfe, 0x57, 0x20, 0x27,
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0xcd, 0x16, 0xe1, 0xc3, 0x30, 0xf0, 0x3a, 0xc7,
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0xff, 0xfe, 0x05, 0xda, 0x49, 0xe4, 0xed, 0x53,
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0x40, 0x00, 0x7d, 0x21, 0x42, 0x00, 0x77, 0x23,
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0x3a, 0xd6, 0xff, 0x77, 0x23, 0x3a, 0xd4, 0xff,
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0x77, 0x23, 0x3a, 0xd8, 0xff, 0x77, 0xc9, 0xfe,
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0x5a, 0x20, 0x45, 0x3a, 0xc7, 0xff, 0x3d, 0xc2,
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0x49, 0xe4, 0x7b, 0x32, 0x42, 0x00, 0xaf, 0x32,
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0x44, 0x00, 0x3c, 0x32, 0x43, 0x00, 0xcd, 0x18,
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0xf0, 0xdb, 0x63, 0xf6, 0x50, 0xd3, 0x63, 0xcd,
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0x33, 0xf0, 0xcd, 0x6e, 0xe1, 0x28, 0x07, 0xcb,
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0xa7, 0xd3, 0x63, 0xcd, 0x33, 0xf0, 0xcd, 0x73,
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0xe1, 0x20, 0xe6, 0xc3, 0x18, 0xf0, 0xdb, 0x63,
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0xcb, 0x6f, 0xc9, 0x3a, 0x44, 0x00, 0x3c, 0x32,
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0x44, 0x00, 0x47, 0x3a, 0x40, 0xf0, 0xb8, 0xc9,
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0xfe, 0x51, 0x20, 0x34, 0x7b, 0x32, 0x42, 0x00,
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0xaf, 0x32, 0x44, 0x00, 0x3e, 0x01, 0x32, 0x43,
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0x00, 0x3a, 0x3f, 0xf0, 0x47, 0xcd, 0x6e, 0xe1,
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0x28, 0x02, 0xcb, 0x20, 0x78, 0x32, 0x45, 0x00,
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0x21, 0x00, 0x01, 0x22, 0x40, 0x00, 0xcd, 0x2d,
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0xf0, 0xcd, 0xbe, 0xe5, 0xcd, 0x73, 0xe1, 0x20,
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0xdb, 0x0e, 0x50, 0xcd, 0x0c, 0xe0, 0x18, 0xd0,
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0xfe, 0x4d, 0x20, 0x23, 0xcd, 0xcb, 0xe5, 0x44,
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0x4d, 0xeb, 0xed, 0x5b, 0xd4, 0xff, 0xb7, 0xed,
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0x52, 0x30, 0x0e, 0x2a, 0xd4, 0xff, 0x09, 0x2b,
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0x54, 0x5d, 0x2a, 0xd2, 0xff, 0xed, 0xb8, 0x18,
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0x05, 0x2a, 0xd0, 0xff, 0xed, 0xb0, 0xc9, 0xfe,
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0x43, 0xca, 0x03, 0xf0, 0xfe, 0x48, 0x20, 0x1d,
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0xe5, 0x19, 0x0e, 0x2b, 0xcd, 0x0c, 0xe0, 0xcd,
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0xf0, 0xe7, 0xcd, 0x39, 0xe7, 0xe1, 0xeb, 0xb7,
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0xed, 0x52, 0x0e, 0x2d, 0xcd, 0x0c, 0xe0, 0xcd,
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0xf0, 0xe7, 0xc3, 0x81, 0xe0, 0xfe, 0x58, 0x20,
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0x15, 0xaf, 0xbb, 0xc4, 0x3e, 0xe7, 0x3a, 0xc7,
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0xff, 0xfe, 0x02, 0x20, 0x06, 0x3a, 0xd2, 0xff,
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0x32, 0xc6, 0xff, 0xc3, 0x88, 0xe6, 0xfe, 0x49,
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0x20, 0x36, 0xfd, 0xcb, 0x0a, 0x86, 0x3a, 0xd0,
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0xff, 0x4f, 0x06, 0x01, 0x3a, 0xc7, 0xff, 0xfe,
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0x02, 0x38, 0x0b, 0x3a, 0xd2, 0xff, 0x47, 0xb7,
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0x20, 0x04, 0xfd, 0xcb, 0x0a, 0xc6, 0x79, 0xcd,
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0xf5, 0xe7, 0xed, 0x78, 0xcd, 0xf5, 0xe7, 0xcd,
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0xbe, 0xe5, 0xc5, 0xcd, 0x2f, 0xe7, 0xc1, 0xfd,
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0xcb, 0x0a, 0x46, 0x20, 0xe9, 0x10, 0xe7, 0xc9,
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0xfe, 0x4f, 0x20, 0x2e, 0xfd, 0xcb, 0x0a, 0x86,
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0x3a, 0xd0, 0xff, 0x4f, 0x3a, 0xd2, 0xff, 0x57,
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0x06, 0x01, 0x3a, 0xc7, 0xff, 0xfe, 0x03, 0x38,
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0x0b, 0x3a, 0xd4, 0xff, 0x47, 0xb7, 0x20, 0x04,
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0xfd, 0xcb, 0x0a, 0xc6, 0xed, 0x51, 0xcd, 0xbe,
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0xe5, 0xfd, 0xcb, 0x0a, 0x46, 0x20, 0xf5, 0x10,
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0xf3, 0xc9, 0xfe, 0x46, 0x20, 0x12, 0x3a, 0xd4,
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0xff, 0xe5, 0xcd, 0xcb, 0xe5, 0xe1, 0x12, 0xe5,
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0xb7, 0xed, 0x52, 0xe1, 0x13, 0x20, 0xf7, 0xc9,
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0xfe, 0x4c, 0x20, 0x4d, 0xcd, 0xcb, 0xe5, 0x3a,
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0xc7, 0xff, 0xd6, 0x03, 0xda, 0x49, 0xe4, 0x47,
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0x3c, 0x32, 0xc7, 0xff, 0x21, 0xd5, 0xff, 0x11,
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0xd6, 0xff, 0x1a, 0x77, 0x23, 0x13, 0x13, 0x10,
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0xf9, 0x3a, 0xc7, 0xff, 0x47, 0x2a, 0xd0, 0xff,
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0x11, 0xd4, 0xff, 0x1a, 0xbe, 0x20, 0x10, 0x23,
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0x13, 0x10, 0xf8, 0x2a, 0xd0, 0xff, 0xcd, 0xf0,
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0xe7, 0xcd, 0x2f, 0xe7, 0xcd, 0xbe, 0xe5, 0x2a,
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0xd2, 0xff, 0xed, 0x5b, 0xd0, 0xff, 0xb7, 0xed,
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0x52, 0xc8, 0x13, 0xed, 0x53, 0xd0, 0xff, 0x18,
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0xd0, 0xfe, 0x56, 0x20, 0x38, 0xcd, 0xcb, 0xe5,
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0xe5, 0xc1, 0xeb, 0xed, 0x5b, 0xd4, 0xff, 0x1a,
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0xed, 0xa1, 0x13, 0x20, 0x03, 0xe0, 0x18, 0xf7,
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0xf5, 0xc5, 0xd5, 0x2b, 0xcd, 0xf0, 0xe7, 0x7e,
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0x23, 0xcd, 0xf5, 0xe7, 0xd1, 0xd5, 0xe5, 0xeb,
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0x2b, 0xcd, 0xf0, 0xe7, 0x7e, 0xcd, 0x4d, 0xe7,
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0xcd, 0x2f, 0xe7, 0xe1, 0xd1, 0xc1, 0xf1, 0xe0,
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0xcd, 0xbe, 0xe5, 0x18, 0xd2, 0xfe, 0x54, 0x20,
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0x3f, 0xeb, 0x13, 0x06, 0x00, 0x2a, 0xd0, 0xff,
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0x7d, 0xac, 0xa8, 0x77, 0x23, 0xe5, 0xb7, 0xed,
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0x52, 0xe1, 0x20, 0xf4, 0x2a, 0xd0, 0xff, 0x7d,
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0xac, 0xa8, 0xbe, 0xc4, 0x61, 0xe3, 0x23, 0xe5,
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0xb7, 0xed, 0x52, 0xe1, 0x20, 0xf1, 0x04, 0xcd,
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0xbe, 0xe5, 0x0e, 0x50, 0xcd, 0x0c, 0xe0, 0x18,
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0xd4, 0xf5, 0xcd, 0xf0, 0xe7, 0xf1, 0xcd, 0xf5,
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0xe7, 0x7e, 0xcd, 0xf5, 0xe7, 0xc3, 0x2f, 0xe7,
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0xfe, 0x44, 0x20, 0x5d, 0xfd, 0xcb, 0x0a, 0x86,
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0xeb, 0x3a, 0xc7, 0xff, 0xfe, 0x02, 0x30, 0x09,
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0x11, 0xff, 0x00, 0xe5, 0x19, 0x22, 0xd2, 0xff,
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0xe1, 0xcd, 0x2f, 0xe7, 0xe5, 0xc1, 0xe5, 0x2a,
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0xd2, 0xff, 0xb7, 0xed, 0x42, 0xda, 0x49, 0xe4,
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0x01, 0x0f, 0x00, 0xb7, 0xed, 0x42, 0x06, 0x10,
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0x28, 0x06, 0xd2, 0xac, 0xe3, 0x7d, 0x80, 0x47,
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0xfd, 0xcb, 0x0a, 0xc6, 0xe1, 0xc5, 0xcd, 0xf0,
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0xe7, 0xc1, 0xcd, 0xa8, 0xe6, 0xcd, 0xbe, 0xe5,
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0xfd, 0xcb, 0x0a, 0x46, 0x28, 0xcb, 0xcd, 0x09,
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0xe0, 0xfe, 0x2e, 0xc8, 0xfe, 0x20, 0x20, 0xf6,
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0xfd, 0xcb, 0x0a, 0x86, 0xcd, 0x2f, 0xe7, 0x18,
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0xaf, 0xfe, 0x45, 0x20, 0x38, 0xeb, 0xcd, 0xf0,
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0xe7, 0x7e, 0xcd, 0x4d, 0xe7, 0x0e, 0x2d, 0xcd,
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0x0c, 0xe0, 0xe5, 0xcd, 0xb6, 0xe7, 0xe1, 0x3a,
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0xc8, 0xff, 0xfe, 0x2e, 0xc8, 0x3a, 0xc7, 0xff,
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0xe6, 0x03, 0x28, 0x0f, 0x3a, 0xd0, 0xff, 0x77,
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0x23, 0x3a, 0xc8, 0xff, 0xfe, 0x0d, 0x28, 0xd6,
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0x2b, 0x18, 0xd3, 0x3a, 0xc8, 0xff, 0xfe, 0x5e,
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0x28, 0xf6, 0x23, 0x18, 0xc9, 0xfe, 0x50, 0x20,
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0x34, 0x3a, 0xd0, 0xff, 0x4f, 0x79, 0xcd, 0xf5,
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0xe7, 0xed, 0x78, 0xcd, 0xf5, 0xe7, 0xc5, 0xcd,
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0xb6, 0xe7, 0xc1, 0x3a, 0xc8, 0xff, 0xfe, 0x2e,
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0xc8, 0x67, 0x3a, 0xc7, 0xff, 0xa7, 0x28, 0x0d,
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0x3a, 0xd0, 0xff, 0xed, 0x79, 0x3e, 0x5e, 0xbc,
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0x28, 0xdb, 0x0c, 0x18, 0xd8, 0x3e, 0x5e, 0xbc,
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0x20, 0xf8, 0x0d, 0x18, 0xd0, 0xfe, 0x53, 0x28,
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0x08, 0x0e, 0x3f, 0xcd, 0x0c, 0xe0, 0xc3, 0x81,
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0xe0, 0xf1, 0xcd, 0x3e, 0xe7, 0x3a, 0xc7, 0xff,
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0xa7, 0x28, 0x04, 0xeb, 0x22, 0xfe, 0xff, 0x3a,
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0xd2, 0xff, 0xa7, 0x20, 0x01, 0x3c, 0x32, 0xc9,
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0xff, 0xaf, 0x32, 0xc7, 0xff, 0xcd, 0xaf, 0xe0,
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0xed, 0x5b, 0xfe, 0xff, 0x1a, 0xfe, 0x40, 0x38,
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0x05, 0xfe, 0xc0, 0xda, 0x53, 0xe5, 0xe6, 0x03,
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0x47, 0x1a, 0x1f, 0x1f, 0xe6, 0x1f, 0xc5, 0x01,
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0x9a, 0xe5, 0x81, 0x6f, 0x60, 0xc1, 0x7e, 0x04,
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0x10, 0x29, 0xe6, 0x03, 0xca, 0x3e, 0xe5, 0xf5,
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0x1a, 0x2a, 0xf4, 0xff, 0xfe, 0xe9, 0xca, 0x07,
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0xe6, 0xfe, 0xc3, 0x28, 0x70, 0xfe, 0xcd, 0x28,
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0x6c, 0xfe, 0xc9, 0x28, 0x5f, 0xfe, 0x10, 0x20,
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0x10, 0x21, 0xf9, 0xff, 0x35, 0x20, 0x47, 0x34,
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0xc3, 0x74, 0xe5, 0xcb, 0x3f, 0xcb, 0x3f, 0x18,
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0xcf, 0xfe, 0x18, 0x28, 0x39, 0xfe, 0x80, 0x30,
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0x0a, 0xee, 0x20, 0x47, 0xe6, 0x67, 0x20, 0xe8,
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0x78, 0x18, 0x0d, 0xe6, 0xc7, 0xfe, 0xc2, 0x28,
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0x06, 0xe6, 0xc3, 0xfe, 0xc0, 0x20, 0x43, 0x1a,
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|
0xe6, 0x30, 0x21, 0xb9, 0xe5, 0x23, 0xd6, 0x10,
|
|
0x30, 0xfb, 0x3a, 0xfc, 0xff, 0xa6, 0x1a, 0x28,
|
|
0x01, 0x2f, 0xcb, 0x5f, 0x20, 0xc2, 0xf1, 0xf5,
|
|
0xfe, 0x02, 0x38, 0x10, 0x20, 0x17, 0x13, 0x1a,
|
|
0x13, 0x6f, 0x17, 0x26, 0x00, 0x30, 0x01, 0x25,
|
|
0x19, 0x18, 0x30, 0x1b, 0x2a, 0xe6, 0xff, 0x7e,
|
|
0x23, 0x66, 0x6f, 0x18, 0x64, 0x1a, 0xcb, 0x57,
|
|
0x13, 0x1a, 0x6f, 0x13, 0x1a, 0x67, 0x20, 0x59,
|
|
0x18, 0x19, 0x1a, 0xe6, 0xc7, 0xfe, 0xc7, 0x1a,
|
|
0x20, 0x07, 0xe6, 0x38, 0x6f, 0x26, 0x00, 0x18,
|
|
0x48, 0xfe, 0xfb, 0x20, 0x3f, 0x2f, 0x32, 0xfa,
|
|
0xff, 0xeb, 0x23, 0xc3, 0x07, 0xe6, 0x1a, 0x13,
|
|
0xfe, 0xed, 0x20, 0x13, 0x06, 0x03, 0x1a, 0xe6,
|
|
0xf7, 0xfe, 0x45, 0x28, 0xbe, 0xe6, 0xc7, 0xfe,
|
|
0x43, 0x28, 0x22, 0x06, 0x01, 0x18, 0x1e, 0xfe,
|
|
0xdd, 0x2a, 0xea, 0xff, 0x28, 0x03, 0x2a, 0xe8,
|
|
0xff, 0x1a, 0xfe, 0xe9, 0x28, 0xd5, 0x21, 0x95,
|
|
0xe5, 0x01, 0x05, 0x00, 0xed, 0xb1, 0x20, 0x0f,
|
|
0x04, 0x04, 0x04, 0xc5, 0xc1, 0xeb, 0x23, 0x10,
|
|
0xfd, 0xcd, 0xce, 0xe0, 0xc3, 0x14, 0xe6, 0xe6,
|
|
0xfe, 0xfe, 0x34, 0x28, 0xec, 0x1a, 0xe6, 0x07,
|
|
0xfe, 0x06, 0x28, 0xe5, 0x1a, 0xe6, 0xf8, 0xfe,
|
|
0x70, 0x28, 0xde, 0x18, 0xdd, 0x21, 0x22, 0x2a,
|
|
0x36, 0xcb, 0x5d, 0x65, 0x55, 0x65, 0x5e, 0x65,
|
|
0x56, 0x65, 0x7e, 0x65, 0x76, 0x65, 0x7e, 0x65,
|
|
0x76, 0x65, 0xf5, 0x67, 0xb5, 0x6f, 0xb5, 0x67,
|
|
0xb5, 0x63, 0x75, 0x67, 0x75, 0x63, 0x75, 0x67,
|
|
0x75, 0x63, 0x40, 0x01, 0x04, 0x80, 0xcd, 0x06,
|
|
0xe0, 0xc8, 0xcd, 0x09, 0xe0, 0xfe, 0x2e, 0xc0,
|
|
0xc3, 0x81, 0xe0, 0xb7, 0xed, 0x52, 0xda, 0x49,
|
|
0xe4, 0x23, 0xc9, 0xed, 0x73, 0xe6, 0xff, 0x31,
|
|
0x00, 0x00, 0xf5, 0xf5, 0xb7, 0xed, 0x57, 0xf5,
|
|
0xf3, 0xc5, 0xd5, 0xe5, 0xd9, 0x08, 0xf5, 0xc5,
|
|
0xd5, 0xe5, 0x3a, 0xfa, 0xff, 0xe6, 0x04, 0x32,
|
|
0xfa, 0xff, 0xd9, 0x08, 0xdd, 0xe5, 0xfd, 0xe5,
|
|
0x21, 0xc1, 0xff, 0xed, 0x5b, 0xc4, 0xff, 0x01,
|
|
0x03, 0x00, 0xed, 0xb0, 0x2a, 0xc4, 0xff, 0x3e,
|
|
0x80, 0x32, 0xc0, 0xff, 0x22, 0xfe, 0xff, 0x31,
|
|
0xc0, 0xff, 0x18, 0x32, 0xed, 0x7b, 0xe6, 0xff,
|
|
0x2a, 0xfe, 0xff, 0xe5, 0x2a, 0xfc, 0xff, 0xe5,
|
|
0xed, 0x73, 0xe4, 0xff, 0x31, 0xe8, 0xff, 0xfd,
|
|
0xe1, 0xdd, 0xe1, 0xd9, 0x08, 0xe1, 0xd1, 0xc1,
|
|
0xf1, 0xd9, 0x08, 0xe1, 0xd1, 0xc1, 0xf1, 0xed,
|
|
0x47, 0xed, 0x7b, 0xe4, 0xff, 0xea, 0x43, 0xe6,
|
|
0xf1, 0xf3, 0xc9, 0xf1, 0xfb, 0xc9, 0xcd, 0x88,
|
|
0xe6, 0x3a, 0xc0, 0xff, 0x47, 0xaf, 0x32, 0xc0,
|
|
0xff, 0x21, 0xc9, 0xff, 0x35, 0x28, 0x07, 0xcd,
|
|
0x06, 0xe0, 0x20, 0x02, 0x18, 0x23, 0xcd, 0x21,
|
|
0xe7, 0xfe, 0x2e, 0xca, 0x81, 0xe0, 0xfe, 0x0d,
|
|
0x28, 0x15, 0xfe, 0x20, 0x20, 0xf0, 0xaf, 0xbe,
|
|
0x36, 0x00, 0x20, 0xea, 0xcd, 0x2f, 0xe7, 0xcd,
|
|
0x3e, 0xe7, 0x3e, 0x0b, 0xc3, 0x66, 0xe4, 0x36,
|
|
0x01, 0xcd, 0x2f, 0xe7, 0x7e, 0xc3, 0x66, 0xe4,
|
|
0x2a, 0xfe, 0xff, 0xcd, 0xf0, 0xe7, 0x3a, 0xc6,
|
|
0xff, 0x1f, 0x06, 0x01, 0x30, 0x02, 0x06, 0x0c,
|
|
0x21, 0xfd, 0xff, 0x7e, 0xcd, 0x4d, 0xe7, 0x2b,
|
|
0x7e, 0xcd, 0xf5, 0xe7, 0x2b, 0x10, 0xf4, 0xc9,
|
|
0xc5, 0xe5, 0x7e, 0xcd, 0xf5, 0xe7, 0x23, 0x10,
|
|
0xf9, 0xcd, 0x39, 0xe7, 0xcd, 0x39, 0xe7, 0xe1,
|
|
0xc1, 0x7e, 0xe6, 0x7f, 0x4f, 0xfe, 0x20, 0x38,
|
|
0x04, 0xfe, 0x7b, 0x38, 0x02, 0x0e, 0x2e, 0xcd,
|
|
0x0c, 0xe0, 0x23, 0x10, 0xec, 0xc9, 0x50, 0x43,
|
|
0x20, 0x20, 0x20, 0x41, 0x46, 0x20, 0x20, 0x49,
|
|
0x20, 0x49, 0x46, 0x20, 0x20, 0x42, 0x43, 0x20,
|
|
0x20, 0x20, 0x44, 0x45, 0x20, 0x20, 0x20, 0x48,
|
|
0x4c, 0x20, 0x20, 0x41, 0x27, 0x46, 0x27, 0x20,
|
|
0x42, 0x27, 0x43, 0x27, 0x20, 0x44, 0x27, 0x45,
|
|
0x27, 0x20, 0x48, 0x27, 0x4c, 0x27, 0x20, 0x20,
|
|
0x49, 0x58, 0x20, 0x20, 0x20, 0x49, 0x59, 0x20,
|
|
0x20, 0x20, 0x53, 0x50, 0x0d, 0x0a, 0x03, 0xdb,
|
|
0x7d, 0xe6, 0x02, 0xc8, 0x3e, 0xff, 0xc9, 0xcd,
|
|
0x0f, 0xe7, 0x28, 0xfb, 0xdb, 0x7c, 0xe6, 0x7f,
|
|
0xc9, 0xcd, 0x09, 0xe0, 0x4f, 0xdb, 0x7d, 0xe6,
|
|
0x01, 0x28, 0xfa, 0x79, 0xd3, 0x7c, 0xc9, 0x0e,
|
|
0x0d, 0xcd, 0x0c, 0xe0, 0x0e, 0x0a, 0xc3, 0x0c,
|
|
0xe0, 0x0e, 0x20, 0xc3, 0x0c, 0xe0, 0x21, 0xce,
|
|
0xe6, 0x7e, 0xfe, 0x03, 0xc8, 0x4f, 0xcd, 0x0c,
|
|
0xe0, 0x23, 0x18, 0xf5, 0x00, 0xf5, 0x0f, 0x0f,
|
|
0x0f, 0x0f, 0xcd, 0x56, 0xe7, 0xf1, 0xe6, 0x0f,
|
|
0xc6, 0x90, 0x27, 0xce, 0x40, 0x27, 0x4f, 0xc3,
|
|
0x0c, 0xe0, 0xd6, 0x30, 0xfe, 0x0a, 0xf8, 0xd6,
|
|
0x07, 0xc9, 0xfe, 0x30, 0x38, 0x0e, 0xfe, 0x3a,
|
|
0x38, 0x08, 0xfe, 0x40, 0x38, 0x06, 0xfe, 0x47,
|
|
0x30, 0x02, 0xaf, 0xc9, 0xaf, 0x3c, 0xc9, 0xfe,
|
|
0x20, 0xc8, 0xfe, 0x5e, 0x28, 0x08, 0xfe, 0x2e,
|
|
0xca, 0x81, 0xe0, 0xfe, 0x0d, 0xc0, 0xc5, 0xcd,
|
|
0x2f, 0xe7, 0xc1, 0xaf, 0xc9, 0xe5, 0xe5, 0xe5,
|
|
0xe5, 0xe5, 0x21, 0x00, 0x00, 0x45, 0xcd, 0x21,
|
|
0xe7, 0x04, 0xcd, 0x7f, 0xe7, 0xc8, 0xcd, 0x6a,
|
|
0xe7, 0xc0, 0x79, 0xcd, 0x62, 0xe7, 0x29, 0x29,
|
|
0x29, 0x29, 0x85, 0x6f, 0x18, 0xe8, 0xaf, 0x21,
|
|
0xd0, 0xff, 0xe5, 0xdd, 0xe1, 0x77, 0x01, 0x09,
|
|
0x00, 0x11, 0xd1, 0xff, 0xed, 0xb0, 0x32, 0xc7,
|
|
0xff, 0xcd, 0x9a, 0xe7, 0xc2, 0x49, 0xe4, 0x79,
|
|
0x32, 0xc8, 0xff, 0xfe, 0x20, 0x28, 0x02, 0x05,
|
|
0xc8, 0xdd, 0x75, 0x00, 0xdd, 0x74, 0x01, 0x3a,
|
|
0xc7, 0xff, 0x3c, 0x32, 0xc7, 0xff, 0xdd, 0x23,
|
|
0xdd, 0x23, 0x79, 0xfe, 0x20, 0x28, 0xda, 0xc9,
|
|
0x7c, 0xcd, 0x4d, 0xe7, 0x7d, 0xc5, 0xcd, 0x4d,
|
|
0xe7, 0xcd, 0x39, 0xe7, 0xc1, 0xc9, 0xff, 0xff,
|
|
};
|
|
|
|
/* SBC-200 DDBIOS 3.3 @ F000 */
|
|
static uint8 sbc200_ddb_rom[SBC200_DDB_SIZE] = {
|
|
0x00, 0x1e, 0x00, 0xc3, 0x6c, 0xf0, 0xc3, 0x06,
|
|
0xe0, 0xc3, 0x09, 0xe0, 0xc3, 0x0c, 0xe0, 0xc3,
|
|
0x1b, 0xf1, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
|
0xc3, 0x6a, 0xf1, 0xc3, 0x79, 0xf1, 0xc3, 0x7e,
|
|
0xf1, 0xc3, 0x83, 0xf1, 0xc3, 0x88, 0xf1, 0xc3,
|
|
0x8d, 0xf1, 0xc3, 0xa9, 0xf1, 0xc3, 0xc3, 0xf3,
|
|
0xc3, 0xd0, 0xf3, 0xc3, 0x14, 0xf4, 0x00, 0x3a,
|
|
0x80, 0x00, 0x5f, 0x16, 0x00, 0x21, 0x80, 0x1a,
|
|
0x4d, 0x49, 0x06, 0x0b, 0x1b, 0x08, 0x18, 0x1c,
|
|
0x32, 0x4d, 0x54, 0x08, 0x16, 0x10, 0x08, 0x18,
|
|
0x1c, 0x1a, 0x4d, 0x2e, 0x08, 0x16, 0x36, 0x08,
|
|
0x18, 0x1c, 0x12, 0x23, 0x0c, 0x06, 0x0b, 0x08,
|
|
0x0b, 0x1b, 0x1f, 0x1d, 0x23, 0x54, 0x08, 0x16,
|
|
0x10, 0x0b, 0x1b, 0x1f, 0x31, 0x80, 0x00, 0xdb,
|
|
0x7f, 0x3e, 0x00, 0x32, 0x42, 0x00, 0x7b, 0xfe,
|
|
0x04, 0xd2, 0x03, 0xe8, 0xf5, 0x3e, 0xef, 0xe5,
|
|
0xed, 0x73, 0x4d, 0x00, 0xe1, 0x0f, 0x30, 0x1a,
|
|
0xd3, 0x63, 0xcd, 0xb7, 0xf3, 0xe6, 0x04, 0x28,
|
|
0x0d, 0xaf, 0xd3, 0x65, 0x3e, 0x02, 0x32, 0x44,
|
|
0x00, 0x3e, 0x1a, 0xcd, 0x0a, 0xf3, 0xdb, 0x63,
|
|
0x18, 0xe3, 0xf1, 0xf5, 0xcd, 0x6a, 0xf1, 0xf1,
|
|
0xcd, 0x1b, 0xf1, 0x20, 0x19, 0xcd, 0xd0, 0xf0,
|
|
0x21, 0x80, 0x00, 0x7e, 0xe6, 0xce, 0x20, 0x05,
|
|
0xcb, 0x46, 0xc2, 0x80, 0x00, 0x3e, 0x31, 0x21,
|
|
0x00, 0xe8, 0xbe, 0xca, 0x00, 0xe8, 0x3e, 0xe0,
|
|
0x21, 0x02, 0xe0, 0xbe, 0xca, 0x03, 0xe0, 0x76,
|
|
0x21, 0x80, 0x00, 0x22, 0x40, 0x00, 0xaf, 0x32,
|
|
0x44, 0x00, 0x3c, 0x32, 0x43, 0x00, 0xcd, 0x8d,
|
|
0xf1, 0xc8, 0x18, 0xe2, 0x3a, 0x42, 0x00, 0x5f,
|
|
0x3e, 0x04, 0xb8, 0x28, 0x19, 0x3d, 0xb8, 0x28,
|
|
0x0c, 0x3d, 0xb8, 0x28, 0x18, 0x3d, 0xb8, 0x28,
|
|
0x1b, 0xf6, 0x01, 0xe1, 0xc9, 0x7b, 0xcb, 0xb7,
|
|
0xcb, 0xbf, 0x32, 0x42, 0x00, 0xc9, 0x7b, 0xcb,
|
|
0xff, 0x32, 0x42, 0x00, 0xc9, 0x7b, 0xcb, 0xef,
|
|
0x32, 0x42, 0x00, 0xc9, 0x7b, 0xcb, 0xf7, 0x32,
|
|
0x42, 0x00, 0xc9, 0x06, 0x04, 0xe6, 0x0f, 0xf6,
|
|
0x40, 0x32, 0x42, 0x00, 0x2a, 0x40, 0x00, 0x22,
|
|
0x51, 0x00, 0xcd, 0x4d, 0xf1, 0x2a, 0x51, 0x00,
|
|
0x22, 0x40, 0x00, 0x3a, 0x42, 0x00, 0xc0, 0x30,
|
|
0x02, 0xcb, 0xff, 0x5f, 0x3a, 0x49, 0x00, 0xb7,
|
|
0x7b, 0xcb, 0xa7, 0xf2, 0x48, 0xf1, 0xcb, 0xe7,
|
|
0x32, 0x42, 0x00, 0xaf, 0xc9, 0xc5, 0xdd, 0xe5,
|
|
0xe5, 0xed, 0x73, 0x4d, 0x00, 0xe1, 0xcd, 0xe4,
|
|
0xf1, 0xcd, 0x37, 0xf2, 0xdd, 0xe1, 0xc1, 0x3a,
|
|
0x4b, 0x00, 0x0f, 0xc8, 0x05, 0xcd, 0xe4, 0xf0,
|
|
0x18, 0xe3, 0xed, 0x73, 0x4d, 0x00, 0xdd, 0xe5,
|
|
0xcd, 0xe4, 0xf1, 0xcd, 0xd8, 0xf1, 0xdd, 0xe1,
|
|
0xc9, 0x79, 0x32, 0x42, 0x00, 0xc9, 0x79, 0x32,
|
|
0x44, 0x00, 0xc9, 0x79, 0x32, 0x43, 0x00, 0xc9,
|
|
0xed, 0x43, 0x40, 0x00, 0xc9, 0x01, 0x01, 0x03,
|
|
0xed, 0x43, 0x56, 0x00, 0xdd, 0xe5, 0xdd, 0x2a,
|
|
0x53, 0x00, 0xc5, 0xcd, 0x6c, 0xf2, 0xc1, 0x28,
|
|
0x05, 0xcd, 0xc2, 0xf1, 0x18, 0xf4, 0xdd, 0xe1,
|
|
0xc9, 0x01, 0x01, 0x03, 0xed, 0x43, 0x56, 0x00,
|
|
0xdd, 0xe5, 0xdd, 0x2a, 0x53, 0x00, 0xc5, 0xcd,
|
|
0xbd, 0xf2, 0xc1, 0x28, 0xe9, 0xcd, 0xc2, 0xf1,
|
|
0x18, 0xf4, 0x10, 0x13, 0x3a, 0x57, 0x00, 0x47,
|
|
0x0d, 0xf2, 0xd2, 0xf1, 0xf1, 0xdd, 0xe1, 0xaf,
|
|
0x3c, 0xc9, 0xc5, 0xcd, 0xd8, 0xf1, 0xc1, 0xc9,
|
|
0xed, 0x73, 0x4d, 0x00, 0xdd, 0x7e, 0x06, 0xcd,
|
|
0x0a, 0xf3, 0xaf, 0xc9, 0x11, 0x42, 0x00, 0x1a,
|
|
0xe6, 0xe0, 0x4f, 0x1a, 0xe6, 0x03, 0x47, 0x3e,
|
|
0x01, 0x28, 0x03, 0x07, 0x10, 0xfd, 0xb1, 0xe6,
|
|
0x7f, 0x47, 0x79, 0xdd, 0x21, 0x3f, 0xf0, 0xfe,
|
|
0x00, 0x28, 0x1c, 0xdd, 0x21, 0x48, 0xf0, 0xfe,
|
|
0x40, 0x28, 0x14, 0xdd, 0x21, 0x51, 0xf0, 0xfe,
|
|
0xc0, 0x28, 0x0c, 0xdd, 0x21, 0x5a, 0xf0, 0xfe,
|
|
0x20, 0x28, 0x04, 0xdd, 0x21, 0x63, 0xf0, 0xdd,
|
|
0x22, 0x53, 0x00, 0xc5, 0xf1, 0x2f, 0xd3, 0x63,
|
|
0x1a, 0x32, 0x55, 0x00, 0xcd, 0x59, 0xf2, 0xdb,
|
|
0x64, 0xe6, 0x80, 0xc2, 0xe1, 0xf2, 0xc9, 0xcd,
|
|
0x42, 0xf3, 0x21, 0x48, 0x00, 0x01, 0x67, 0x06,
|
|
0x3e, 0xf8, 0x32, 0x46, 0x00, 0xcd, 0x75, 0xf3,
|
|
0x3e, 0xc0, 0xcd, 0x77, 0xf2, 0x3a, 0x48, 0x00,
|
|
0xfe, 0x4d, 0xd2, 0xfe, 0xf2, 0xd3, 0x65, 0xaf,
|
|
0xc9, 0x3a, 0x42, 0x00, 0xcb, 0x6f, 0x3e, 0x27,
|
|
0x28, 0x02, 0x3e, 0x3c, 0x06, 0x00, 0x10, 0xfe,
|
|
0x3d, 0x20, 0xf9, 0xc9, 0xcd, 0x9c, 0xf2, 0x3e,
|
|
0x88, 0xcd, 0x90, 0xf2, 0x2a, 0x40, 0x00, 0x32,
|
|
0x4c, 0x00, 0xed, 0x5b, 0x4c, 0x00, 0xd5, 0xf3,
|
|
0xd3, 0x64, 0x18, 0x00, 0x18, 0x00, 0xed, 0xb2,
|
|
0xd1, 0xed, 0x53, 0x4c, 0x00, 0xfb, 0x18, 0x45,
|
|
0x67, 0x3a, 0x49, 0x00, 0x6f, 0xe6, 0x01, 0x7c,
|
|
0xc8, 0xcb, 0xcf, 0xc9, 0xe1, 0xed, 0x73, 0x4d,
|
|
0x00, 0xe5, 0x3a, 0x42, 0x00, 0x57, 0x3a, 0x55,
|
|
0x00, 0xba, 0x28, 0x06, 0xcd, 0xe4, 0xf1, 0xcd,
|
|
0x37, 0xf2, 0xcd, 0xf1, 0xf2, 0x3e, 0xfe, 0x32,
|
|
0x46, 0x00, 0xc3, 0x7c, 0xf3, 0xcd, 0x9c, 0xf2,
|
|
0x3e, 0xa8, 0xcd, 0x90, 0xf2, 0x2a, 0x40, 0x00,
|
|
0x32, 0x4c, 0x00, 0xf3, 0xd3, 0x64, 0x18, 0x00,
|
|
0x18, 0x00, 0xed, 0xb3, 0xfb, 0xcd, 0x42, 0xf3,
|
|
0xdb, 0x64, 0x57, 0x3a, 0x46, 0x00, 0xa2, 0xc8,
|
|
0x7a, 0x32, 0x47, 0x00, 0xcd, 0x59, 0xf2, 0xf6,
|
|
0x01, 0xed, 0x7b, 0x4d, 0x00, 0xcd, 0xf4, 0xf7,
|
|
0xc9, 0xcd, 0x2f, 0xf2, 0xdd, 0x7e, 0x01, 0x4f,
|
|
0x3a, 0x44, 0x00, 0xb9, 0x38, 0x04, 0x3e, 0x0f,
|
|
0x18, 0xdf, 0x4f, 0xdb, 0x65, 0xb9, 0xc8, 0xdd,
|
|
0x7e, 0x08, 0x32, 0x4c, 0x00, 0x06, 0xd2, 0x10,
|
|
0xfe, 0xcd, 0x42, 0xf3, 0x3a, 0x44, 0x00, 0xd3,
|
|
0x67, 0x3e, 0x80, 0x32, 0x46, 0x00, 0x3a, 0x4c,
|
|
0x00, 0xd3, 0x64, 0x06, 0x0a, 0x10, 0xfe, 0xcd,
|
|
0xd5, 0xf2, 0xcd, 0x59, 0xf2, 0x3a, 0x4c, 0x00,
|
|
0xdd, 0xbe, 0x06, 0xc8, 0xdb, 0x64, 0xe6, 0x10,
|
|
0x20, 0x04, 0xdb, 0x65, 0xb9, 0xc8, 0x3e, 0x20,
|
|
0x18, 0x9f, 0x1e, 0x00, 0xc5, 0x0e, 0x02, 0xdb,
|
|
0x64, 0xe6, 0x01, 0x28, 0x20, 0x10, 0xf8, 0x1d,
|
|
0x20, 0xf5, 0x0d, 0x20, 0xf2, 0xc1, 0xdb, 0x63,
|
|
0xf6, 0x80, 0xd3, 0x60, 0x10, 0xfe, 0xdb, 0x60,
|
|
0xcd, 0xb7, 0xf3, 0xdd, 0x7e, 0x06, 0xcd, 0x0a,
|
|
0xf3, 0x3e, 0xfe, 0x18, 0xd3, 0xc1, 0xdb, 0x63,
|
|
0xf6, 0x80, 0xd3, 0x63, 0xc9, 0xdb, 0x63, 0xe6,
|
|
0x7f, 0xd3, 0x63, 0xc9, 0x06, 0x00, 0xdd, 0x7e,
|
|
0x00, 0x3c, 0x4f, 0x3a, 0x43, 0x00, 0xb9, 0x38,
|
|
0x04, 0x06, 0x10, 0x0d, 0x91, 0xf5, 0xcd, 0xa1,
|
|
0xf3, 0xf1, 0xd3, 0x66, 0x01, 0x67, 0x80, 0x3a,
|
|
0x42, 0x00, 0x07, 0x30, 0xd8, 0x06, 0x00, 0x18,
|
|
0xd4, 0xdb, 0x63, 0x2f, 0x5f, 0xe6, 0x10, 0xb8,
|
|
0xc8, 0x7b, 0xe6, 0x6f, 0xb0, 0x2f, 0xd3, 0x63,
|
|
0x06, 0xd2, 0x10, 0xfe, 0xc3, 0x37, 0xf2, 0x3e,
|
|
0xd0, 0xd3, 0x64, 0x3e, 0x0a, 0x3d, 0x20, 0xfd,
|
|
0xdb, 0x64, 0xc9, 0xcd, 0xf4, 0xf7, 0xcd, 0x8d,
|
|
0xf1, 0xc0, 0xcd, 0xdd, 0xf3, 0x20, 0xf7, 0xc9,
|
|
0xcd, 0xf4, 0xf7, 0xcd, 0xa9, 0xf1, 0xc0, 0xcd,
|
|
0xdd, 0xf3, 0x20, 0xf7, 0xc9, 0x2a, 0x40, 0x00,
|
|
0x11, 0x80, 0x00, 0x3a, 0x42, 0x00, 0x07, 0x30,
|
|
0x03, 0x11, 0x00, 0x01, 0x19, 0x22, 0x40, 0x00,
|
|
0x21, 0x45, 0x00, 0x35, 0xc8, 0x2b, 0x2b, 0x34,
|
|
0x3a, 0x49, 0x00, 0xb7, 0xdd, 0xe5, 0xdd, 0x2a,
|
|
0x53, 0x00, 0xdd, 0x7e, 0x00, 0xdd, 0xe1, 0xf2,
|
|
0x0b, 0xf4, 0x07, 0x3c, 0xbe, 0xc0, 0x36, 0x01,
|
|
0x23, 0x34, 0xb7, 0xc9, 0xcd, 0xf4, 0xf7, 0xed,
|
|
0x73, 0x51, 0x00, 0xfd, 0xe5, 0xdd, 0xe5, 0xe5,
|
|
0x21, 0x00, 0x08, 0x22, 0x40, 0x00, 0xed, 0x73,
|
|
0x4d, 0x00, 0xe1, 0xcd, 0xe4, 0xf1, 0xcc, 0xd8,
|
|
0xf1, 0x20, 0x30, 0xcd, 0x6a, 0xf4, 0xcd, 0xd9,
|
|
0xf4, 0xaf, 0xcd, 0x0d, 0xf5, 0xc5, 0xcd, 0x61,
|
|
0xf5, 0xcd, 0xaa, 0xf5, 0xc1, 0x20, 0x05, 0xdd,
|
|
0xbe, 0x01, 0x20, 0xee, 0x3e, 0x4c, 0x32, 0x44,
|
|
0x00, 0xdb, 0x63, 0xcb, 0xaf, 0xd3, 0x63, 0x11,
|
|
0x55, 0x00, 0x1a, 0xcb, 0xef, 0x12, 0xdd, 0xe1,
|
|
0xfd, 0xe1, 0xc9, 0xdd, 0xe1, 0xed, 0x7b, 0x51,
|
|
0x00, 0xc9, 0x2a, 0x40, 0x00, 0xdd, 0x7e, 0x04,
|
|
0x0f, 0x3e, 0x4e, 0xd2, 0x78, 0xf4, 0x3e, 0xff,
|
|
0x5f, 0xdd, 0x46, 0x02, 0xcd, 0xd4, 0xf4, 0xdd,
|
|
0x46, 0x05, 0xcd, 0xd4, 0xf4, 0xaf, 0xdd, 0x46,
|
|
0x03, 0xcd, 0xd4, 0xf4, 0xcd, 0xcd, 0xf4, 0x3e,
|
|
0xfe, 0x77, 0x23, 0xe5, 0xd9, 0xd1, 0xd9, 0xaf,
|
|
0x06, 0x04, 0xcd, 0xd4, 0xf4, 0x3e, 0xf7, 0x77,
|
|
0x23, 0xdd, 0x46, 0x04, 0x78, 0xcb, 0x3f, 0x3c,
|
|
0x4f, 0x7b, 0xcd, 0xd4, 0xf4, 0x41, 0xaf, 0xcd,
|
|
0xd4, 0xf4, 0xcd, 0xcd, 0xf4, 0x3e, 0xfb, 0x77,
|
|
0x23, 0x06, 0x80, 0x3a, 0x42, 0x00, 0x07, 0x30,
|
|
0x02, 0x06, 0x00, 0x3e, 0xe5, 0xcd, 0xd4, 0xf4,
|
|
0x3e, 0xf7, 0x77, 0x23, 0xc9, 0x7b, 0xb7, 0xf8,
|
|
0x3e, 0xf5, 0x06, 0x03, 0x77, 0x23, 0x10, 0xfc,
|
|
0xc9, 0xd9, 0xdd, 0x46, 0x00, 0x05, 0xd9, 0xed,
|
|
0x5b, 0x40, 0x00, 0xe5, 0xb7, 0xdd, 0x4e, 0x02,
|
|
0x06, 0x00, 0xeb, 0x09, 0xeb, 0xed, 0x52, 0xe5,
|
|
0xc1, 0xe1, 0xc5, 0xeb, 0xd9, 0xd9, 0xed, 0xb0,
|
|
0xc1, 0xc5, 0xd9, 0x10, 0xf8, 0xd9, 0xc1, 0xeb,
|
|
0x3a, 0x42, 0x00, 0xcb, 0x67, 0x3e, 0x80, 0x20,
|
|
0x01, 0xaf, 0x6f, 0x65, 0xc9, 0xe5, 0xc5, 0xd9,
|
|
0xc1, 0xe1, 0xd5, 0xfd, 0xe1, 0xd5, 0x08, 0x16,
|
|
0x01, 0xdd, 0x7e, 0x00, 0xfe, 0x1a, 0x3e, 0x01,
|
|
0x28, 0x08, 0xdd, 0x7e, 0x00, 0xcb, 0x3f, 0x3c,
|
|
0x30, 0x26, 0x08, 0xfd, 0x77, 0x00, 0xb5, 0xf2,
|
|
0x37, 0xf5, 0xfd, 0x74, 0x01, 0xcb, 0xbf, 0x08,
|
|
0xfd, 0x77, 0x02, 0xf5, 0x3a, 0x42, 0x00, 0x07,
|
|
0x30, 0x05, 0x3e, 0x01, 0xfd, 0x77, 0x03, 0xf1,
|
|
0xdd, 0xbe, 0x00, 0x28, 0x10, 0xfd, 0x09, 0x3c,
|
|
0x5f, 0x3e, 0x1a, 0xdd, 0xbe, 0x00, 0x7b, 0x28,
|
|
0xd1, 0x7a, 0x53, 0x18, 0xcd, 0x08, 0xd1, 0xd9,
|
|
0xc9, 0xd5, 0xc5, 0xd9, 0x08, 0xc1, 0xd5, 0x5f,
|
|
0x51, 0xdd, 0x46, 0x02, 0x0e, 0x67, 0x2a, 0x40,
|
|
0x00, 0x3e, 0x80, 0x32, 0x46, 0x00, 0xcd, 0x75,
|
|
0xf3, 0x3a, 0x42, 0x00, 0x07, 0x3e, 0x00, 0x30,
|
|
0x02, 0x3e, 0x01, 0x32, 0x50, 0x00, 0x3e, 0xf4,
|
|
0x32, 0x4c, 0x00, 0xf3, 0xd3, 0x64, 0x3a, 0x50,
|
|
0x00, 0xed, 0xb3, 0x42, 0xed, 0xb3, 0xb7, 0x28,
|
|
0x02, 0xed, 0xb3, 0x42, 0x1d, 0x20, 0xf5, 0xd1,
|
|
0xe1, 0x7e, 0xed, 0x79, 0x10, 0xfc, 0xfb, 0xd9,
|
|
0x08, 0xc9, 0x08, 0x3e, 0x2f, 0x10, 0xfe, 0x3d,
|
|
0x20, 0xfb, 0xdb, 0x63, 0xf6, 0x80, 0xcb, 0x7d,
|
|
0x28, 0x10, 0xcb, 0x44, 0xcb, 0x84, 0x20, 0x0a,
|
|
0x24, 0xcb, 0xa7, 0xd3, 0x63, 0x10, 0xfe, 0x08,
|
|
0xbf, 0xc9, 0xcb, 0xe7, 0xd3, 0x63, 0x08, 0x3c,
|
|
0xdd, 0xbe, 0x01, 0xc8, 0x32, 0x44, 0x00, 0xe5,
|
|
0xed, 0x73, 0x4d, 0x00, 0xe1, 0x10, 0xfe, 0xd9,
|
|
0xeb, 0xdd, 0x7e, 0x07, 0xcd, 0x0a, 0xf3, 0xeb,
|
|
0xd9, 0xdb, 0x65, 0x47, 0x3a, 0x44, 0x00, 0xb8,
|
|
0x06, 0x00, 0xc9, 0x05, 0x58, 0xff, 0xff, 0x05,
|
|
0x26, 0x16, 0x71, 0x00, 0x79, 0xff, 0xff, 0x05,
|
|
0x31, 0x80, 0x00, 0x21, 0x5b, 0xf6, 0xcd, 0x38,
|
|
0xf6, 0xcd, 0x41, 0xf6, 0x20, 0x20, 0x7d, 0x32,
|
|
0x42, 0x00, 0x7c, 0x32, 0x39, 0x00, 0xcd, 0x18,
|
|
0xf0, 0xdd, 0x2a, 0x53, 0x00, 0x3a, 0x39, 0x00,
|
|
0xcd, 0x7c, 0xf6, 0xcd, 0x18, 0xf0, 0x21, 0x6e,
|
|
0xf6, 0xcd, 0x38, 0xf6, 0x18, 0xd2, 0x0e, 0x3f,
|
|
0xcd, 0x0c, 0xf0, 0xcd, 0xc6, 0xf6, 0x18, 0xc8,
|
|
0xcd, 0x53, 0xf6, 0xc2, 0x41, 0xe7, 0xc3, 0x07,
|
|
0xe7, 0xcd, 0x53, 0xf6, 0xc2, 0x9a, 0xe7, 0xc3,
|
|
0x60, 0xe7, 0xcd, 0x53, 0xf6, 0xc2, 0x4d, 0xe7,
|
|
0xc3, 0x13, 0xe7, 0x47, 0x3a, 0x28, 0xe0, 0xfe,
|
|
0x01, 0x78, 0xc9, 0x54, 0x45, 0x53, 0x54, 0x23,
|
|
0x44, 0x52, 0x56, 0x23, 0x20, 0x28, 0x54, 0x54,
|
|
0x44, 0x44, 0x29, 0x3a, 0x20, 0x03, 0x0a, 0x0d,
|
|
0x54, 0x41, 0x53, 0x4b, 0x20, 0x44, 0x4f, 0x4e,
|
|
0x45, 0x0d, 0x0a, 0x03, 0xfe, 0x00, 0xca, 0xd1,
|
|
0xf7, 0xfe, 0x05, 0x28, 0x19, 0x38, 0x60, 0xfe,
|
|
0xff, 0xc0, 0x21, 0x94, 0xf6, 0xcd, 0x38, 0xf6,
|
|
0xcd, 0x41, 0xf6, 0xe9, 0x41, 0x44, 0x44, 0x52,
|
|
0x45, 0x53, 0x53, 0x3a, 0x20, 0x03, 0xcd, 0x33,
|
|
0xf0, 0xc9, 0x21, 0xcf, 0xf6, 0xcd, 0x38, 0xf6,
|
|
0x3a, 0x4c, 0x00, 0xcd, 0xec, 0xf7, 0x3a, 0x47,
|
|
0x00, 0xcd, 0xec, 0xf7, 0x3a, 0x42, 0x00, 0xcd,
|
|
0xec, 0xf7, 0x3a, 0x44, 0x00, 0xcd, 0xec, 0xf7,
|
|
0x3a, 0x43, 0x00, 0xcd, 0x4a, 0xf6, 0xcd, 0x53,
|
|
0xf6, 0xc2, 0x2f, 0xe7, 0xc3, 0xf5, 0xe6, 0x43,
|
|
0x4d, 0x44, 0x20, 0x53, 0x54, 0x41, 0x54, 0x20,
|
|
0x44, 0x52, 0x56, 0x20, 0x54, 0x52, 0x4b, 0x20,
|
|
0x53, 0x43, 0x54, 0x52, 0x3e, 0x20, 0x03, 0xaf,
|
|
0x32, 0x44, 0x00, 0x3c, 0x32, 0x43, 0x00, 0x18,
|
|
0x54, 0x21, 0x00, 0x08, 0x22, 0x40, 0x00, 0xcd,
|
|
0x2a, 0xf0, 0xc4, 0xa2, 0xf6, 0x21, 0x00, 0x09,
|
|
0x22, 0x40, 0x00, 0xcd, 0x27, 0xf0, 0xc4, 0xa2,
|
|
0xf6, 0x3a, 0x39, 0x00, 0xfe, 0x02, 0x28, 0x0f,
|
|
0xf5, 0xcd, 0x59, 0xf7, 0xf1, 0xfe, 0x03, 0xca,
|
|
0xae, 0xf7, 0xfe, 0x04, 0xca, 0x9e, 0xf7, 0x21,
|
|
0x43, 0x00, 0x34, 0xdd, 0x7e, 0x00, 0xe5, 0x21,
|
|
0x42, 0x00, 0xcb, 0x66, 0xe1, 0x28, 0x01, 0x07,
|
|
0x3c, 0xbe, 0x20, 0x11, 0x36, 0x01, 0x23, 0x34,
|
|
0xdd, 0x7e, 0x01, 0xbe, 0x20, 0x07, 0x36, 0x00,
|
|
0x0e, 0x50, 0xcd, 0x0c, 0xf0, 0xcd, 0x06, 0xf0,
|
|
0x28, 0x06, 0xcd, 0x09, 0xf0, 0xfe, 0x2e, 0xc8,
|
|
0x3a, 0x39, 0x00, 0xfe, 0x02, 0x28, 0xa6, 0x18,
|
|
0x98, 0x21, 0x00, 0x09, 0xeb, 0x21, 0x00, 0x08,
|
|
0x3a, 0x42, 0x00, 0x07, 0x06, 0x80, 0x30, 0x02,
|
|
0x06, 0x00, 0x1a, 0xbe, 0x3e, 0xff, 0x32, 0x47,
|
|
0x00, 0xc2, 0xa2, 0xf6, 0x23, 0x13, 0x10, 0xf2,
|
|
0x21, 0x38, 0x00, 0x11, 0x00, 0x08, 0x06, 0x40,
|
|
0x3a, 0x42, 0x00, 0x07, 0x38, 0x02, 0xcb, 0x20,
|
|
0x7e, 0x0f, 0x38, 0x01, 0x13, 0xed, 0x5f, 0x12,
|
|
0x13, 0x13, 0x10, 0xf9, 0x7e, 0x0f, 0x38, 0x03,
|
|
0x3c, 0x77, 0xc9, 0xaf, 0x77, 0xc9, 0xe5, 0x21,
|
|
0x42, 0x00, 0x7e, 0xe6, 0xf0, 0x77, 0xed, 0x5f,
|
|
0x00, 0xe6, 0x01, 0xb6, 0x77, 0xe1, 0xdd, 0x7e,
|
|
0x00, 0x3c, 0x47, 0xed, 0x5f, 0xe6, 0x1f, 0xb7,
|
|
0x28, 0xf4, 0x32, 0x43, 0x00, 0xb8, 0x30, 0xee,
|
|
0xdd, 0x7e, 0x01, 0x47, 0xed, 0x5f, 0xe6, 0x7f,
|
|
0x32, 0x44, 0x00, 0xb8, 0x30, 0xf2, 0xc3, 0x45,
|
|
0xf7, 0xcd, 0x18, 0xf0, 0xdd, 0x7e, 0x01, 0x3d,
|
|
0xd3, 0x67, 0xdd, 0x7e, 0x07, 0xd3, 0x64, 0xcd,
|
|
0x06, 0xf0, 0x28, 0xed, 0xcd, 0x09, 0xf0, 0xfe,
|
|
0x2e, 0xc8, 0x18, 0xe5, 0xcd, 0x4a, 0xf6, 0x0e,
|
|
0x20, 0xc3, 0x0c, 0xf0, 0x3e, 0xff, 0x32, 0x55,
|
|
0x00, 0xc9, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
|
|
};
|
|
|
|
/* Provide RAM if ROMs are disabled */
|
|
static uint8 sbc200_mon_ram[SBC200_MON_SIZE] = {0};
|
|
static uint8 sbc200_ddb_ram[SBC200_DDB_SIZE] = {0};
|
|
|
|
static int32 poc = TRUE; /* Power On Clear */
|
|
|
|
/* Debug flags */
|
|
#define STATUS_MSG (1 << 0)
|
|
#define IRQ_MSG (1 << 1)
|
|
#define VERBOSE_MSG (1 << 3)
|
|
|
|
typedef struct {
|
|
t_bool conn; /* Connected Status */
|
|
TMLN *tmln; /* TMLN pointer */
|
|
TMXR *tmxr; /* TMXR pointer */
|
|
t_bool mif; /* Mode Instruction */
|
|
int32 mode; /* Mode */
|
|
int32 baud; /* Baud rate */
|
|
int32 dtr; /* DTR Status */
|
|
int32 rts; /* RTS Status */
|
|
int32 cts; /* CTS Status */
|
|
int32 rxb; /* Receive Buffer */
|
|
int32 txb; /* Transmit Buffer */
|
|
t_bool txp; /* Transmit Pending */
|
|
int32 stb; /* Status Buffer */
|
|
int32 ctb; /* Control Buffer */
|
|
uint8 rxintenable; /* Interrupt Enable */
|
|
uint8 txintenable; /* Interrupt Enable */
|
|
uint8 rxintvector; /* Interrupt Vector */
|
|
uint8 txintvector; /* Interrupt Vector */
|
|
uint8 rxdatabus; /* Data Bus Value */
|
|
uint8 txdatabus; /* Data Bus Value */
|
|
} SBC200_INFO;
|
|
|
|
static const char* sbc200_description(DEVICE *dptr);
|
|
static t_stat sbc200_svc(UNIT *uptr);
|
|
static t_stat sbc200_reset(DEVICE *dptr);
|
|
static t_stat sbc200_attach(UNIT *uptr, const char *cptr);
|
|
static t_stat sbc200_detach(UNIT *uptr);
|
|
static t_stat sbc200_set_console(UNIT *uptr, int32 value, const char *cptr, void *desc);
|
|
static t_stat sbc200_set_baud(UNIT *uptr, int32 value, const char *cptr, void *desc);
|
|
static t_stat sbc200_show_baud(FILE *st, UNIT *uptr, int32 value, const void *desc);
|
|
static t_stat sbc200_config_line(UNIT *uptr);
|
|
static t_stat sbc200_config_dtr(DEVICE *dptr, char rts);
|
|
static t_stat sbc200_config_rts(DEVICE *dptr, char rts);
|
|
static int32 sbc200_io(int32 addr, int32 io, int32 data);
|
|
static int32 sbc200_stat(DEVICE *dptr, int32 io, int32 data);
|
|
static int32 sbc200_data(DEVICE *dptr, int32 io, int32 data);
|
|
static int32 sbc200_rom(DEVICE *dptr, int32 io, int32 data);
|
|
static void sbc200_int(UNIT *uptr, int32 vector, int32 databus);
|
|
static int32 sbc200_mon(int32 Addr, int32 rw, int32 Data);
|
|
static int32 sbc200_ddb(int32 Addr, int32 rw, int32 Data);
|
|
static t_stat sbc200_show_help(FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, const char *cptr);
|
|
|
|
extern uint32 vectorInterrupt; /* Vector Interrupt bits */
|
|
extern uint8 dataBus[MAX_INT_VECTORS]; /* Data bus value */
|
|
|
|
/* Debug Flags */
|
|
static DEBTAB sbc200_dt[] = {
|
|
{ "STATUS", STATUS_MSG, "Status messages" },
|
|
{ "IRQ", IRQ_MSG, "Interrupt messages" },
|
|
{ "VERBOSE", VERBOSE_MSG, "Verbose messages" },
|
|
{ NULL, 0 }
|
|
};
|
|
|
|
/* Terminal multiplexer library descriptors */
|
|
|
|
static TMLN sbc200_tmln[] = { /* line descriptors */
|
|
{ 0 }
|
|
};
|
|
|
|
static TMXR sbc200_tmxr = { /* multiplexer descriptor */
|
|
1, /* number of terminal lines */
|
|
0, /* listening port (reserved) */
|
|
0, /* master socket (reserved) */
|
|
sbc200_tmln, /* line descriptor array */
|
|
NULL, /* line connection order */
|
|
NULL /* multiplexer device (derived internally) */
|
|
};
|
|
|
|
#define UNIT_V_SBC200_CONSOLE (UNIT_V_UF + 0) /* Port checks console for input */
|
|
#define UNIT_SBC200_CONSOLE (1 << UNIT_V_SBC200_CONSOLE)
|
|
#define UNIT_V_SBC200_MONITOR (UNIT_V_UF + 1) /* Monitor ROM */
|
|
#define UNIT_SBC200_MONITOR (1 << UNIT_V_SBC200_MONITOR)
|
|
#define UNIT_V_SBC200_DDBIOS (UNIT_V_UF + 2) /* DDBIOS ROM */
|
|
#define UNIT_SBC200_DDBIOS (1 << UNIT_V_SBC200_DDBIOS)
|
|
|
|
static MTAB sbc200_mod[] = {
|
|
{ UNIT_SBC200_MONITOR, UNIT_SBC200_MONITOR, "MONITOR", "MONITOR", NULL, NULL, NULL,
|
|
"Enable ROM monitor at E000" },
|
|
{ UNIT_SBC200_MONITOR, 0, "NOMONITOR", "NOMONITOR", NULL, NULL, NULL,
|
|
"Disable ROM monitor at E000" },
|
|
{ UNIT_SBC200_DDBIOS, UNIT_SBC200_DDBIOS, "DDBIOS", "DDBIOS", NULL, NULL, NULL,
|
|
"Enable ROM DDBIOS at F000" },
|
|
{ UNIT_SBC200_DDBIOS, 0, "NODDBIOS", "NODDBIOS", NULL, NULL, NULL,
|
|
"Disable ROM DDBIOS at F000" },
|
|
|
|
{ MTAB_XTD | MTAB_VUN, UNIT_SBC200_CONSOLE, NULL, "CONSOLE", &sbc200_set_console, NULL, NULL, "Set as CONSOLE" },
|
|
{ MTAB_XTD | MTAB_VUN, 0, NULL, "NOCONSOLE", &sbc200_set_console, NULL, NULL, "Remove as CONSOLE" },
|
|
|
|
{ MTAB_XTD|MTAB_VDV|MTAB_VALR, 0, "BAUD", "BAUD", &sbc200_set_baud, &sbc200_show_baud,
|
|
NULL, "Set baud rate (default=9600)" },
|
|
{ 0 }
|
|
};
|
|
|
|
static SBC200_INFO sbc200_info = { 0, sbc200_tmln, &sbc200_tmxr, SBC200_BAUD, 1 };
|
|
|
|
static UNIT sbc200_unit[] = {
|
|
{ UDATA (&sbc200_svc, UNIT_ATTABLE | UNIT_DISABLE |
|
|
UNIT_SBC200_CONSOLE | UNIT_SBC200_MONITOR | UNIT_SBC200_DDBIOS, 0), SBC200_WAIT },
|
|
};
|
|
|
|
static REG sbc200_reg[] = {
|
|
{ HRDATAD (SBCSTA, sbc200_info.stb, 8, "Status register"), },
|
|
{ HRDATAD (SBCCTL, sbc200_info.ctb, 8, "Control register"), },
|
|
{ HRDATAD (SBCRXD, sbc200_info.rxb, 8, "RX data buffer"), },
|
|
{ HRDATAD (SBCTXD, sbc200_info.txb, 8, "TX data buffer"), },
|
|
{ FLDATAD (SBCTXP, sbc200_info.txp, 0, "TX data pending"), },
|
|
{ FLDATAD (SBCCON, sbc200_info.conn, 0, "Connection status"), },
|
|
{ FLDATAD (SBCRTS, sbc200_info.rts, 0, "RTS status (active low)"), },
|
|
{ FLDATAD (SBCDTR, sbc200_info.dtr, 0, "DTR status (active low)"), },
|
|
{ FLDATAD (SBCRDRF, sbc200_info.stb, 0, "RDRF status"), },
|
|
{ FLDATAD (SBCTRDY, sbc200_info.stb, 1, "TRDY status"), },
|
|
{ FLDATAD (SBCTDRE, sbc200_info.stb, 2, "TDRE status"), },
|
|
{ FLDATAD (SBCOVRN, sbc200_info.stb, 4, "OVRN status"), },
|
|
{ FLDATAD (SBCCTS, sbc200_info.cts, 0, "CTS status (active low)"), },
|
|
{ FLDATAD (SBCDSR, sbc200_info.stb, 7, "DSR status (active low)"), },
|
|
{ DRDATAD (SBCWAIT, sbc200_unit[0].wait, 32, "Wait cycles"), },
|
|
{ FLDATAD (SBCRXINTEN, sbc200_info.rxintenable, 1, "Global vectored interrupt enable"), },
|
|
{ FLDATAD (SBCTXINTEN, sbc200_info.txintenable, 1, "Global vectored interrupt enable"), },
|
|
{ DRDATAD (SBCRXVEC, sbc200_info.rxintvector, 8, "RX interrupt vector"), },
|
|
{ DRDATAD (SBCTXVEC, sbc200_info.txintvector, 8, "TX interrupt vector"), },
|
|
{ HRDATAD (SBCRXDBVAL, sbc200_info.rxdatabus, 8, "RX data bus value"), },
|
|
{ HRDATAD (SBCTXDBVAL, sbc200_info.txdatabus, 8, "TX data bus value"), },
|
|
{ NULL }
|
|
};
|
|
|
|
DEVICE sbc200_dev = {
|
|
SBC200_SNAME, /* name */
|
|
sbc200_unit, /* unit */
|
|
sbc200_reg, /* registers */
|
|
sbc200_mod, /* modifiers */
|
|
1, /* # units */
|
|
ADDRRADIX, /* address radix */
|
|
ADDRWIDTH, /* address width */
|
|
1, /* address increment */
|
|
DATARADIX, /* data radix */
|
|
DATAWIDTH, /* data width */
|
|
NULL, /* examine routine */
|
|
NULL, /* deposit routine */
|
|
&sbc200_reset, /* reset routine */
|
|
NULL, /* boot routine */
|
|
&sbc200_attach, /* attach routine */
|
|
&sbc200_detach, /* detach routine */
|
|
&sbc200_iores, /* context */
|
|
(DEV_DISABLE | DEV_DIS | DEV_DEBUG | DEV_MUX), /* flags */
|
|
0, /* debug control */
|
|
sbc200_dt, /* debug flags */
|
|
NULL, /* mem size routine */
|
|
NULL, /* logical name */
|
|
&sbc200_show_help, /* help */
|
|
NULL, /* attach help */
|
|
NULL, /* context for help */
|
|
&sbc200_description /* description */
|
|
};
|
|
|
|
static const char* sbc200_description(DEVICE *dptr)
|
|
{
|
|
return SBC200_NAME;
|
|
}
|
|
|
|
static t_stat sbc200_reset(DEVICE *dptr)
|
|
{
|
|
sim_debug(STATUS_MSG, dptr, "reset adapter.\n");
|
|
|
|
/* Connect/Disconnect I/O Ports at base address */
|
|
if (dptr->flags & DEV_DIS) {
|
|
s100_bus_remio(sbc200_iores.io_base, sbc200_iores.io_size, &sbc200_io);
|
|
s100_bus_remmem(sbc200_monres.mem_base, sbc200_monres.mem_size, &sbc200_mon);
|
|
s100_bus_remmem(sbc200_ddbres.mem_base, sbc200_ddbres.mem_size, &sbc200_ddb);
|
|
|
|
s100_bus_noconsole(&dptr->units[0]);
|
|
|
|
poc = TRUE;
|
|
|
|
return SCPE_OK;
|
|
}
|
|
|
|
if (poc == TRUE) {
|
|
s100_bus_addio(sbc200_iores.io_base, sbc200_iores.io_size, &sbc200_io, dptr->name);
|
|
|
|
cpu_set_chiptype(CHIP_TYPE_Z80); /* Set to Z80 */
|
|
|
|
poc = FALSE;
|
|
}
|
|
|
|
/* Enable ROMs on Reset */
|
|
s100_bus_addmem(sbc200_monres.mem_base, sbc200_monres.mem_size, &sbc200_mon, dptr->name);
|
|
s100_bus_addmem(sbc200_ddbres.mem_base, sbc200_ddbres.mem_size, &sbc200_ddb, dptr->name);
|
|
|
|
/* Set as CONSOLE unit */
|
|
if (dptr->units[0].flags & UNIT_SBC200_CONSOLE) {
|
|
s100_bus_console(&dptr->units[0]);
|
|
}
|
|
|
|
/* Set DEVICE for this UNIT */
|
|
dptr->units[0].dptr = dptr;
|
|
dptr->units[0].wait = SBC200_WAIT;
|
|
|
|
/* Enable TMXR modem control passthrough */
|
|
tmxr_set_modem_control_passthru(sbc200_info.tmxr);
|
|
|
|
/* Reset status registers */
|
|
dptr->units[0].flags |= (UNIT_SBC200_MONITOR | UNIT_SBC200_DDBIOS);
|
|
sbc200_info.mif = TRUE;
|
|
sbc200_info.stb = 0x00;
|
|
sbc200_info.txp = FALSE;
|
|
sbc200_info.cts = 0; /* Force CTS active (low) */
|
|
sbc200_info.rxintenable = FALSE;
|
|
sbc200_info.txintenable = FALSE;
|
|
if (dptr->units[0].flags & UNIT_ATT) {
|
|
sbc200_config_dtr(dptr, 1); /* disable DTR */
|
|
sbc200_config_rts(dptr, 1); /* disable RTS */
|
|
}
|
|
|
|
/* Activate Service Routine */
|
|
sim_activate(&dptr->units[0], dptr->units[0].wait);
|
|
|
|
return SCPE_OK;
|
|
}
|
|
|
|
static t_stat sbc200_svc(UNIT *uptr)
|
|
{
|
|
int32 c,s,stb,cts;
|
|
t_stat r = SCPE_OK;
|
|
|
|
/* Check for new incoming connection */
|
|
if (uptr->flags & UNIT_ATT) {
|
|
if (tmxr_poll_conn(sbc200_info.tmxr) >= 0) { /* poll connection */
|
|
|
|
sbc200_info.conn = TRUE; /* set connected */
|
|
|
|
sim_debug(STATUS_MSG, uptr->dptr, "new connection.\n");
|
|
}
|
|
}
|
|
|
|
/* Update incoming modem status bits */
|
|
if (uptr->flags & UNIT_ATT) {
|
|
tmxr_set_get_modem_bits(sbc200_info.tmln, 0, 0, &s);
|
|
cts = sbc200_info.cts;
|
|
stb = sbc200_info.stb;
|
|
|
|
sbc200_info.stb &= ~SBC200_DSR;
|
|
sbc200_info.stb |= (s & TMXR_MDM_DSR) ? 0 : SBC200_DSR; /* Active Low */
|
|
if ((stb ^ sbc200_info.stb) & SBC200_DSR) {
|
|
sim_debug(STATUS_MSG, uptr->dptr, "DSR state changed to %s.\n", (sbc200_info.stb & SBC200_DSR) ? "LOW" : "HIGH");
|
|
}
|
|
sbc200_info.cts = 0;
|
|
sbc200_info.cts = (s & TMXR_MDM_CTS) ? 0 : 1; /* Active Low */
|
|
if (cts != sbc200_info.cts) {
|
|
sim_debug(STATUS_MSG, uptr->dptr, "CTS state changed to %s.\n", (sbc200_info.cts) ? "LOW" : "HIGH");
|
|
}
|
|
} else {
|
|
/*
|
|
* The SBC-200 connects RXD to DSR to determine
|
|
* the baud rate. Simulate by toggling DSR.
|
|
*/
|
|
sbc200_info.stb ^= SBC200_DSR;
|
|
}
|
|
|
|
/* TX data */
|
|
if (sbc200_info.txp) {
|
|
if (uptr->flags & UNIT_ATT) {
|
|
if (!(sbc200_info.cts)) { /* Active low */
|
|
r = tmxr_putc_ln(sbc200_info.tmln, sbc200_info.txb);
|
|
sbc200_info.txp = FALSE; /* Reset TX Pending */
|
|
} else {
|
|
r = SCPE_STALL;
|
|
}
|
|
} else {
|
|
r = sim_putchar(sbc200_info.txb);
|
|
sbc200_info.txp = FALSE; /* Reset TX Pending */
|
|
}
|
|
|
|
if (r == SCPE_LOST) {
|
|
sbc200_info.conn = FALSE; /* Connection was lost */
|
|
sim_debug(STATUS_MSG, uptr->dptr, "lost connection.\n");
|
|
}
|
|
|
|
/* If TX buffer now empty, send interrupt */
|
|
if (!sbc200_info.txp && sbc200_info.txintenable) {
|
|
sim_debug(IRQ_MSG, uptr->dptr, "%s: TxRDY Vector=%d\n", sim_uname(uptr), sbc200_info.txintvector);
|
|
sbc200_int(uptr, sbc200_info.txintvector, sbc200_info.txdatabus);
|
|
}
|
|
|
|
}
|
|
|
|
/* Update TDRE if not set and no character pending */
|
|
if (!sbc200_info.txp && !(sbc200_info.stb & SBC200_TDRE)) {
|
|
if (uptr->flags & UNIT_ATT) {
|
|
tmxr_poll_tx(sbc200_info.tmxr);
|
|
sbc200_info.stb |= (tmxr_txdone_ln(sbc200_info.tmln) && sbc200_info.conn) ? SBC200_TRDY | SBC200_TDRE : 0;
|
|
} else {
|
|
sbc200_info.stb |= (SBC200_TRDY | SBC200_TDRE);
|
|
}
|
|
}
|
|
|
|
/* Check for Data if RX buffer empty */
|
|
if (!(sbc200_info.stb & SBC200_RDRF)) {
|
|
if (uptr->flags & UNIT_ATT) {
|
|
tmxr_poll_rx(sbc200_info.tmxr);
|
|
|
|
c = tmxr_getc_ln(sbc200_info.tmln);
|
|
}
|
|
else {
|
|
c = s100_bus_poll_kbd(uptr);
|
|
}
|
|
|
|
if (c & (TMXR_VALID | SCPE_KFLAG)) {
|
|
sbc200_info.rxb = c & 0xff;
|
|
sbc200_info.stb |= SBC200_RDRF;
|
|
sbc200_info.stb &= ~(SBC200_FE | SBC200_OVRN | SBC200_PE);
|
|
sim_debug(IRQ_MSG, uptr->dptr, "%s: RxRDY Vector=%d\n", sim_uname(uptr), sbc200_info.rxintvector);
|
|
if (sbc200_info.rxintenable) {
|
|
sbc200_int(uptr, sbc200_info.rxintvector, sbc200_info.rxdatabus);
|
|
}
|
|
}
|
|
}
|
|
|
|
/* Don't let TMXR clobber our wait time */
|
|
uptr->wait = SBC200_WAIT;
|
|
|
|
sim_activate_abs(uptr, uptr->wait);
|
|
|
|
return r;
|
|
}
|
|
|
|
|
|
/* Attach routine */
|
|
static t_stat sbc200_attach(UNIT *uptr, const char *cptr)
|
|
{
|
|
t_stat r;
|
|
|
|
sim_debug(VERBOSE_MSG, uptr->dptr, "attach (%s).\n", cptr);
|
|
|
|
if ((r = tmxr_attach(sbc200_info.tmxr, uptr, cptr)) == SCPE_OK) {
|
|
|
|
if (sbc200_info.tmln->serport) {
|
|
sbc200_config_dtr(uptr->dptr, sbc200_info.dtr); /* update DTR */
|
|
sbc200_config_rts(uptr->dptr, sbc200_info.rts); /* update RTS */
|
|
}
|
|
|
|
sbc200_info.tmln->rcve = 1;
|
|
}
|
|
|
|
return r;
|
|
}
|
|
|
|
|
|
/* Detach routine */
|
|
static t_stat sbc200_detach(UNIT *uptr)
|
|
{
|
|
if (uptr->dptr == NULL) {
|
|
return SCPE_IERR;
|
|
}
|
|
|
|
sim_debug(VERBOSE_MSG, uptr->dptr, "detach.\n");
|
|
|
|
if (uptr->flags & UNIT_ATT) {
|
|
sim_cancel(uptr);
|
|
|
|
return (tmxr_detach(sbc200_info.tmxr, uptr));
|
|
}
|
|
|
|
return SCPE_UNATT;
|
|
}
|
|
|
|
static t_stat sbc200_set_console(UNIT *uptr, int32 value, const char *cptr, void *desc)
|
|
{
|
|
if (value == UNIT_SBC200_CONSOLE) {
|
|
s100_bus_console(uptr);
|
|
}
|
|
else {
|
|
s100_bus_noconsole(uptr);
|
|
}
|
|
|
|
return SCPE_OK;
|
|
}
|
|
|
|
static t_stat sbc200_set_baud(UNIT *uptr, int32 value, const char *cptr, void *desc)
|
|
{
|
|
int32 baud;
|
|
t_stat r = SCPE_ARG;
|
|
|
|
if (!(uptr->flags & UNIT_ATT)) {
|
|
return SCPE_UNATT;
|
|
}
|
|
|
|
if (cptr != NULL) {
|
|
if (sscanf(cptr, "%d", &baud)) {
|
|
switch (baud) {
|
|
case 110:
|
|
case 150:
|
|
case 300:
|
|
case 1200:
|
|
case 1800:
|
|
case 2400:
|
|
case 4800:
|
|
case 9600:
|
|
case 19200:
|
|
sbc200_info.baud = baud;
|
|
r = sbc200_config_line(uptr);
|
|
|
|
return r;
|
|
|
|
default:
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
|
|
return r;
|
|
}
|
|
|
|
static t_stat sbc200_show_baud(FILE *st, UNIT *uptr, int32 value, const void *desc)
|
|
{
|
|
if (uptr->flags & UNIT_ATT) {
|
|
fprintf(st, "Baud rate: %d", sbc200_info.baud);
|
|
}
|
|
|
|
return SCPE_OK;
|
|
}
|
|
|
|
static t_stat sbc200_config_line(UNIT *uptr)
|
|
{
|
|
char config[20];
|
|
const char *fmt;
|
|
t_stat r = SCPE_IERR;
|
|
|
|
switch (sbc200_info.mode & SBC200_FMTMSK) {
|
|
case SBC200_72E:
|
|
fmt = "7E2";
|
|
break;
|
|
case SBC200_72O:
|
|
fmt = "7O2";
|
|
break;
|
|
case SBC200_71E:
|
|
fmt = "7E1";
|
|
break;
|
|
case SBC200_71O:
|
|
fmt = "7O1";
|
|
break;
|
|
case SBC200_82N:
|
|
fmt = "8N2";
|
|
break;
|
|
case SBC200_81E:
|
|
fmt = "8E1";
|
|
break;
|
|
case SBC200_81O:
|
|
fmt = "8O1";
|
|
break;
|
|
case SBC200_81N:
|
|
default:
|
|
fmt = "8N1";
|
|
break;
|
|
}
|
|
|
|
sprintf(config, "%d-%s", sbc200_info.baud, fmt);
|
|
|
|
r = tmxr_set_config_line(sbc200_info.tmln, config);
|
|
|
|
sim_debug(STATUS_MSG, uptr->dptr, "port configuration set to '%s'.\n", config);
|
|
|
|
return r;
|
|
}
|
|
|
|
/*
|
|
** DTR is active low
|
|
** 0 = DTR active
|
|
** 1 = DTR inactive
|
|
*/
|
|
static t_stat sbc200_config_dtr(DEVICE *dptr, char dtr)
|
|
{
|
|
t_stat r = SCPE_OK;
|
|
int32 s;
|
|
|
|
if (dptr->units[0].flags & UNIT_ATT) {
|
|
/* DTR Control */
|
|
s = TMXR_MDM_DTR;
|
|
|
|
if (!dtr) {
|
|
r = tmxr_set_get_modem_bits(sbc200_info.tmln, s, 0, NULL);
|
|
if (sbc200_info.dtr) {
|
|
sim_debug(STATUS_MSG, dptr, "DTR state changed to HIGH.\n");
|
|
}
|
|
} else {
|
|
r = tmxr_set_get_modem_bits(sbc200_info.tmln, 0, s, NULL);
|
|
if (!sbc200_info.dtr) {
|
|
sim_debug(STATUS_MSG, dptr, "DTR state changed to LOW.\n");
|
|
}
|
|
}
|
|
}
|
|
|
|
sbc200_info.dtr = dtr; /* Active low */
|
|
|
|
return r;
|
|
}
|
|
|
|
/*
|
|
** RTS is active low
|
|
** 0 = RTS active
|
|
** 1 = RTS inactive
|
|
*/
|
|
static t_stat sbc200_config_rts(DEVICE *dptr, char rts)
|
|
{
|
|
t_stat r = SCPE_OK;
|
|
int32 s;
|
|
|
|
if (dptr->units[0].flags & UNIT_ATT) {
|
|
/* RTS Control */
|
|
s = TMXR_MDM_RTS;
|
|
|
|
if (!rts) {
|
|
r = tmxr_set_get_modem_bits(sbc200_info.tmln, s, 0, NULL);
|
|
if (sbc200_info.rts) {
|
|
sim_debug(STATUS_MSG, dptr, "RTS state changed to HIGH.\n");
|
|
}
|
|
} else {
|
|
r = tmxr_set_get_modem_bits(sbc200_info.tmln, 0, s, NULL);
|
|
if (!sbc200_info.rts) {
|
|
sim_debug(STATUS_MSG, dptr, "RTS state changed to LOW.\n");
|
|
}
|
|
}
|
|
}
|
|
|
|
sbc200_info.rts = rts; /* Active low */
|
|
|
|
return r;
|
|
}
|
|
|
|
static int32 sbc200_io(int32 addr, int32 io, int32 data)
|
|
{
|
|
int32 r = 0xff;
|
|
|
|
switch (addr - sbc200_iores.io_base) {
|
|
case 0x04:
|
|
r = sbc200_data(&sbc200_dev, io, data);
|
|
break;
|
|
|
|
case 0x05:
|
|
r = sbc200_stat(&sbc200_dev, io, data);
|
|
break;
|
|
|
|
case 0x07:
|
|
r = sbc200_rom(&sbc200_dev, io, data);
|
|
break;
|
|
|
|
default:
|
|
break;
|
|
|
|
}
|
|
|
|
return(r);
|
|
}
|
|
|
|
static int32 sbc200_stat(DEVICE *dptr, int32 io, int32 data)
|
|
{
|
|
int32 r;
|
|
|
|
if (io == S100_IO_READ) {
|
|
r = sbc200_info.stb;
|
|
} else {
|
|
if (sbc200_info.mif) {
|
|
sbc200_info.mif = FALSE;
|
|
sbc200_info.mode = data & 0xff;
|
|
|
|
/* Set data bits, parity and stop bits format */
|
|
sbc200_config_line(&dptr->units[0]);
|
|
} else { /* Command Mode */
|
|
/* Internal Reset */
|
|
if (data & SBC200_IR) {
|
|
sim_debug(STATUS_MSG, dptr, "8251 internal reset.\n");
|
|
|
|
sbc200_info.ctb = data & 0xff; /* save control byte */
|
|
sbc200_info.stb = SBC200_DSR; /* Reset status register */
|
|
sbc200_info.mif = TRUE;
|
|
sbc200_info.rxb = 0x00;
|
|
sbc200_info.txp = FALSE;
|
|
|
|
sbc200_config_dtr(dptr, 1); /* disable DTR */
|
|
sbc200_config_rts(dptr, 1); /* disable RTS */
|
|
} else {
|
|
sbc200_config_dtr(dptr, (data & SBC200_DTR)); /* enable DTR */
|
|
sbc200_config_rts(dptr, (data & SBC200_RTS)); /* enable RTS */
|
|
}
|
|
}
|
|
|
|
r = 0x00;
|
|
}
|
|
|
|
return(r);
|
|
}
|
|
|
|
static int32 sbc200_data(DEVICE *dptr, int32 io, int32 data)
|
|
{
|
|
int32 r;
|
|
|
|
if (io == S100_IO_READ) {
|
|
r = sbc200_info.rxb;
|
|
sbc200_info.stb &= ~(SBC200_RDRF | SBC200_FE | SBC200_OVRN | SBC200_PE);
|
|
} else {
|
|
sbc200_info.txb = data;
|
|
sbc200_info.stb &= ~(SBC200_TRDY | SBC200_TDRE);
|
|
sbc200_info.txp = TRUE;
|
|
|
|
sbc200_svc(dptr->units); /* Process TX right now */
|
|
|
|
r = 0x00;
|
|
}
|
|
|
|
return r;
|
|
}
|
|
|
|
static int32 sbc200_rom(DEVICE *dptr, int32 io, int32 data)
|
|
{
|
|
sim_debug(VERBOSE_MSG, dptr, "Switch %s ROMs\n", data & 0x02 ? "OUT" : "IN");
|
|
|
|
if (data & 0x02) { /* Disable ROMs */
|
|
s100_bus_remmem(sbc200_monres.mem_base, sbc200_monres.mem_size, &sbc200_mon);
|
|
s100_bus_remmem(sbc200_ddbres.mem_base, sbc200_ddbres.mem_size, &sbc200_ddb);
|
|
}
|
|
else {
|
|
s100_bus_addmem(sbc200_monres.mem_base, sbc200_monres.mem_size, &sbc200_mon, dptr->name);
|
|
s100_bus_addmem(sbc200_ddbres.mem_base, sbc200_ddbres.mem_size, &sbc200_ddb, dptr->name);
|
|
}
|
|
|
|
return data;
|
|
}
|
|
|
|
static void sbc200_int(UNIT *uptr, int32 vector, int32 databus)
|
|
{
|
|
vectorInterrupt |= (1 << vector);
|
|
dataBus[vector] = databus;
|
|
|
|
sim_debug(IRQ_MSG, uptr->dptr, "%s: IRQ Vector=%d dataBus=%02X Status=%02X\n", sim_uname(uptr), vector, databus, sbc200_info.stb);
|
|
}
|
|
|
|
|
|
static int32 sbc200_mon(int32 Addr, int32 rw, int32 Data)
|
|
{
|
|
/* If ROM enabled, return ROM byte */
|
|
if (sbc200_dev.units->flags & UNIT_SBC200_MONITOR) {
|
|
return(sbc200_mon_rom[Addr & SBC200_MON_MASK]);
|
|
} else if (rw == S100_IO_WRITE) {
|
|
sbc200_mon_ram[Addr & SBC200_MON_MASK] = Data;
|
|
}
|
|
|
|
return sbc200_mon_ram[Addr & SBC200_MON_MASK];
|
|
}
|
|
|
|
static int32 sbc200_ddb(int32 Addr, int32 rw, int32 Data)
|
|
{
|
|
/* If ROM has been disabled, unmap and return byte from RAM */
|
|
if (sbc200_dev.units->flags & UNIT_SBC200_DDBIOS) {
|
|
return(sbc200_ddb_rom[Addr & SBC200_DDB_MASK]);
|
|
} else if (rw == S100_IO_WRITE) {
|
|
sbc200_ddb_ram[Addr & SBC200_DDB_MASK] = Data;
|
|
}
|
|
|
|
return sbc200_ddb_ram[Addr & SBC200_DDB_MASK];
|
|
}
|
|
|
|
static t_stat sbc200_show_help(FILE *st, DEVICE *dptr, UNIT *uptr, int32 flag, const char *cptr)
|
|
{
|
|
fprintf (st, "\nSD Systems SBC-200 (%s)\n", dptr->name);
|
|
|
|
fprint_set_help (st, dptr);
|
|
fprint_show_help (st, dptr);
|
|
fprint_reg_help (st, dptr);
|
|
fprintf(st, "\n\n");
|
|
tmxr_attach_help(st, dptr, uptr, flag, cptr);
|
|
|
|
fprintf(st, "----- NOTES -----\n\n");
|
|
fprintf(st, "Only one device may poll the host keyboard for CONSOLE input.\n");
|
|
fprintf(st, "Use SET %s CONSOLE to select this UNIT as the CONSOLE device.\n", sim_dname(dptr));
|
|
fprintf(st, "\nUse SHOW BUS CONSOLE to display the current CONSOLE device.\n\n");
|
|
|
|
return SCPE_OK;
|
|
}
|
|
|