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add w11a port to Arty S7 (BRAM only, sim-tested only)

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wfjm
2018-08-25 07:59:59 +02:00
parent b24fd9a3cb
commit 010c79c0fc
16 changed files with 1109 additions and 1 deletions
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25
rtl/sys_gen/w11a/artys7_bram/Makefile Normal file
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# $Id: Makefile 1038 2018-08-11 12:39:52Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2018-08-05 1038 1.0 Initial version
#
VBOM_all = sys_w11a_br_as7.vbom
BIT_all = $(VBOM_all:.vbom=.bit)
#
include ${RETROBASE}/rtl/make_viv/viv_default_artys7.mk
#
.PHONY : all clean
#
all : $(BIT_all)
#
clean : viv_clean
#
#----
#
include ${RETROBASE}/rtl/make_viv/generic_vivado.mk
#
ifndef DONTINCDEP
include $(VBOM_all:.vbom=.dep_vsyn)
endif
#

6
rtl/sys_gen/w11a/artys7_bram/pdp11_hio70_artys7.vbom Normal file
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# libs
../../../vlib/slvtypes.vhd
../../../w11a/pdp11.vbom
# components
# design
pdp11_hio70_artys7.vhd

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rtl/sys_gen/w11a/artys7_bram/pdp11_hio70_artys7.vhd Normal file
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-- $Id: pdp11_hio70_artys7.vhd 1038 2018-08-11 12:39:52Z mueller $
--
-- Copyright 2018- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 3, or (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: pdp11_hio70_artys7 - syn
-- Description: pdp11: hio led and rgb for sys70 for artys7
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic
-- Tool versions: viv 2017.2-2018.2; ghdl 0.34
--
-- Revision History:
-- Date Rev Version Comment
-- 2018-08-05 1038 1.0 Initial version (cloned from pdp11_hio70_artya7)
------------------------------------------------------------------------------
--
-- collects the output for LED and RGB leds
-- MODE = 00xy
-- LED IO activity
-- (3) not SER_MONI.txok (shows tx back pressure)
-- (2) SER_MONI.txact (shows tx activity)
-- (1) not SER_MONI.rxok (shows rx back pressure)
-- (0) SER_MONI.rxact (shows rx activity)
-- RGB_G CPU busy (active cpugo=1, enabled with y=1)
-- (1) kernel mode, non-wait
-- (0) user or supervisor mode
-- RGB_R CPU rust (active cpugo=0, enabled with y=1)
-- (1:0) cpurust code
-- RGB_B MEM/cmd busy (enabled with x=1)
-- (1) cmdbusy (all rlink access, mostly rdma)
-- (0) not cpugo
--
-- MODE = 0100 (DR emulation)
-- LED DR(15:12)
-- RGB_B DR( 9:08)
-- RGB_G DR( 5:04)
-- RGB_R DR( 1:00)
--
-- MODE = 1xyy (show lsb or msb of 16 bit register)
-- LED show bit 7:4, RGB_G bit 1:0; x=0 shows lsb and x=1 shows msb
-- yy = 00: abclkdiv & abclkdiv_f
-- 01: PC
-- 10: DISPREG
-- 11: DR emulation
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.pdp11.all;
-- ----------------------------------------------------------------------------
entity pdp11_hio70_artys7 is -- hio led+rgb for sys70 for artys7
port (
CLK : in slbit; -- clock
MODE : in slv4; -- mode select
MEM_ACT_R : in slbit; -- memory active read
MEM_ACT_W : in slbit; -- memory active write
CP_STAT : in cp_stat_type; -- console port status
DM_STAT_DP : in dm_stat_dp_type; -- debug and monitor status
DISPREG : in slv16; -- display register
IOLEDS : in slv4; -- serport ioleds
ABCLKDIV : in slv16; -- serport clock divider
LED : out slv4; -- hio leds
RGB_R : out slv2; -- hio rgb leds - red
RGB_G : out slv2; -- hio rgb leds - green
RGB_B : out slv2 -- hio rgb leds - blue
);
end pdp11_hio70_artys7;
architecture syn of pdp11_hio70_artys7 is
signal R_LED : slv4 := (others=>'0');
signal R_RGB_R : slv2 := (others=>'0');
signal R_RGB_G : slv2 := (others=>'0');
signal R_RGB_B : slv2 := (others=>'0');
begin
proc_regs : process (CLK)
variable idat16 : slv16 := (others=>'0');
variable idat8 : slv8 := (others=>'0');
variable iled : slv4 := (others=>'0');
variable irgb_r : slv2 := (others=>'0');
variable irgb_g : slv2 := (others=>'0');
variable irgb_b : slv2 := (others=>'0');
begin
if rising_edge(CLK) then
idat16 := (others=>'0');
case MODE(1 downto 0) is
when "00" => idat16 := ABCLKDIV;
when "01" => idat16 := DM_STAT_DP.pc;
when "10" => idat16 := DISPREG;
when "11" => idat16 := DM_STAT_DP.dsrc;
when others => null;
end case;
if MODE(2) = '0' then
idat8 := idat16( 7 downto 0);
else
idat8 := idat16(15 downto 8);
end if;
iled := (others=>'0');
irgb_r := (others=>'0');
irgb_g := (others=>'0');
irgb_b := (others=>'0');
if MODE(3) = '0' then
if MODE(2) = '0' then -- LED shows IO; RGB shows CPU/MEM
iled := IOLEDS;
if MODE(0) = '1' then
if CP_STAT.cpugo = '1' then
case DM_STAT_DP.psw.cmode is
when c_psw_kmode =>
if CP_STAT.cpuwait = '0' then
irgb_g(1) := '1';
end if;
when c_psw_smode =>
irgb_g(0) := '1';
when c_psw_umode =>
irgb_g(0) := '1';
when others => null;
end case;
else
irgb_r(1 downto 0) := CP_STAT.cpurust(1 downto 0);
end if;
end if; -- MODE(0) = '1'
if MODE(1) = '1' then
irgb_b(1) := CP_STAT.cmdbusy;
irgb_b(0) := not CP_STAT.cpugo;
end if;
else -- LED+RGB show DR emulation
iled := DM_STAT_DP.dsrc(15 downto 12);
irgb_b := DM_STAT_DP.dsrc( 9 downto 8);
irgb_g := DM_STAT_DP.dsrc( 5 downto 4);
irgb_r := DM_STAT_DP.dsrc( 1 downto 0);
end if; -- MODE(2) = '0'
else -- LED+RGB show one of four regs
iled := idat8(7 downto 4);
irgb_g := idat8(1 downto 0);
end if; -- MODE(3) = '0'
R_LED <= iled;
R_RGB_R <= irgb_r;
R_RGB_G <= irgb_g;
R_RGB_B <= irgb_b;
end if;
end process proc_regs;
LED <= R_LED;
RGB_R <= R_RGB_R;
RGB_G <= R_RGB_G;
RGB_B <= R_RGB_B;
end syn;

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rtl/sys_gen/w11a/artys7_bram/sys_conf.vhd Normal file
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-- $Id: sys_conf.vhd 1038 2018-08-11 12:39:52Z mueller $
--
-- Copyright 2018- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 3, or (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for sys_w11a_br_artys7 (for synthesis)
--
-- Dependencies: -
-- Tool versions: viv 2017.2-2018.2; ghdl 0.34
-- Revision History:
-- Date Rev Version Comment
-- 2018-08-11 1038 1.0 Initial version (derived from _aa7 version)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package sys_conf is
-- configure clocks --------------------------------------------------------
constant sys_conf_clksys_vcodivide : positive := 1;
constant sys_conf_clksys_vcomultiply : positive := 8; -- vco 800 MHz
constant sys_conf_clksys_outdivide : positive := 10; -- sys 80 MHz
constant sys_conf_clksys_gentype : string := "MMCM";
-- dual clock design, clkser = 120 MHz
constant sys_conf_clkser_vcodivide : positive := 1;
constant sys_conf_clkser_vcomultiply : positive := 12; -- vco 1200 MHz
constant sys_conf_clkser_outdivide : positive := 10; -- sys 120 MHz
constant sys_conf_clkser_gentype : string := "PLL";
-- configure rlink and hio interfaces --------------------------------------
constant sys_conf_ser2rri_defbaud : integer := 115200; -- default 115k baud
constant sys_conf_hio_debounce : boolean := true; -- instantiate debouncers
-- configure memory controller ---------------------------------------------
constant sys_conf_memctl_mawidth : positive := 4;
constant sys_conf_memctl_nblock : positive := 16;
-- configure debug and monitoring units ------------------------------------
constant sys_conf_rbmon_awidth : integer := 0; -- no rbmon to save BRAMs
constant sys_conf_ibmon_awidth : integer := 0; -- no ibmon to save BRAMs
constant sys_conf_dmscnt : boolean := false;
constant sys_conf_dmhbpt_nunit : integer := 2; -- use 0 to disable
constant sys_conf_dmcmon_awidth : integer := 0; -- no dmcmon to save BRAMs
constant sys_conf_rbd_sysmon : boolean := true; -- SYSMON(XADC)
-- configure w11 cpu core --------------------------------------------------
-- sys_conf_mem_losize is highest 64 byte MMU block number
-- the bram_memcnt uses 4*4kB memory blocks => 1 MEM block = 256 MMU blocks
constant sys_conf_mem_losize : natural := 256*sys_conf_memctl_nblock-1;
constant sys_conf_cache_fmiss : slbit := '0'; -- cache enabled
constant sys_conf_cache_twidth : integer := 9; -- 8kB cache
-- configure w11 system devices --------------------------------------------
-- configure character and communication devices
constant sys_conf_ibd_dl11_1 : boolean := true; -- 2nd DL11
constant sys_conf_ibd_pc11 : boolean := true; -- PC11
constant sys_conf_ibd_lp11 : boolean := true; -- LP11
constant sys_conf_ibd_deuna : boolean := true; -- DEUNA
-- configure mass storage devices
constant sys_conf_ibd_rk11 : boolean := true; -- RK11
constant sys_conf_ibd_rl11 : boolean := true; -- RL11
constant sys_conf_ibd_rhrp : boolean := true; -- RHRP
constant sys_conf_ibd_tm11 : boolean := true; -- TM11
-- configure other devices
constant sys_conf_ibd_iist : boolean := true; -- IIST
-- derived constants =======================================================
constant sys_conf_clksys : integer :=
((100000000/sys_conf_clksys_vcodivide)*sys_conf_clksys_vcomultiply) /
sys_conf_clksys_outdivide;
constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000;
constant sys_conf_clkser : integer :=
((100000000/sys_conf_clkser_vcodivide)*sys_conf_clkser_vcomultiply) /
sys_conf_clkser_outdivide;
constant sys_conf_clkser_mhz : integer := sys_conf_clkser/1000000;
constant sys_conf_ser2rri_cdinit : integer :=
(sys_conf_clkser/sys_conf_ser2rri_defbaud)-1;
end package sys_conf;

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rtl/sys_gen/w11a/artys7_bram/sys_w11a_br_as7.vbom Normal file
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# libs
../../../vlib/slvtypes.vhd
../../../vlib/xlib/xlib.vhd
../../../vlib/genlib/genlib.vhd
../../../vlib/serport/serportlib.vbom
../../../vlib/rbus/rblib.vhd
../../../vlib/rbus/rbdlib.vhd
../../../vlib/rlink/rlinklib.vbom
../../../bplib/bpgen/bpgenlib.vbom
../../../bplib/sysmon/sysmonrbuslib.vbom
../../../ibus/iblib.vhd
../../../ibus/ibdlib.vhd
../../../w11a/pdp11.vhd
${sys_conf := sys_conf.vhd}
# components
[xst,vsyn]../../../vlib/xlib/s7_cmt_sfs_unisim.vbom
[ghdl,isim,vsim]../../../vlib/xlib/s7_cmt_sfs_gsim.vbom
../../../vlib/genlib/clkdivce.vbom
../../../bplib/bpgen/bp_rs232_2line_iob.vbom
../../../vlib/rlink/rlink_sp2c.vbom
../../../w11a/pdp11_sys70.vbom
../../../ibus/ibdr_maxisys.vbom
../../../w11a/pdp11_bram_memctl.vbom
../../../vlib/rlink/ioleds_sp1c.vbom
pdp11_hio70_artys7.vbom
../../../bplib/bpgen/bp_swibtnled.vbom
../../../bplib/bpgen/rgbdrv_3x2mux.vbom
../../../bplib/sysmon/sysmonx_rbus_base.vbom
../../../vlib/rbus/rbd_usracc.vbom
../../../vlib/rbus/rb_sres_or_3.vbom
# design
sys_w11a_br_as7.vhd
@xdc:../../../bplib/artys7/artys7_pclk.xdc
@xdc:../../../bplib/artys7/artys7_pins.xdc

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rtl/sys_gen/w11a/artys7_bram/sys_w11a_br_as7.vhd Normal file
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-- $Id: sys_w11a_br_as7.vhd 1039 2018-08-12 10:04:09Z mueller $
--
-- Copyright 2018- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 3, or (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: sys_w11a_br_as7 - syn
-- Description: w11a test design for as7
--
-- Dependencies: vlib/xlib/s7_cmt_sfs
-- vlib/genlib/clkdivce
-- bplib/bpgen/bp_rs232_2line_iob
-- vlib/rlink/rlink_sp2c
-- w11a/pdp11_sys70
-- ibus/ibdr_maxisys
-- w11a/pdp11_bram_memctl
-- vlib/rlink/ioleds_sp1c
-- pdp11_hio70_artys7
-- bplib/bpgen/bp_swibtnled
-- bplib/bpgen/rgbdrv_3x2mux
-- bplib/sysmon/sysmonx_rbus_base
-- vlib/rbus/rbd_usracc
-- vlib/rbus/rb_sres_or_3
--
-- Test bench: tb/tb_sys_w11a_br_as7
--
-- Target Devices: generic
-- Tool versions: viv 2017.2-2018.2; ghdl 0.34
--
-- Synthesized:
-- Date Rev viv Target flop lutl lutm bram slic
-- 2018-08-11 1038 2018.2 xc7s50 2279 5369 138 67.5 1598
-- 2018-08-11 1038 2018.1 xc7s50 2279 5381 138 67.5 1597
-- 2018-08-11 1038 2017.4 xc7s50 2274 5137 138 67.5 1549
-- 2018-08-11 1038 2017.2 xc7s50 2271 5083 138 67.5 1560
--
-- Revision History:
-- Date Rev Version Comment
-- 2018-08-11 1038 1.0 Initial version (derived from sys_w11a_aa7)
------------------------------------------------------------------------------
--
-- w11a test design for artys7 (using BRAM as memory)
-- w11a + rlink + serport
--
-- Usage of Arty S7 switches, Buttons, LEDs
--
-- SWI(3:0): determine what is displayed in the LEDs and RGBLEDs
-- 00xy LED shows IO
-- y=1 enables CPU activities on RGB_G,RGB_R
-- x=1 enables MEM activities on RGB_B
-- 0100 LED+RGB give DR emulation 'light show'
-- 1xyy LED+RGB show low (x=0) or high (x=1) byte of
-- yy = 00: abclkdiv & abclkdiv_f
-- 01: PC
-- 10: DISPREG
-- 11: DR emulation
-- LED shows bit 7:4, RGB bit 1:0 of the byte selected by x
--
-- LED and RGB assignment for SWI=00xy
-- LED IO activity
-- (3) not SER_MONI.txok (shows tx back pressure)
-- (2) SER_MONI.txact (shows tx activity)
-- (1) not SER_MONI.rxok (shows rx back pressure)
-- (0) SER_MONI.rxact (shows rx activity)
-- RGB_G CPU busy (active cpugo=1, enabled with SWI(0))
-- (1) kernel mode, non-wait
-- (0) user or supervisor mode
-- RGB_R CPU rust (active cpugo=0, enabled with SWI(0))
-- (1:0) cpurust code
-- RGB_B MEM/cmd busy (enabled with SWI(1))
-- (1) cmdbusy (all rlink access, mostly rdma)
-- (0) not cpugo
--
-- LED and RGB assignment for SWI=0100 (DR emulation)
-- LED DR(15:12)
-- RGB_B DR( 9:08)
-- RGB_G DR( 5:04)
-- RGB_R DR( 1:00)
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.xlib.all;
use work.genlib.all;
use work.serportlib.all;
use work.rblib.all;
use work.rbdlib.all;
use work.rlinklib.all;
use work.bpgenlib.all;
use work.sysmonrbuslib.all;
use work.iblib.all;
use work.ibdlib.all;
use work.pdp11.all;
use work.sys_conf.all;
-- ----------------------------------------------------------------------------
entity sys_w11a_br_as7 is -- top level
-- implements artys7_aif
port (
I_CLK100 : in slbit; -- 100 MHz clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
I_SWI : in slv4; -- artys7 switches
I_BTN : in slv4; -- artys7 buttons
O_LED : out slv4; -- artys7 leds
O_RGBLED0 : out slv3; -- artys7 rgb-led 0
O_RGBLED1 : out slv3 -- artys7 rgb-led 1
);
end sys_w11a_br_as7;
architecture syn of sys_w11a_br_as7 is
signal CLK : slbit := '0';
signal RESET : slbit := '0';
signal CE_USEC : slbit := '0';
signal CE_MSEC : slbit := '0';
signal CLKS : slbit := '0';
signal CES_MSEC : slbit := '0';
signal RXD : slbit := '1';
signal TXD : slbit := '0';
signal RB_MREQ : rb_mreq_type := rb_mreq_init;
signal RB_SRES : rb_sres_type := rb_sres_init;
signal RB_SRES_CPU : rb_sres_type := rb_sres_init;
signal RB_SRES_HIO : rb_sres_type := rb_sres_init;
signal RB_SRES_SYSMON : rb_sres_type := rb_sres_init;
signal RB_SRES_USRACC : rb_sres_type := rb_sres_init;
signal RB_LAM : slv16 := (others=>'0');
signal RB_STAT : slv4 := (others=>'0');
signal SER_MONI : serport_moni_type := serport_moni_init;
signal GRESET : slbit := '0'; -- general reset (from rbus)
signal CRESET : slbit := '0'; -- cpu reset (from cp)
signal BRESET : slbit := '0'; -- bus reset (from cp or cpu)
signal ITIMER : slbit := '0';
signal EI_PRI : slv3 := (others=>'0');
signal EI_VECT : slv9_2 := (others=>'0');
signal EI_ACKM : slbit := '0';
signal CP_STAT : cp_stat_type := cp_stat_init;
signal DM_STAT_DP : dm_stat_dp_type := dm_stat_dp_init;
signal MEM_REQ : slbit := '0';
signal MEM_WE : slbit := '0';
signal MEM_BUSY : slbit := '0';
signal MEM_ACK_R : slbit := '0';
signal MEM_ACT_R : slbit := '0';
signal MEM_ACT_W : slbit := '0';
signal MEM_ADDR : slv20 := (others=>'0');
signal MEM_BE : slv4 := (others=>'0');
signal MEM_DI : slv32 := (others=>'0');
signal MEM_DO : slv32 := (others=>'0');
signal IB_MREQ : ib_mreq_type := ib_mreq_init;
signal IB_SRES_IBDR : ib_sres_type := ib_sres_init;
signal DISPREG : slv16 := (others=>'0');
signal ABCLKDIV : slv16 := (others=>'0');
signal IOLEDS : slv4 := (others=>'0');
signal SWI : slv4 := (others=>'0');
signal BTN : slv4 := (others=>'0');
signal LED : slv4 := (others=>'0');
signal RGB_R : slv2 := (others=>'0');
signal RGB_G : slv2 := (others=>'0');
signal RGB_B : slv2 := (others=>'0');
constant rbaddr_rbmon : slv16 := x"ffe8"; -- ffe8/0008: 1111 1111 1110 1xxx
constant rbaddr_sysmon: slv16 := x"fb00"; -- fb00/0080: 1111 1011 0xxx xxxx
constant sysid_proj : slv16 := x"0201"; -- w11a
constant sysid_board : slv8 := x"0a"; -- artys7
constant sysid_vers : slv8 := x"00";
begin
assert (sys_conf_clksys mod 1000000) = 0
report "assert sys_conf_clksys on MHz grid"
severity failure;
GEN_CLKSYS : s7_cmt_sfs -- clock generator system ------------
generic map (
VCO_DIVIDE => sys_conf_clksys_vcodivide,
VCO_MULTIPLY => sys_conf_clksys_vcomultiply,
OUT_DIVIDE => sys_conf_clksys_outdivide,
CLKIN_PERIOD => 10.0,
CLKIN_JITTER => 0.01,
STARTUP_WAIT => false,
GEN_TYPE => sys_conf_clksys_gentype)
port map (
CLKIN => I_CLK100,
CLKFX => CLK,
LOCKED => open
);
CLKDIV_CLK : clkdivce -- usec/msec clock divider system ----
generic map (
CDUWIDTH => 7,
USECDIV => sys_conf_clksys_mhz,
MSECDIV => 1000)
port map (
CLK => CLK,
CE_USEC => CE_USEC,
CE_MSEC => CE_MSEC
);
GEN_CLKSER : s7_cmt_sfs -- clock generator serport------------
generic map (
VCO_DIVIDE => sys_conf_clkser_vcodivide,
VCO_MULTIPLY => sys_conf_clkser_vcomultiply,
OUT_DIVIDE => sys_conf_clkser_outdivide,
CLKIN_PERIOD => 10.0,
CLKIN_JITTER => 0.01,
STARTUP_WAIT => false,
GEN_TYPE => sys_conf_clkser_gentype)
port map (
CLKIN => I_CLK100,
CLKFX => CLKS,
LOCKED => open
);
CLKDIV_CLKS : clkdivce -- usec/msec clock divider serport ---
generic map (
CDUWIDTH => 7,
USECDIV => sys_conf_clkser_mhz,
MSECDIV => 1000)
port map (
CLK => CLKS,
CE_USEC => open,
CE_MSEC => CES_MSEC
);
IOB_RS232 : bp_rs232_2line_iob -- serport iob ----------------------
port map (
CLK => CLKS,
RXD => RXD,
TXD => TXD,
I_RXD => I_RXD,
O_TXD => O_TXD
);
RLINK : rlink_sp2c -- rlink for serport -----------------
generic map (
BTOWIDTH => 7, -- 128 cycles access timeout
RTAWIDTH => 12,
SYSID => sysid_proj & sysid_board & sysid_vers,
IFAWIDTH => 5, -- 32 word input fifo
OFAWIDTH => 5, -- 32 word output fifo
ENAPIN_RLMON => sbcntl_sbf_rlmon,
ENAPIN_RBMON => sbcntl_sbf_rbmon,
CDWIDTH => 12,
CDINIT => sys_conf_ser2rri_cdinit,
RBMON_AWIDTH => sys_conf_rbmon_awidth,
RBMON_RBADDR => rbaddr_rbmon)
port map (
CLK => CLK,
CE_USEC => CE_USEC,
CE_MSEC => CE_MSEC,
CE_INT => CE_MSEC,
RESET => RESET,
CLKS => CLKS,
CES_MSEC => CES_MSEC,
ENAXON => '1', -- XON statically enabled !
ESCFILL => '0',
RXSD => RXD,
TXSD => TXD,
CTS_N => '0',
RTS_N => open,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES,
RB_LAM => RB_LAM,
RB_STAT => RB_STAT,
RL_MONI => open,
SER_MONI => SER_MONI
);
SYS70 : pdp11_sys70 -- 1 cpu system ----------------------
port map (
CLK => CLK,
RESET => RESET,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_CPU,
RB_STAT => RB_STAT,
RB_LAM_CPU => RB_LAM(0),
GRESET => GRESET,
CRESET => CRESET,
BRESET => BRESET,
CP_STAT => CP_STAT,
EI_PRI => EI_PRI,
EI_VECT => EI_VECT,
EI_ACKM => EI_ACKM,
ITIMER => ITIMER,
IB_MREQ => IB_MREQ,
IB_SRES => IB_SRES_IBDR,
MEM_REQ => MEM_REQ,
MEM_WE => MEM_WE,
MEM_BUSY => MEM_BUSY,
MEM_ACK_R => MEM_ACK_R,
MEM_ADDR => MEM_ADDR,
MEM_BE => MEM_BE,
MEM_DI => MEM_DI,
MEM_DO => MEM_DO,
DM_STAT_DP => DM_STAT_DP
);
IBDR_SYS : ibdr_maxisys -- IO system -------------------------
port map (
CLK => CLK,
CE_USEC => CE_USEC,
CE_MSEC => CE_MSEC,
RESET => GRESET,
BRESET => BRESET,
ITIMER => ITIMER,
CPUSUSP => CP_STAT.cpususp,
RB_LAM => RB_LAM(15 downto 1),
IB_MREQ => IB_MREQ,
IB_SRES => IB_SRES_IBDR,
EI_ACKM => EI_ACKM,
EI_PRI => EI_PRI,
EI_VECT => EI_VECT,
DISPREG => DISPREG
);
BRAM_CTL: pdp11_bram_memctl -- memory controller -----------------
generic map (
MAWIDTH => sys_conf_memctl_mawidth,
NBLOCK => sys_conf_memctl_nblock)
port map (
CLK => CLK,
RESET => GRESET,
REQ => MEM_REQ,
WE => MEM_WE,
BUSY => MEM_BUSY,
ACK_R => MEM_ACK_R,
ACK_W => open,
ACT_R => MEM_ACT_R,
ACT_W => MEM_ACT_W,
ADDR => MEM_ADDR,
BE => MEM_BE,
DI => MEM_DI,
DO => MEM_DO
);
LED_IO : ioleds_sp1c -- hio leds from serport -------------
port map (
SER_MONI => SER_MONI,
IOLEDS => IOLEDS
);
ABCLKDIV <= SER_MONI.abclkdiv(11 downto 0) & '0' & SER_MONI.abclkdiv_f;
HIO70 : entity work.pdp11_hio70_artys7 -- hio from sys70 --------------------
port map (
CLK => CLK,
MODE => SWI,
MEM_ACT_R => MEM_ACT_R,
MEM_ACT_W => MEM_ACT_W,
CP_STAT => CP_STAT,
DM_STAT_DP => DM_STAT_DP,
DISPREG => DISPREG,
IOLEDS => IOLEDS,
ABCLKDIV => ABCLKDIV,
LED => LED,
RGB_R => RGB_R,
RGB_G => RGB_G,
RGB_B => RGB_B
);
HIO : bp_swibtnled
generic map (
SWIDTH => I_SWI'length,
BWIDTH => I_BTN'length,
LWIDTH => O_LED'length,
DEBOUNCE => sys_conf_hio_debounce)
port map (
CLK => CLK,
RESET => RESET,
CE_MSEC => CE_MSEC,
SWI => SWI,
BTN => BTN,
LED => LED,
I_SWI => I_SWI,
I_BTN => I_BTN,
O_LED => O_LED
);
HIORGB : rgbdrv_3x2mux
port map (
CLK => CLK,
RESET => RESET,
CE_USEC => CE_USEC,
DATR => RGB_R,
DATG => RGB_G,
DATB => RGB_B,
O_RGBLED0 => O_RGBLED0,
O_RGBLED1 => O_RGBLED1
);
SMRB : if sys_conf_rbd_sysmon generate
I0: sysmonx_rbus_base
generic map ( -- use default INIT_ (Vccint=1.00)
CLK_MHZ => sys_conf_clksys_mhz,
RB_ADDR => rbaddr_sysmon)
port map (
CLK => CLK,
RESET => RESET,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_SYSMON,
ALM => open,
OT => open,
TEMP => open
);
end generate SMRB;
UARB : rbd_usracc
port map (
CLK => CLK,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_USRACC
);
RB_SRES_OR : rb_sres_or_3 -- rbus or ---------------------------
port map (
RB_SRES_1 => RB_SRES_CPU,
RB_SRES_2 => RB_SRES_SYSMON,
RB_SRES_3 => RB_SRES_USRACC,
RB_SRES_OR => RB_SRES
);
end syn;

96
rtl/sys_gen/w11a/artys7_bram/sys_w11a_br_as7.vmfset Normal file
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# $Id: sys_w11a_br_as7.vmfset 1039 2018-08-12 10:04:09Z mueller $
#
# ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
[syn]
# general issues -----------------------------------------------
{2018.2:}
# stupid new warning, Xilinx suggests to safely ingnore
i [Constraints 18-5210] # generic
{:}
# binding instance .. which has no pins ------------------------
I [Synth 8-115] # generic
# false_path -hold ignored by synth ----------------------------
I [Designutils 20-1567] # generic
# net without driver -------------------------------------------
# unconnected ports --------------------------------------------
I [Synth 8-3331] RB_MREQ # generic
I [Synth 8-3331] DM_STAT_DP # generic
# --> pdp11_hio70_arty uses only subset of CP_STAT info # OK 2018-08-11
I [Synth 8-3331] pdp11_hio70_arty.*CP_STAT[.*]
I [Synth 8-3331] pdp11_hio70_artys7.*MEM_ACT_(R|W)
# sequential element removed (2017.1 nonsense) -----------------
I [Synth 8-6014] _reg # generic
# unused sequential element ------------------------------------
{2017.2:}
I [Synth 8-3332] R_LREGS_reg[attn][\d*] # generic
# --> not yet used # OK 2018-08-11
i [Synth 8-3332] R_STATUS_reg[suspext].* pdp11_sequencer
# --> mawidth=4, nblock=11, so some cellen unused # OK 2018-08-11
i [Synth 8-3332] R_REGS_reg[dtyp][3].* ibdr_rhrp
# --> not yet used # OK 2018-08-11
i [Synth 8-3332] R_REGS_reg[req_lock].* ibd_iist
i [Synth 8-3332] R_REGS_reg[req_boot].* ibd_iist
# --> [8] is for DZ11TX, not yet available # OK 2018-08-11
# --> [9] is for DZ11RX, unclear why this one isn't removed too !!
i [Synth 8-3332] R_STATUS_reg[intvect][8].* pdp11_sequencer
# --> _decode only uses _[oalm]unit -> [2] always '0' in decode # OK 2018-08-11
i [Synth 8-3332] R_IDSTAT_reg[res_sel][2].* pdp11_sequencer
# --> dmcmon not configured, snum not used
i [Synth 8-3332] SNUM0.R_VMWAIT_reg.* pdp11_sequencer # OK 2018-08-11
{2017.2:2017.4}
# --> many HIO pins not used # OK 2018-08-11
I [Synth 8-3332] HIO/R_REGS_reg[(btn|swi)(eff)?][\d*]
i [Synth 8-3332] HIO/IOB_BTN/R_DI_reg[\d*]
i [Synth 8-3332] HIO/DEB.DEB_BTN/R_REGS_reg[(dref|dout|dchange|cecnt)][\d*]
# --> usec not used for serport clock domain # OK 2018-08-11
i [Synth 8-3332] CLKDIV_CLKS/R_REGS_reg[usec]
# --> inst_compl logic disabled in pdp11_mmu # OK 2018-08-11
i [Synth 8-3332] MMU/R_SSR0_reg[inst_compl].* pdp11_vmbox
# --> IB_MREQ.cacc only used in ibd_ibmon, which is disabled # OK 2018-08-11
i [Synth 8-3332] R_REGS_reg[ibcacc].* pdp11_vmbox
# --> monitor outputs moneop,monattn currently not used # OK 2018-08-11
i [Synth 8-3332] RLINK/CORE/RL/R_LREGS_reg[moneop]
i [Synth 8-3332] RLINK/CORE/RL/R_LREGS_reg[monattn]
{2018.1:}
# --> many HIO pins not used # OK 2018-08-11
I [Synth 8-3332] HIO/R_REGS_reg[(btn|swi)(eff)?][\d*]
i [Synth 8-3332] IOB_BTN/R_DI_reg[\d*]
i [Synth 8-3332] DEB.DEB_BTN/R_REGS_reg[(dref|dout|dchange|cecnt)][\d*]
# --> usec not used for serport clock domain # OK 2018-08-11
i [Synth 8-3332] R_REGS_reg[usec].* clkdivce
# --> inst_compl logic disabled in pdp11_mmu # OK 2018-08-11
i [Synth 8-3332] MMU/R_SSR0_reg[inst_compl].* pdp11_core
# --> IB_MREQ.cacc only used in ibd_ibmon, which is disabled # OK 2018-08-11
i [Synth 8-3332] R_REGS_reg[ibcacc].* pdp11_core
# --> monitor outputs moneop,monattn currently not used # OK 2018-08-11
i [Synth 8-3332] CORE/RL/R_LREGS_reg[moneop]
i [Synth 8-3332] CORE/RL/R_LREGS_reg[monattn]
{:}
# INFO: encoded FSM with state register as --------------------
# test for sys_w11a_as7 that all FSMs are one_hot
r [Synth 8-3354] R_BREGS_reg[state.*'one-hot'.*'rlink_core'
r [Synth 8-3354] R_LREGS_reg[state].*'one-hot'.*'rlink_core'
r [Synth 8-3354] R_REGS_reg[state].*'one-hot'.*'serport_uart_autobaud'
r [Synth 8-3354] R_REGS_reg[state].*'one-hot'.*'serport_uart_rx'
r [Synth 8-3354] R_REGS_reg[state].*'one-hot'.*'pdp11_core_rbus'
r [Synth 8-3354] R_REGS_reg[state].*'one-hot'.*'pdp11_vmbox'
r [Synth 8-3354] R_STATE_reg.*'one-hot'.*'pdp11_sequencer'
r [Synth 8-3354] R_REGS_reg[state].*'one-hot'.*'pdp11_cache'
r [Synth 8-3354] R_REGS_reg[state].*'one-hot'.*'ibdr_rhrp'
r [Synth 8-3354] R_REGS_reg[state].*'one-hot'.*'ibdr_rl11'
r [Synth 8-3354] R_REGS_reg[state].*'one-hot'.*'sysmon_rbus_core'
# ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
[imp]
I [Vivado 12-2489] # multiple of 1 ps
I [Physopt 32-742] # BRAM Flop Optimization

2
rtl/sys_gen/w11a/artys7_bram/tb/.gitignore vendored Normal file
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tb_w11a_br_as7
sysmon_stim

39
rtl/sys_gen/w11a/artys7_bram/tb/Makefile Normal file
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# $Id: Makefile 1038 2018-08-11 12:39:52Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2018-08-11 1038 1.0 Initial version
#
EXE_all = tb_w11a_br_as7
#
include ${RETROBASE}/rtl/make_viv/viv_default_artys7.mk
#
.PHONY : all all_ssim all_osim clean
.PHONY : all_XSim all_XSim_ssim all_XSim_osim all_XSim_tsim
#
all : $(EXE_all)
all_ssim : $(EXE_all:=_ssim)
all_osim : $(EXE_all:=_osim)
#
all_XSim : $(EXE_all:=_XSim)
all_XSim_ssim : $(EXE_all:=_XSim_ssim)
all_XSim_osim : $(EXE_all:=_XSim_osim)
all_XSim_tsim : $(EXE_all:=_XSim_tsim)
#
clean : viv_clean ghdl_clean xsim_clean
#
#-----
#
include ${RETROBASE}/rtl/make_viv/generic_ghdl.mk
include ${RETROBASE}/rtl/make_viv/generic_xsim.mk
include ${RETROBASE}/rtl/make_viv/generic_vivado.mk
#
VBOM_all = $(wildcard *.vbom)
#
ifndef DONTINCDEP
include $(VBOM_all:.vbom=.dep_vsyn)
include $(VBOM_all:.vbom=.dep_ghdl)
include $(VBOM_all:.vbom=.dep_vsim)
include $(wildcard *.o.dep_ghdl)
endif
#

94
rtl/sys_gen/w11a/artys7_bram/tb/sys_conf_sim.vhd Normal file
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-- $Id: sys_conf_sim.vhd 1038 2018-08-11 12:39:52Z mueller $
--
-- Copyright 2018- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 3, or (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for sys_w11a_br_as7 (for simulation)
--
-- Dependencies: -
-- Tool versions: viv 2017.2-2018.2; ghdl 0.34
-- Revision History:
-- Date Rev Version Comment
-- 2018-08-11 1038 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package sys_conf is
-- configure clocks --------------------------------------------------------
constant sys_conf_clksys_vcodivide : positive := 1;
constant sys_conf_clksys_vcomultiply : positive := 8; -- vco 800 MHz
constant sys_conf_clksys_outdivide : positive := 10; -- sys 80 MHz
constant sys_conf_clksys_gentype : string := "MMCM";
-- dual clock design, clkser = 120 MHz
constant sys_conf_clkser_vcodivide : positive := 1;
constant sys_conf_clkser_vcomultiply : positive := 12; -- vco 1200 MHz
constant sys_conf_clkser_outdivide : positive := 10; -- sys 120 MHz
constant sys_conf_clkser_gentype : string := "PLL";
-- configure rlink and hio interfaces --------------------------------------
constant sys_conf_ser2rri_cdinit : integer := 1-1; -- 1 cycle/bit in sim
constant sys_conf_hio_debounce : boolean := false; -- no debouncers
-- configure memory controller ---------------------------------------------
constant sys_conf_memctl_mawidth : positive := 4;
constant sys_conf_memctl_nblock : positive := 16;
-- configure debug and monitoring units ------------------------------------
constant sys_conf_rbmon_awidth : integer := 0; -- no rbmon to save BRAMs
constant sys_conf_ibmon_awidth : integer := 0; -- no ibmon to save BRAMs
constant sys_conf_dmscnt : boolean := false;
constant sys_conf_dmhbpt_nunit : integer := 2; -- use 0 to disable
constant sys_conf_dmcmon_awidth : integer := 0; -- no dmcmon to save BRAMs
constant sys_conf_rbd_sysmon : boolean := true; -- SYSMON(XADC)
-- configure w11 cpu core --------------------------------------------------
-- sys_conf_mem_losize is highest 64 byte MMU block number
-- the bram_memcnt uses 4*4kB memory blocks => 1 MEM block = 256 MMU blocks
constant sys_conf_mem_losize : natural := 256*sys_conf_memctl_nblock-1;
constant sys_conf_cache_fmiss : slbit := '0'; -- cache enabled
constant sys_conf_cache_twidth : integer := 9; -- 8kB cache
-- configure w11 system devices --------------------------------------------
-- configure character and communication devices
constant sys_conf_ibd_dl11_1 : boolean := true; -- 2nd DL11
constant sys_conf_ibd_pc11 : boolean := true; -- PC11
constant sys_conf_ibd_lp11 : boolean := true; -- LP11
constant sys_conf_ibd_deuna : boolean := true; -- DEUNA
-- configure mass storage devices
constant sys_conf_ibd_rk11 : boolean := true; -- RK11
constant sys_conf_ibd_rl11 : boolean := true; -- RL11
constant sys_conf_ibd_rhrp : boolean := true; -- RHRP
constant sys_conf_ibd_tm11 : boolean := true; -- TM11
-- configure other devices
constant sys_conf_ibd_iist : boolean := true; -- IIST
-- derived constants =======================================================
constant sys_conf_clksys : integer :=
((100000000/sys_conf_clksys_vcodivide)*sys_conf_clksys_vcomultiply) /
sys_conf_clksys_outdivide;
constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000;
constant sys_conf_clkser : integer :=
((100000000/sys_conf_clkser_vcodivide)*sys_conf_clkser_vcomultiply) /
sys_conf_clkser_outdivide;
constant sys_conf_clkser_mhz : integer := sys_conf_clkser/1000000;
end package sys_conf;

9
rtl/sys_gen/w11a/artys7_bram/tb/tb_w11a_br_as7.vbom Normal file
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# configure tb_artys7 with sys_w11a_br_as7 target;
# use vhdl configure file (tb_w11a_br_as7.vhd) to allow
# that all configurations will co-exist in work library
# configure
artys7_aif = ../sys_w11a_br_as7.vbom
sys_conf = sys_conf_sim.vhd
# design
../../../../bplib/artys7/tb/tb_artys7.vbom
tb_w11a_br_as7.vhd

35
rtl/sys_gen/w11a/artys7_bram/tb/tb_w11a_br_as7.vhd Normal file
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-- $Id: tb_w11a_br_as7.vhd 1038 2018-08-11 12:39:52Z mueller $
--
-- Copyright 2018- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 3, or (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: tb_w11a_br_as7
-- Description: Configuration for tb_w11a_br_as7 for tb_artys7
--
-- Dependencies: sys_w11a_br_as7
--
-- To test: sys_w11a_br_as7
--
-- Revision History:
-- Date Rev Version Comment
-- 2018-08-11 1038 1.0 Initial version
------------------------------------------------------------------------------
configuration tb_w11a_br_as7 of tb_artys7 is
for sim
for all : artys7_aif
use entity work.sys_w11a_br_as7;
end for;
end for;
end tb_w11a_br_as7;

8
rtl/sys_gen/w11a/artys7_bram/tb/tb_w11a_br_as7_ssim.vbom Normal file
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# configure for _*sim case
# Note: this tb uses sys_w11a_br_as7.vbom in local directory
# (not in .. as usual) to allow a tb specific configure !!!
# configure
artys7_aif = sys_w11a_br_as7_ssim.vhd
# design
tb_w11a_br_as7.vbom
@top:tb_w11a_br_as7

29
rtl/sys_gen/w11a/artys7_bram/tb/tbrun.yml Normal file
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# $Id: tbrun.yml 1038 2018-08-11 12:39:52Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2018-08-11 1038 1.0 Initial version
#
- default:
mode: ${viv_modes}
#
- tag: [viv, sys_w11a, br_as7, stim1]
test: |
tbrun_tbwrri --hxon --lsuf stim1 tb_w11a_br_as7${ms} \
"rlink::run_rri ../../../../w11a/tb/tb_rlink_tba_pdp11core_stim.dat"
- tag: [viv, sys_w11a, br_as7, stim2]
test: |
tbrun_tbwrri --hxon --lsuf stim2 --pack rw11 tb_w11a_br_as7${ms} \
"rw11::setup_cpu" \
"rw11::run_pdpcp ../../../../w11a/tb/tb_pdp11core_stim.dat 60."
- tag: [viv, sys_w11a, br_as7, tbcpu]
test: |
tbrun_tbwrri --hxon --lsuf tbcpu --pack rw11 tb_w11a_br_as7${ms} \
"rw11::setup_cpu" "rw11::tbench @cpu_all.dat"
- tag: [viv, sys_w11a, br_as7, tbdev]
test: |
tbrun_tbwrri --hxon --lsuf tbdev --pack rw11 tb_w11a_br_as7${ms} \
"rw11::setup_cpu" "rw11::tbench @dev_all.dat"

7
rtl/sys_gen/w11a/artys7_bram/tb/tbw.dat Normal file
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# $Id: tbw.dat 1038 2018-08-11 12:39:52Z mueller $
#
[tb_w11a_br_as7]
rlink_cext_fifo_rx = <fifo>
rlink_cext_fifo_tx = <fifo>
rlink_cext_conf = <null>
sysmon_stim = ../../../../bplib/sysmon/tb/sysmon_stim_n4.dat

5
rtl/sys_gen/w11a/tbrun.yml
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@@ -1,7 +1,8 @@
# $Id: tbrun.yml 916 2017-06-25 13:30:07Z mueller $
# $Id: tbrun.yml 1038 2018-08-11 12:39:52Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2018-08-11 1038 1.1 add artys7
# 2017-06-25 914 1.1 add cmoda7
# 2016-08-22 800 1.0 Initial version
#
@@ -9,6 +10,8 @@
- include: nexys2/tb/tbrun.yml
- include: nexys3/tb/tbrun.yml
- include: nexys4/tb/tbrun.yml
- include: nexys4_bram/tb/tbrun.yml
- include: basys3/tb/tbrun.yml
- include: arty_bram/tb/tbrun.yml
- include: artys7_bram/tb/tbrun.yml
- include: cmoda7/tb/tbrun.yml