docu updates [skip ci]

doc/ECO-035-stklim-tbit-fixes.md

@@ -6,8 +6,8 @@
 
 ### Symptom summary
 The w11 had several deficits in the stack protection, the yellow stack trap,
-and T-bit trace trap logic. They caused diagnostic messages in `ekbee1` and
-`eqkce1` xxdp tests.
+and T-bit trace trap logic. They caused diagnostic messages in the xxdp
+programs `ekbee1` and `eqkce1`.
 
 ### Background
 The 11/70, and also the 11/45, differ from most other PDP-11 models in the

doc/ECO-037-mmu-instruction_complete.md

@@ -40,8 +40,8 @@ The `MMR2` register is loaded from the virtual address
 - at the beginning of an instruction fetch (VA = instruction address)
 
 ### Hindsight
-This is the most mysterious feature of an 11/70. It was only exercised in one
-xxdp test and never used. Because of poor documentation, it took a long time to
-understand what it really does and what it can be used for. Nevertheless,
-the goal of the w11 is to be an as precise as feasible replica of the 11/70,
-and it was time to finally implement this esoteric feature.
+This is the most mysterious feature of an 11/70. It was only exercised in test
+067 of the xxdp program `ekbee1` and never used. Because of poor documentation,
+it took a long time to understand what it really does and what it can be used
+for. Nevertheless, the goal of the w11 is to be an as precise as feasible
+replica of the 11/70, and it was time to finally implement this esoteric feature.

doc/README_resolved_issues.md

@@ -260,7 +260,7 @@ Fixed Resolved with buffered DL11 in commit
 
 ### V0.50-10 {[issue #20](https://github.com/wfjm/w11/issues/20)} -- DL11: output chars lost when device polling used
 #### Original Issue
-Part of the console output can be lost when `xxdp` test `eqkce1` is
+Part of the console output can be lost when `xxdp` program `eqkce1` is
 run on FPGA, also some kernel messages during the 2.11bsd boot sequence.
 In both cases very simple polling output routines are used. Most likely
 cause is that device ready polls timeout before the rlink interface can

doc/simh_diff_div_after_v1.md

@@ -14,8 +14,8 @@ in sometimes surprising settings.
 SimH returns Z=0 and N based on the sign of the full 32-bit result, as can be
 easily determined by xor'ing of the sign bits of dividend and divisor.
 
-xxdp `ekbbf0` test 15 tests the exact 11/70 behavior to verify the
-divide logic and is skipped.
+xxdp program `ekbbf0` test 014 checks the exact 11/70 behavior to verify the
+divide logic and is modified (see [patch](../tools/xxdp/ekbbf0_patch_1170.scmd)).
 
 w11 also returns Z=0 and N based on the sign of the full 32-bit result, this
 is documented as [w11 known difference](w11a_diff_70_div_after_v1.md).

doc/simh_diff_instruction_complete.md

@@ -18,7 +18,11 @@ aborted. The `MMR2` contains the vector address in the latter case.
 
 SimH does not support the `MMR0` `instruction completed` flag and the
 associated `MMR2` behavior.
-xxdp `ekbee1` test 67 verifies this behavior and is skipped.
+xxdp program `ekbee1` test 067 verifies this behavior and is skipped
+(see [patch](../tools/xxdp/ekbee1_patch_1170.scmd)).
 
 w11 supports `instruction completed` with some minor implementation differences,
 see [w11 known difference](w11a_diff_70_instruction_complete.md).
+This is verified in a [tcode](../tools/tcode/README.md), the tests are skipped
+when executed on SimH
+(see [cpu_mmu.mac](../tools/tcode/cpu_mmu.mac) test C2.6 and D2.1).

doc/simh_diff_mmr1.md

@@ -0,0 +1,27 @@
+## Known differences between SimH, 11/70, and w11a
+
+### SimH: `MMR1` recording has J11 behavior
+
+The register `MMR1` records register modifications and can be used in the event
+of an MMU abort to rollback the register state and re-execute the instruction.
+Explicit `PC` modifications from addressing mode 2 or 3 accesses can be
+recorded, but are ignored in MMU abort handling because the `PC` roll back
+is done with `MMR2`. Implicit `PC` modifications from instruction fetch or
+index word reads are never recorded in `MMR1`.
+Essential is, that the content of `MMR1` reflects the register modifications
+_at the time of the instruction abort_.
+
+The 11/70 and the J11 `MMR1` recording behavior differs in several respects:
+- for instructions with implicit stack pops (`RTS`, `MTPI`, `MTPD`) the
+  11/70 updates the `SP` and records this in `MMR1` before accessing the stack
+  value and detecting an MMU abort. The J11 increments `SP` after the stack
+  access.
+- the 11/70 records `PC` changes from immediate value are absolute
+  addressing modes. The J11, with a much more sophisticated instruction
+  stream prefetch, doesn't.
+
+SimH uses the J11 `MMR1` behavior for all models.
+
+w11 implements the 11/70 behavior. This is verified in a
+[tcode](../tools/tcode/README.md), the tests are skipped when executed on SimH
+(see [cpu_mmu.mac](../tools/tcode/cpu_mmu.mac) test C1.1 and C2.3).

doc/simh_diff_mmr1_rts_mtp.md

@@ -1,12 +0,0 @@
-## Known differences between SimH, 11/70, and w11a
-
-### SimH: implicit stack pops not recorded in `MMR1`
-
-The MMU abort behavior for instructions with implicit stack pops
-(`RTS`, `MTPI`, `MTPD`) differs for SimH from a real 11/70 and from w11.
-SimH updates the stack pointer _after_ the stack value has been
-read. If this read is aborted by the MMU, the state is `SP` unchanged
-and `MMR1` zero. A real 11/70 and w11 update `SP` and record that in
-`MMR1` before the stack value is accessed and an MMU abort detected.
-In both cases the register change state and the `MMR1` state
-are consistent, so MMU vector 250 handlers will work correctly.

doc/simh_diff_mmu_nxm_prio.md

@@ -10,8 +10,9 @@ In the KB11-C processor, the NXM condition is handled before the MMU condition.
 This leads to the surprising situation that the access is aborted with a
 vector 4 flow rather than a vector 250 flow.
 
-SimH verifies the MMU abort condition first. xxdp `ekbee1` test 122 verifies
-the 11/70 behavior and is patched.
+SimH verifies the MMU abort condition first. xxdp program `ekbee1` test 122
+verifies the 11/70 behavior and is modified
+(see [patch](../tools/xxdp/ekbee1_patch_1170.scmd)).
 
 w11 also doesn't support this behavior, this is documented as
 [w11 known difference](w11a_diff_70_mmu_nxm_prio.md).

doc/simh_diff_mmu_trap_suppression.md

@@ -7,7 +7,8 @@ when an MMU register is accessed, thus `MMR0` to `MMR3` and any of the
 `PDR` and `PAR` registers.
 
 SimH doesn't support this behavior.
-xxdp `ekbee1` tests 61 and 63 verify this behavior and are skipped.
+xxdp program `ekbee1` tests 061 and 063 verify this behavior and are skipped
+(see [patch](../tools/xxdp/ekbee1_patch_1170.scmd)).
 
 w11 also doesn't support this behavior, this is documented as
 [w11 known difference](w11a_diff_70_mmu_trap_suppression.md).

doc/simh_diff_red_psw.md

@@ -1,6 +1,6 @@
 ## Known differences between SimH, 11/70, and w11a
 
-### SimH: Red stack zone PSW protection
+### SimH: Red stack zone `PSW` protection
 
 The 11/70 includes location 177776 in the red stack zone. This is not
 documented in the Processor Handbooks, only mentioned in the Technical
@@ -9,4 +9,8 @@ is done after an emergency stack was set up, the vector flow of a fatal
 stack errors had concluded, and the handler does a stack push when `SP`
 is still 0.
 
-SimH doesn't support this behavior. W11 does.
+SimH doesn't support this behavior.
+
+w11 implements the `PSW` protection. This is verified in a
+[tcode](../tools/tcode/README.md), the test is skipped when executed on SimH
+(see [cpu_details.mac](../tools/tcode/cpu_details.mac) test A3.2).

doc/simh_diff_service-order.md

@@ -16,6 +16,9 @@ and one after the hander exit.
 SimH uses the J11 service order with interrupts having the lowest priority for
 all PDP-11 models.
 
-The w11 implements the proper 11/70 service order.
+The w11 implements the 11/70 service order.
+This is verified in a [tcode](../tools/tcode/README.md), the test is
+skipped when executed on SimH
+(see [cpu_details.mac](../tools/tcode/cpu_details.mac) test A4.4 part 3).
 
 See also [traced `WAIT`](simh_diff_traced-wait.md).

doc/simh_diff_spl.md

@@ -9,8 +9,12 @@ a situation suitable for interrupt response testing.
 
 SimH does not implement this behavior, `SPL` behaves like all other
 instructions, and interrupts or traps are honored after it completes.
-xxdp `ekbbf0` test 32 depends on the 11/70 behavior and is skipped.
+xxdp program `ekbbf0` test 032 depends on the 11/70 behavior and is skipped
+(see [patch](../tools/xxdp/ekbbf0_patch_1170.scmd)).
 
 The w11 implements 11/70 behavior for `SPL` in kernel mode only. In supervisor
 or user mode `SPL` is a nop and honors traps and interrupts, see
 [`SPL` on w11](w11a_diff_70_spl_bug.md).
+Several [tcodes](../tools/tcode/README.md) utilize the `SPL` behavior and
+are skipped when executed on SimH
+(see [cpu_basics.mac](../tools/tcode/cpu_basics.mac) test F2.3).

doc/simh_diff_stklim_amode.md

@@ -9,7 +9,6 @@ Beyond that, the 11/70 and the J11 logic are very different
 - the 11/70 checks for writes with specifiers with mode 1, 2, 4, or 6, thus for
   - `clr  (sp)`
   - `mov  #77,(sp)+`
-  - `mov  #77,(sp)+`
   - `mov  #77,-(sp)`
   - `mov  #77,2(sp)`
 - the J11 checks for all accesses with specifiers with mode 4 and 5, thus for
@@ -21,9 +20,14 @@ The 11/70 logic focuses on that a write was done, while the J11 logic focuses
 on that the `SP` was decremented.
 
 SimH uses the J11 behavior for all models, thus also for an 11/70 simulation.  
-xxdp `ekbbf0` tests 36,40 and 42,
-`ekbee1` tests 122 and 123,
-`eqkce1` tests 41 and 65,
-depend on the 11/70 behavior and are patched or skipped.
+xxdp program `ekbbf0` tests 036, 040 and 042,
+`ekbee1` tests 122 and 123, and
+`eqkce1` tests 041 and 065
+depend on the 11/70 behavior and are patched or skipped
+(see patch for [ekbbf0](../tools/xxdp/ekbbf0_patch_1170.scmd),
+[ekbee1](../tools/xxdp/ekbee1_patch_1170.scmd), and
+[eqkce1](../tools/xxdp/eqkce1_patch_1170.scmd)).
 
-The w11 correctly implements the 11/70 behavior.
+The w11 correctly implements the 11/70 behavior. This is verified in a
+[tcode](../tools/tcode/README.md), the test is skipped when executed on SimH
+(see [cpu_details.mac](../tools/tcode/cpu_details.mac) test A3.3).

doc/simh_diff_stklim_vpush.md

@@ -16,9 +16,6 @@ writes have been performed and one or two values have been potentially written
 into the red zone. An emergency stack is set up and a vector 4 flow is started
 that will save the PS and PC values taken read in beginning of the aborted
 vector flow.
-The [tcode](../tools/tcode/README.md)
-[cpu_details](../tools/tcode/cpu_details.mac) test A3.5 verifies the 11/70
-behaviour and is skipped when executed on SimH.
 
 **Note**: The SimH behavior for vector push aborts caused by an MMU abort is
 different. These aborts are detected before the actual write, and the vector
@@ -29,3 +26,6 @@ failed and is converted to a fatal stack error. In these cases, SimH
 implements the 11/70 behavior.
 
 The w11 correctly implements the 11/70 behavior in all cases.
+This is verified in a [tcode](../tools/tcode/README.md), the tests are
+skipped when executed on SimH
+(see [cpu_details](../tools/tcode/cpu_details.mac) tests A3.4 and A3.5).

doc/simh_diff_summary.md

@@ -10,14 +10,18 @@ for all PDP-11 models, and also when `set cpu 11/70` is configured.
 
 Test codes are sometimes sensitive to those details, so the most relevant
 ones are listed here:
-- [SimH: State of N and Z and registers after a `DIV` abort with `V=1`](simh_diff_div_after_v1.md)
-- [SimH: stack limit check and addressing modes](simh_diff_stklim_amode.md)
-- [SimH: stack limit check and vector push aborts](simh_diff_stklim_vpush.md)
-- [SimH: Red stack zone PSW protection](simh_diff_red_psw.md)
-- [SimH: trap and interrupt service order has J11 behavior](simh_diff_service-order.md)
-- [SimH: traced `WAIT` has J11 behavior](simh_diff_traced-wait.md)
-- [SimH: `SPL` doesn't have 11/70 behavior](simh_diff_spl.md)
-- [SimH: MMU traps not suppressed when MMU register accessed](simh_diff_mmu_trap_suppression.md)
-- [SimH: implicit stack pops not recorded in `MMR1`](simh_diff_mmr1_rts_mtp.md)
-- [SimH: The 'instruction completed flag' in `MMR0` is not implemented](simh_diff_instruction_complete.md)
-- [SimH: MMU aborts have priority over NXM aborts](simh_diff_mmu_nxm_prio.md)
+- instruction behavior
+  - [SimH: `SPL` doesn't have 11/70 behavior](simh_diff_spl.md)
+  - [SimH: State of N and Z and registers after a `DIV` abort with `V=1`](simh_diff_div_after_v1.md)
+- stack limit and stack error behavior
+  - [SimH: stack limit check and addressing modes](simh_diff_stklim_amode.md)
+  - [SimH: stack limit check and vector push aborts](simh_diff_stklim_vpush.md)
+  - [SimH: Red stack zone PSW protection](simh_diff_red_psw.md)
+- service order and trap handling
+  - [SimH: trap and interrupt service order has J11 behavior](simh_diff_service-order.md)
+  - [SimH: traced `WAIT` has J11 behavior](simh_diff_traced-wait.md)
+- memory management behavior
+  - [SimH: `MMR1` recording has J11 behavior](simh_diff_mmr1.md)
+  - [SimH: MMU traps not suppressed when MMU register accessed](simh_diff_mmu_trap_suppression.md)
+  - [SimH: The 'instruction completed flag' in `MMR0` is not implemented](simh_diff_instruction_complete.md)
+  - [SimH: MMU aborts have priority over NXM aborts](simh_diff_mmu_nxm_prio.md)

doc/simh_diff_traced-wait.md

@@ -15,6 +15,10 @@ precedence in those models.
 SimH uses the J11 service order with interrupts having the lowest priority for
 all PDP-11 models, and consequently, a traced `WAIT` falls through and raises
 a trace trap immediately.
-xxdp `ekbbf0` test 63 verifies the 11/70 behavior and is skipped.
+xxdp program `ekbbf0` test 063 verifies the 11/70 behavior and is skipped
+(see [patch](../tools/xxdp/ekbbf0_patch_1170.scmd)).
 
-The w11 implements the proper 11/70 service order and `WAIT` behavior.
+The w11 implements the 11/70 service order and `WAIT` behavior.
+This is verified in a [tcode](../tools/tcode/README.md), the `WAIT` test is
+skipped when executed on SimH
+(see [cpu_details.mac](../tools/tcode/cpu_details.mac) test A4.4 part 4).

doc/w11a_diff_70_instruction_complete.md

@@ -18,5 +18,5 @@ w11 supports this feature, but has two implementation differences:
   decrements the `SP` twice before the 1st vector push. Therefore, after an
   MMU abort of the 1st vector push, `MMR1` has `000336` on the w11 and `173366`
   on the 11/70.
-  `ekbee1` test 067 checks this `MMR1` response and has been modified
-  (see [patch](../tools/xxdp/ekbee1_patch_w11a.tcl)).
+  xxdp program `ekbee1` test 067 checks this `MMR1` response and has been
+  modified (see [patch](../tools/xxdp/ekbee1_patch_w11a.tcl)).

doc/w11a_diff_70_mmu_stklim_prio.md

@@ -18,6 +18,6 @@ The w11 does not implement this suppression, the MMU logic and the stack limit
 check logic are independent. The case described above leads to a vector 4,
 but also sets an abort bit in `MMR0`.
 
-The `ekbee1` diagnostic tests this behavior in test 122. This test is
+The xxdp program `ekbee1` checks this behavior in test 122. This test is
 modified when executed on w11
 (see [patch](../tools/xxdp/ekbee1_patch_w11a.tcl)).

doc/w11a_known_differences.md

@@ -5,15 +5,21 @@ The issues of the w11 CPU and systems are listed in a separate document
 [README_known_issues.md](README_known_issues.md).
 
 ### Known differences between w11a and KB11-C (11/70)
-- [Instruction fetch after `SPL`](w11a_diff_70_spl_bug.md)
-- [`CLR` and `SXT` do a write](w11a_diff_70_clr_sxt_write.md)
-- [`jsr sp` pushes original `sp` value](w11a_diff_70_jsr_sp.md)
-- [Stack limit checks done independent of register set](w11a_diff_70_stklim_rset.md)
-- [18-bit UNIBUS address space not mapped](w11a_diff_70_unibus_mapping.md)
-- [`MMR0` instruction complete implementation differences](w11a_diff_70_instruction_complete.md)
-- [MMU traps not suppressed when MMU register accessed](w11a_diff_70_mmu_trap_suppression.md)
-- [MMU aborts have priority over NXM aborts](w11a_diff_70_mmu_nxm_prio.md)
-- [`MMR0` abort flags are set when stack limit abort done](w11a_diff_70_mmu_stklim_prio.md)
+- instruction behavior
+  - [Instruction fetch after `SPL`](w11a_diff_70_spl_bug.md)
+  - [`CLR` and `SXT` do a write](w11a_diff_70_clr_sxt_write.md)
+  - [`jsr sp` pushes original `sp` value](w11a_diff_70_jsr_sp.md)
+  - [State of N and Z and registers after a `DIV` abort with `V=1`](w11a_diff_70_div_after_v1.md)
+- stack limit and stack error behavior
+  - [Stack limit checks done independent of register set](w11a_diff_70_stklim_rset.md)
+- memory management behavior
+  - [`MMR0` instruction complete implementation differences](w11a_diff_70_instruction_complete.md)
+  - [MMU traps not suppressed when MMU register accessed](w11a_diff_70_mmu_trap_suppression.md)
+  - [MMU aborts have priority over NXM aborts](w11a_diff_70_mmu_nxm_prio.md)
+  - [`MMR0` abort flags are set when stack limit abort done](w11a_diff_70_mmu_stklim_prio.md)
+- other differences
+  - [18-bit UNIBUS address space not mapped](w11a_diff_70_unibus_mapping.md)
+  - [Usage of 11/70 `SYSID` register](w11a_diff_70_sysid_usage.md)
 
 All points relate to very 11/70 specific behavior, no operating system
 depends on them, therefore they are considered acceptable implementation
@@ -30,32 +36,24 @@ Also helpful are the differences sections in the manuals of for processors
 - [J-11 Programmer's Reference Rev 2.04 1982](http://www.bitsavers.org/pdf/dec/pdp11/j11/J-11_Programmers_Reference_Jan82.pdf) Section 11.0 p37 (focus on registers and instructions)
 - [KD11-E (11/34) Central Processor Manual](http://www.bitsavers.org/pdf/dec/pdp11/1134/EK-KD11E-TM-001_KD11-E_Central_Processor_Maintenance_Manual_Dec76.pdf) Table 2-8 p41
 
-### Differences in unspecified behavior between w11a and KB11-C (11/70)
-- [State of N and Z and registers after a `DIV` abort with `V=1`](w11a_diff_70_div_after_v1.md)
-
-No software should depend on the unspecified behavior of the CPU, therefore
-this is considered as an acceptable implementation difference.
-
-### Other differences between w11a and KB11-C (11/70)
-- [Usage of 11/70 `SYSID` register](w11a_diff_70_sysid_usage.md)
-
 ### <a id="lim">Known limitations</a>
 
 - some programs use timing loops based on the execution speed of the
   original processors. This can lead to spurious timeouts, especially
   in old test programs.  
-  **--> a 'CPU throttle mechanism' will be added in a future version to 
-  circumvent this for some old test codes.**
+  A 'CPU throttle mechanism' will be added in a future version to
+  circumvent this for some old test codes.
 - the emulated I/O can lead to apparently slow device reaction times,
   especially when the server runs as a normal user process. This can lead
   to a timeout, again mostly in test programs.  
-  **--> a 'watch dog' mechanism will be added in a future version which
-  suspends the CPU when the server doesn't respond fast enough.**
+  A 'watch dog' mechanism will be added in a future version which
+  suspends the CPU when the server doesn't respond fast enough.
 
 ### Known differences between Simh, e11, a real 11/70, and w11a
 The Simh and e11 simulators do not model some 11/70 details that have no
-effect on normal operation for performance reasons. Test codes, like xxdp
-diagostic programs from DEC or the tcodes of the w11 verification suite are
+effect on normal operation for performance reasons. Test codes, like
+[xxdp](../tools/xxdp/README.md) diagostic programs or the
+[tcodes](../tools/tcode/README.md) of the w11 verification suite are
 sometimes sensitive to those details, so the most relevant ones are
 listed under
 - [Known differences between SimH, 11/70, and w11a](simh_diff_summary.md)

rtl/w11a/pdp11_mmu.vhd

@@ -1,4 +1,4 @@
--- $Id: pdp11_mmu.vhd 1330 2022-12-16 17:52:40Z mueller $
+-- $Id: pdp11_mmu.vhd 1331 2022-12-18 11:55:47Z mueller $
 -- SPDX-License-Identifier: GPL-3.0-or-later
 -- Copyright 2006-2022 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
 --

rtl/w11a/pdp11_vmbox.vhd

@@ -1,4 +1,4 @@
--- $Id: pdp11_vmbox.vhd 1320 2022-11-22 18:52:59Z mueller $
+-- $Id: pdp11_vmbox.vhd 1331 2022-12-18 11:55:47Z mueller $
 -- SPDX-License-Identifier: GPL-3.0-or-later
 -- Copyright 2006-2022 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
 --

tools/tcode/README.md

@@ -10,6 +10,9 @@ The codes can be executed
 - with SimH, usually via a `load <lda-file>`, `dep pc 200`, `cont`
 - with `e11`, usually via a `mount pr: <lda-file>`, `boot pr:`
 
+The codes use the `SYSID` register to detect the execution environment,
+see [usage of `SYSID` register](../../doc/w11a_diff_70_sysid_usage.md).
+
 A [Makefile](Makefile) is provided with the targets
 ```
   make alllda           all .lda + .lst files
@@ -25,3 +28,6 @@ A [Makefile](Makefile) is provided with the targets
   make <tcode>.te11     run on e11  simulator
   make <tcode>.tw11     run on w11  GHDL simulation (for C7)
 ```
+
+The `Makefile` starts the codes with `SYSID` settings constent with the
+execution environment.

tools/tcode/cpu_details.mac

@@ -1,4 +1,4 @@
-; $Id: cpu_details.mac 1329 2022-12-11 17:28:28Z mueller $
+; $Id: cpu_details.mac 1332 2022-12-21 11:56:32Z mueller $
 ; SPDX-License-Identifier: GPL-3.0-or-later
 ; Copyright 2022- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
 ;
@@ -1207,7 +1207,7 @@ ta0404: mov     #vhtbpt,v..bpt          ; BPT handler
 ;
 3000$:  cmpb    systyp,#sy.sih          ; skip on SimH (different service order)
         beq     4000$
-        cmpb    systyp,#sy.e11          ; skip on e11 (different service order
+        cmpb    systyp,#sy.e11          ; skip on e11 (different service order)
         beq     4000$
 ;
 3001$:  mov     #3200$,r5

tools/tcode/cpu_mmu.mac

@@ -1,4 +1,4 @@
-; $Id: cpu_mmu.mac 1330 2022-12-16 17:52:40Z mueller $
+; $Id: cpu_mmu.mac 1332 2022-12-21 11:56:32Z mueller $
 ; SPDX-License-Identifier: GPL-3.0-or-later
 ; Copyright 2022- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
 ;
@@ -1442,7 +1442,7 @@ tc0205: mov     #<127.*md.plf>,kipdr5   ; page 5 non-resident (afc=0)
 ;   and a PIRQ handler in supervisor space.
 ;   Verify that PS and PC at the beginning of the failed vector flow are saved.
 ;   Test inspired by ekbee1 test 124.
-;   Verify also that MMR0,MMR2 instruction complete (unless on SimH)
+;   Verify also MMR0,MMR2 instruction complete response (unless on SimH)
 ;
 tc0206: mov     kipdr0,sipdr0           ; super page 0 1-to-1
         mov     kipar0,sipar0