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added preliminary and FPFA untested(!) support for nexys4 DDR board

Browse Source 
- rtl/bplib/nexys4d: added board support
- rtl/sys_gen
  - tst_rlink/nexys4d: rlink tester design
  - tst_serloop/nexys4d: serial port tester design
  - tst_snhumanio/nexys4d: human IO tester design
  - w11a/nexys4d_bram: w11 design using BRAM only
This commit is contained in:
Walter F.J. Mueller
2017-01-04 22:12:29 +01:00
parent b2e7c1cdbb
commit 0e96fa106b
66 changed files with 3670 additions and 5 deletions
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8
doc/CHANGELOG.md
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@@ -10,9 +10,17 @@
<!-- --------------------------------------------------------------------- -->
---
## HEAD <a name="head"></a>
### Proviso
_The HEAD version is shows the current development. No guarantees that
software or firmware builds or that the documentation is consistent.
The full set of tests is only run for releases._
### Summary
- [w11 shell](../tools/tcl/rw11/shell.tcl) re-organized abd expanded,
now default in [ti_w11](../tools/bin/ti_w11)
- `CPUERR` cleared with cpu reset (see [ECO-029](ECO-029-cpuerr_creset.md))
- `PS` initialized now with `000000` (see [ECO-028](ECO-028-ps_init.md))
- added **preliminary** and **FPGA untested** support for nexys4 DDR
<!-- --------------------------------------------------------------------- -->
---