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added preliminary and FPFA untested(!) support for nexys4 DDR board

Browse Source 
- rtl/bplib/nexys4d: added board support
- rtl/sys_gen
  - tst_rlink/nexys4d: rlink tester design
  - tst_serloop/nexys4d: serial port tester design
  - tst_snhumanio/nexys4d: human IO tester design
  - w11a/nexys4d_bram: w11 design using BRAM only
This commit is contained in:
Walter F.J. Mueller
2017-01-04 22:12:29 +01:00
parent b2e7c1cdbb
commit 0e96fa106b
66 changed files with 3670 additions and 5 deletions
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13
rtl/bplib/nexys4d/nexys4d_pclk.xdc Normal file
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# $Id: nexys4d_pclk.xdc 838 2017-01-04 20:57:57Z mueller $
#
# Copyright 2017- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
# License disclaimer see License.txt in $RETROBASE directory
#
# Primary clocks for Nexys4 DDR
#
# Revision History:
# Date Rev Version Comment
# 2017-01-04 838 1.0 Initial version
#
create_clock -name I_CLK100 -period 10 -waveform {0 5} [get_ports I_CLK100]

138
rtl/bplib/nexys4d/nexys4d_pins.xdc Normal file
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# -*- tcl -*-
# $Id: nexys4d_pins.xdc 838 2017-01-04 20:57:57Z mueller $
#
# Copyright 2017- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
# License disclaimer see License.txt in $RETROBASE directory
#
# Nexys 4DDR core functionality
# - Configuration setup
# - config voltage
# - enable bitstream timestamp
# - Pin Locks for
# - USB UART
# - human I/O (switches, buttons, leds, display)
#
# Revision History:
# Date Rev Version Comment
# 2017-01-04 838 1.0 Initial version
#
# config setup --------------------------------------------------------------
set_property CFGBVS VCCO [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property BITSTREAM.CONFIG.USR_ACCESS TIMESTAMP [current_design]
# clocks -- in bank 35 ------------------------------------------------------
set_property PACKAGE_PIN e3 [get_ports {I_CLK100}]
set_property IOSTANDARD LVCMOS33 [get_ports {I_CLK100}]
#
# USB UART Interface -- in bank 35 ------------------------------------------
set_property PACKAGE_PIN c4 [get_ports {I_RXD}]
set_property PACKAGE_PIN d4 [get_ports {O_TXD}]
set_property PACKAGE_PIN d3 [get_ports {O_RTS_N}]
set_property PACKAGE_PIN e5 [get_ports {I_CTS_N}]
set_property IOSTANDARD LVCMOS33 [get_ports {I_RXD O_TXD O_RTS_N I_CTS_N}]
set_property DRIVE 12 [get_ports {O_TXD O_RTS_N}]
set_property SLEW SLOW [get_ports {O_TXD O_RTS_N}]
#
# switches -- in bank 14+15 -------------------------------------------------
set_property PACKAGE_PIN j15 [get_ports {I_SWI[0]}]
set_property PACKAGE_PIN l16 [get_ports {I_SWI[1]}]
set_property PACKAGE_PIN m13 [get_ports {I_SWI[2]}]
set_property PACKAGE_PIN r15 [get_ports {I_SWI[3]}]
set_property PACKAGE_PIN r17 [get_ports {I_SWI[4]}]
set_property PACKAGE_PIN t18 [get_ports {I_SWI[5]}]
set_property PACKAGE_PIN u18 [get_ports {I_SWI[6]}]
set_property PACKAGE_PIN r13 [get_ports {I_SWI[7]}]
set_property PACKAGE_PIN t8 [get_ports {I_SWI[8]}]
set_property PACKAGE_PIN u8 [get_ports {I_SWI[9]}]
set_property PACKAGE_PIN r16 [get_ports {I_SWI[10]}]
set_property PACKAGE_PIN t13 [get_ports {I_SWI[11]}]
set_property PACKAGE_PIN h6 [get_ports {I_SWI[12]}]
set_property PACKAGE_PIN u12 [get_ports {I_SWI[13]}]
set_property PACKAGE_PIN u11 [get_ports {I_SWI[14]}]
set_property PACKAGE_PIN v10 [get_ports {I_SWI[15]}]
set_property IOSTANDARD LVCMOS33 [get_ports {I_SWI[*]}]
#
# buttons -- in bank 14+15 --------------------------------------------------
# sequence: clockwise(U-R-D-L) - middle - reset
set_property PACKAGE_PIN m18 [get_ports {I_BTN[0]}]
set_property PACKAGE_PIN m17 [get_ports {I_BTN[1]}]
set_property PACKAGE_PIN p18 [get_ports {I_BTN[2]}]
set_property PACKAGE_PIN p17 [get_ports {I_BTN[3]}]
set_property PACKAGE_PIN n17 [get_ports {I_BTN[4]}]
set_property PACKAGE_PIN c12 [get_ports {I_BTNRST_N}]
set_property IOSTANDARD LVCMOS33 [get_ports {I_BTN[*]}]
set_property IOSTANDARD LVCMOS33 [get_ports {I_BTNRST_N}]
#
# LEDs -- in bank 14+15------------------------------------------------------
set_property PACKAGE_PIN h17 [get_ports {O_LED[0]}]
set_property PACKAGE_PIN k15 [get_ports {O_LED[1]}]
set_property PACKAGE_PIN j13 [get_ports {O_LED[2]}]
set_property PACKAGE_PIN n14 [get_ports {O_LED[3]}]
set_property PACKAGE_PIN r18 [get_ports {O_LED[4]}]
set_property PACKAGE_PIN v17 [get_ports {O_LED[5]}]
set_property PACKAGE_PIN u17 [get_ports {O_LED[6]}]
set_property PACKAGE_PIN u16 [get_ports {O_LED[7]}]
set_property PACKAGE_PIN v16 [get_ports {O_LED[8]}]
set_property PACKAGE_PIN t15 [get_ports {O_LED[9]}]
set_property PACKAGE_PIN u14 [get_ports {O_LED[10]}]
set_property PACKAGE_PIN t16 [get_ports {O_LED[11]}]
set_property PACKAGE_PIN v15 [get_ports {O_LED[12]}]
set_property PACKAGE_PIN v14 [get_ports {O_LED[13]}]
set_property PACKAGE_PIN v12 [get_ports {O_LED[14]}]
set_property PACKAGE_PIN v11 [get_ports {O_LED[15]}]
set_property IOSTANDARD LVCMOS33 [get_ports {O_LED[*]}]
set_property DRIVE 12 [get_ports {O_LED[*]}]
set_property SLEW SLOW [get_ports {O_LED[*]}]
#
# RGB-LEDs -- in bank 14+15 -------------------------------------------------
set_property PACKAGE_PIN n15 [get_ports {O_RGBLED0[0]}]
set_property PACKAGE_PIN m16 [get_ports {O_RGBLED0[1]}]
set_property PACKAGE_PIN r12 [get_ports {O_RGBLED0[2]}]
set_property PACKAGE_PIN n16 [get_ports {O_RGBLED1[0]}]
set_property PACKAGE_PIN r11 [get_ports {O_RGBLED1[1]}]
set_property PACKAGE_PIN g14 [get_ports {O_RGBLED1[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {O_RGBLED0[*] O_RGBLED1[*]}]
set_property DRIVE 12 [get_ports {O_RGBLED0[*] O_RGBLED1[*]}]
set_property SLEW SLOW [get_ports {O_RGBLED0[*] O_RGBLED1[*]}]
#
# 7 segment display -- in bank 14+15-----------------------------------------
set_property PACKAGE_PIN j17 [get_ports {O_ANO_N[0]}]
set_property PACKAGE_PIN j18 [get_ports {O_ANO_N[1]}]
set_property PACKAGE_PIN t9 [get_ports {O_ANO_N[2]}]
set_property PACKAGE_PIN j14 [get_ports {O_ANO_N[3]}]
set_property PACKAGE_PIN p14 [get_ports {O_ANO_N[4]}]
set_property PACKAGE_PIN t14 [get_ports {O_ANO_N[5]}]
set_property PACKAGE_PIN k2 [get_ports {O_ANO_N[6]}]
set_property PACKAGE_PIN u13 [get_ports {O_ANO_N[7]}]
set_property IOSTANDARD LVCMOS33 [get_ports {O_ANO_N[*]}]
set_property DRIVE 12 [get_ports {O_ANO_N[*]}]
set_property SLEW SLOW [get_ports {O_ANO_N[*]}]
#
set_property PACKAGE_PIN t10 [get_ports {O_SEG_N[0]}]
set_property PACKAGE_PIN r10 [get_ports {O_SEG_N[1]}]
set_property PACKAGE_PIN k16 [get_ports {O_SEG_N[2]}]
set_property PACKAGE_PIN k13 [get_ports {O_SEG_N[3]}]
set_property PACKAGE_PIN p15 [get_ports {O_SEG_N[4]}]
set_property PACKAGE_PIN t11 [get_ports {O_SEG_N[5]}]
set_property PACKAGE_PIN l18 [get_ports {O_SEG_N[6]}]
set_property PACKAGE_PIN h15 [get_ports {O_SEG_N[7]}]
set_property IOSTANDARD LVCMOS33 [get_ports {O_SEG_N[*]}]
set_property DRIVE 12 [get_ports {O_SEG_N[*]}]
set_property SLEW SLOW [get_ports {O_SEG_N[*]}]
#

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rtl/bplib/nexys4d/nexys4dlib.vhd Normal file
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-- $Id: nexys4dlib.vhd 838 2017-01-04 20:57:57Z mueller $
--
-- Copyright 2017- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Package Name: nexys4dlib
-- Description: Nexys 4DDR components
--
-- Dependencies: -
-- Tool versions: viv 2016.2; ghdl 0.33
--
-- Revision History:
-- Date Rev Version Comment
-- 2017-01-04 838 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package nexys4dlib is
component nexys4d_aif is -- NEXYS 4D, abstract iface, base
port (
I_CLK100 : in slbit; -- 100 MHz clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
O_RTS_N : out slbit; -- rx rts (board view; act.low)
I_CTS_N : in slbit; -- tx cts (board view; act.low)
I_SWI : in slv16; -- n4 switches
I_BTN : in slv5; -- n4 buttons
I_BTNRST_N : in slbit; -- n4 reset button
O_LED : out slv16; -- n4 leds
O_RGBLED0 : out slv3; -- n4 rgb-led 0
O_RGBLED1 : out slv3; -- n4 rgb-led 1
O_ANO_N : out slv8; -- 7 segment disp: anodes (act.low)
O_SEG_N : out slv8 -- 7 segment disp: segments (act.low)
);
end component;
end package nexys4dlib;

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rtl/bplib/nexys4d/tb/Makefile Normal file
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# $Id: Makefile 838 2017-01-04 20:57:57Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2017-01-04 838 1.0 Initial version
#
EXE_all = tb_nexys4d_dummy
#
include ${RETROBASE}/rtl/make_viv/viv_default_nexys4d.mk
#
.PHONY : all all_ssim all_osim clean
.PHONY : all_XSim all_XSim_ssim all_XSim_osim all_XSim_tsim
#
all : $(EXE_all)
all_ssim : $(EXE_all:=_ssim)
all_osim : $(EXE_all:=_osim)
#
all_XSim : $(EXE_all:=_XSim)
all_XSim_ssim : $(EXE_all:=_XSim_ssim)
all_XSim_osim : $(EXE_all:=_XSim_osim)
all_XSim_tsim : $(EXE_all:=_XSim_tsim)
#
clean : viv_clean ghdl_clean xsim_clean
#
#-----
#
include ${RETROBASE}/rtl/make_viv/generic_ghdl.mk
include ${RETROBASE}/rtl/make_viv/generic_xsim.mk
include ${RETROBASE}/rtl/make_viv/generic_vivado.mk
#
VBOM_all = $(wildcard *.vbom)
#
ifndef DONTINCDEP
include $(VBOM_all:.vbom=.dep_vsyn)
include $(VBOM_all:.vbom=.dep_ghdl)
include $(VBOM_all:.vbom=.dep_vsim)
include $(wildcard *.o.dep_ghdl)
endif
#

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rtl/bplib/nexys4d/tb/nexys4d_dummy.vbom Normal file
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# libs
../../../vlib/slvtypes.vhd
# design
nexys4d_dummy.vhd

67
rtl/bplib/nexys4d/tb/nexys4d_dummy.vhd Normal file
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-- $Id: nexys4d_dummy.vhd 838 2017-01-04 20:57:57Z mueller $
--
-- Copyright 2017- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: nexys4d_dummy - syn
-- Description: nexys4d minimal target (base; serport loopback)
--
-- Dependencies: -
-- To test: tb_nexys4d
-- Target Devices: generic
-- Tool versions: viv 2016.4; ghdl 0.33
--
-- Revision History:
-- Date Rev Version Comment
-- 2017-01-04 838 1.0 Initial version (derived from nexys4_dummy)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
entity nexys4d_dummy is -- NEXYS 4DDR dummy (base; loopback)
-- implements nexys4d_aif
port (
I_CLK100 : in slbit; -- 100 MHz board clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
O_RTS_N : out slbit; -- rx rts (board view; act.low)
I_CTS_N : in slbit; -- tx cts (board view; act.low)
I_SWI : in slv16; -- n4d switches
I_BTN : in slv5; -- n4d buttons
I_BTNRST_N : in slbit; -- n4d reset button
O_LED : out slv16; -- n4d leds
O_RGBLED0 : out slv3; -- n4d rgb-led 0
O_RGBLED1 : out slv3; -- n4d rgb-led 1
O_ANO_N : out slv8; -- 7 segment disp: anodes (act.low)
O_SEG_N : out slv8 -- 7 segment disp: segments (act.low)
);
end nexys4d_dummy;
architecture syn of nexys4d_dummy is
begin
O_TXD <= I_RXD; -- loop back serport
O_RTS_N <= I_CTS_N;
O_LED <= I_SWI; -- mirror SWI on LED
O_RGBLED0 <= I_BTN(2 downto 0); -- mirror BTN on RGBLED
O_RGBLED1 <= not I_BTNRST_N & I_BTN(4) & I_BTN(3);
O_ANO_N <= (others=>'1');
O_SEG_N <= (others=>'1');
end syn;

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rtl/bplib/nexys4d/tb/sys_conf_sim.vhd Normal file
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-- $Id: sys_conf_sim.vhd 838 2017-01-04 20:57:57Z mueller $
--
-- Copyright 2017- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for tb_nexys4d_dummy (for simulation)
--
-- Dependencies: -
-- Tool versions: viv 2016.2; ghdl 0.33
-- Revision History:
-- Date Rev Version Comment
-- 2017-01-04 838 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package sys_conf is
constant sys_conf_clksys_vcodivide : positive := 1;
constant sys_conf_clksys_vcomultiply : positive := 8; -- vco 800 MHz
constant sys_conf_clksys_outdivide : positive := 10; -- sys 80 MHz
constant sys_conf_clksys_gentype : string := "MMCM";
constant sys_conf_clkser_vcodivide : positive := 1;
constant sys_conf_clkser_vcomultiply : positive := 12; -- vco 1200 MHz
constant sys_conf_clkser_outdivide : positive := 10; -- sys 120 MHz
constant sys_conf_clkser_gentype : string := "MMCM";
-- derived constants
constant sys_conf_clksys : integer :=
((100000000/sys_conf_clksys_vcodivide)*sys_conf_clksys_vcomultiply) /
sys_conf_clksys_outdivide;
constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000;
constant sys_conf_clkser : integer :=
((100000000/sys_conf_clkser_vcodivide)*sys_conf_clkser_vcomultiply) /
sys_conf_clkser_outdivide;
constant sys_conf_clkser_mhz : integer := sys_conf_clkser/1000000;
end package sys_conf;

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rtl/bplib/nexys4d/tb/tb_nexys4d.vbom Normal file
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# Not meant for direct top level usage. Used with
# tb_nexys4d_(....)[_ssim].vbom and config
# lines to generate the different cases.
#
# libs
../../../vlib/slvtypes.vhd
../../../vlib/rlink/rlinklib.vbom
../../../vlib/xlib/xlib.vhd
../nexys4dlib.vhd
../../../vlib/simlib/simlib.vhd
../../../vlib/simlib/simbus.vhd
${sys_conf := sys_conf_sim.vhd}
# components
../../../vlib/simlib/simclk.vbom
../../../vlib/simlib/simclkcnt.vbom
../../../vlib/rlink/tbcore/tbcore_rlink.vbom
../../../vlib/xlib/tb/s7_cmt_sfs_tb.vbom
tb_nexys4d_core.vbom
../../../vlib/serport/tb/serport_master_tb.vbom
${nexys4d_aif := nexys4d_dummy.vbom} -UUT
# design
tb_nexys4d.vhd
@top:tb_nexys4d

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rtl/bplib/nexys4d/tb/tb_nexys4d.vhd Normal file
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-- $Id: tb_nexys4d.vhd 838 2017-01-04 20:57:57Z mueller $
--
-- Copyright 2017- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: tb_nexys4d - sim
-- Description: Test bench for nexys4d (base)
--
-- Dependencies: simlib/simclk
-- simlib/simclkcnt
-- rlink/tbcore/tbcore_rlink
-- xlib/tb/s7_cmt_sfs_tb
-- tb_nexys4d_core
-- serport/tb/serport_master_tb
-- nexys4d_aif [UUT]
--
-- To test: generic, any nexys4d_aif target
--
-- Target Devices: generic
-- Tool versions: viv 2016.2; ghdl 0.33
--
-- Revision History:
-- Date Rev Version Comment
-- 2017-01-04 838 1.0 Initial version (derived from tb_nexys4)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
use work.rlinklib.all;
use work.xlib.all;
use work.nexys4dlib.all;
use work.simlib.all;
use work.simbus.all;
use work.sys_conf.all;
entity tb_nexys4d is
end tb_nexys4d;
architecture sim of tb_nexys4d is
signal CLKOSC : slbit := '0'; -- board clock (100 Mhz)
signal CLKCOM : slbit := '0'; -- communication clock
signal CLKCOM_CYCLE : integer := 0;
signal RESET : slbit := '0';
signal CLKDIV : slv2 := "00"; -- run with 1 clocks / bit !!
signal RXDATA : slv8 := (others=>'0');
signal RXVAL : slbit := '0';
signal RXERR : slbit := '0';
signal RXACT : slbit := '0';
signal TXDATA : slv8 := (others=>'0');
signal TXENA : slbit := '0';
signal TXBUSY : slbit := '0';
signal I_RXD : slbit := '1';
signal O_TXD : slbit := '1';
signal O_RTS_N : slbit := '0';
signal I_CTS_N : slbit := '0';
signal I_SWI : slv16 := (others=>'0');
signal I_BTN : slv5 := (others=>'0');
signal I_BTNRST_N : slbit := '1';
signal O_LED : slv16 := (others=>'0');
signal O_RGBLED0 : slv3 := (others=>'0');
signal O_RGBLED1 : slv3 := (others=>'0');
signal O_ANO_N : slv8 := (others=>'0');
signal O_SEG_N : slv8 := (others=>'0');
signal R_PORTSEL_XON : slbit := '0'; -- if 1 use xon/xoff
constant sbaddr_portsel: slv8 := slv(to_unsigned( 8,8));
constant clock_period : Delay_length := 10 ns;
constant clock_offset : Delay_length := 200 ns;
begin
CLKGEN : simclk
generic map (
PERIOD => clock_period,
OFFSET => clock_offset)
port map (
CLK => CLKOSC
);
CLKGEN_COM : entity work.s7_cmt_sfs_tb
generic map (
VCO_DIVIDE => sys_conf_clkser_vcodivide,
VCO_MULTIPLY => sys_conf_clkser_vcomultiply,
OUT_DIVIDE => sys_conf_clkser_outdivide,
CLKIN_PERIOD => 10.0,
CLKIN_JITTER => 0.01,
STARTUP_WAIT => false,
GEN_TYPE => sys_conf_clkser_gentype)
port map (
CLKIN => CLKOSC,
CLKFX => CLKCOM,
LOCKED => open
);
CLKCNT : simclkcnt port map (CLK => CLKCOM, CLK_CYCLE => CLKCOM_CYCLE);
TBCORE : entity work.tbcore_rlink
port map (
CLK => CLKCOM,
RX_DATA => TXDATA,
RX_VAL => TXENA,
RX_HOLD => TXBUSY,
TX_DATA => RXDATA,
TX_ENA => RXVAL
);
N4CORE : entity work.tb_nexys4d_core
port map (
I_SWI => I_SWI,
I_BTN => I_BTN,
I_BTNRST_N => I_BTNRST_N
);
UUT : nexys4d_aif
port map (
I_CLK100 => CLKOSC,
I_RXD => I_RXD,
O_TXD => O_TXD,
O_RTS_N => O_RTS_N,
I_CTS_N => I_CTS_N,
I_SWI => I_SWI,
I_BTN => I_BTN,
I_BTNRST_N => I_BTNRST_N,
O_LED => O_LED,
O_RGBLED0 => O_RGBLED0,
O_RGBLED1 => O_RGBLED1,
O_ANO_N => O_ANO_N,
O_SEG_N => O_SEG_N
);
SERMSTR : entity work.serport_master_tb
generic map (
CDWIDTH => CLKDIV'length)
port map (
CLK => CLKCOM,
RESET => RESET,
CLKDIV => CLKDIV,
ENAXON => R_PORTSEL_XON,
ENAESC => '0',
RXDATA => RXDATA,
RXVAL => RXVAL,
RXERR => RXERR,
RXOK => '1',
TXDATA => TXDATA,
TXENA => TXENA,
TXBUSY => TXBUSY,
RXSD => O_TXD,
TXSD => I_RXD,
RXRTS_N => I_CTS_N,
TXCTS_N => O_RTS_N
);
proc_moni: process
variable oline : line;
begin
loop
wait until rising_edge(CLKCOM);
if RXERR = '1' then
writetimestamp(oline, CLKCOM_CYCLE, " : seen RXERR=1");
writeline(output, oline);
end if;
end loop;
end process proc_moni;
proc_simbus: process (SB_VAL)
begin
if SB_VAL'event and to_x01(SB_VAL)='1' then
if SB_ADDR = sbaddr_portsel then
R_PORTSEL_XON <= to_x01(SB_DATA(1));
end if;
end if;
end process proc_simbus;
end sim;

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rtl/bplib/nexys4d/tb/tb_nexys4d_core.vbom Normal file
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# libs
../../../vlib/slvtypes.vhd
../../../vlib/simlib/simbus.vhd
# components
# design
tb_nexys4d_core.vhd

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-- $Id: tb_nexys4d_core.vhd 838 2017-01-04 20:57:57Z mueller $
--
-- Copyright 2017- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: tb_nexys4d_core - sim
-- Description: Test bench for nexys4d - core device handling
--
-- Dependencies: -
--
-- To test: generic, any nexys4d target
--
-- Target Devices: generic
-- Tool versions: viv 2016.2; ghdl 0.33
-- Revision History:
-- Date Rev Version Comment
-- 2017-01-04 834 1.0 Initial version (derived from tb_nexys4_core)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
use work.simbus.all;
entity tb_nexys4d_core is
port (
I_SWI : out slv16; -- n4d switches
I_BTN : out slv5; -- n4d buttons
I_BTNRST_N : out slbit -- n4d reset button
);
end tb_nexys4d_core;
architecture sim of tb_nexys4d_core is
signal R_SWI : slv16 := (others=>'0');
signal R_BTN : slv5 := (others=>'0');
signal R_BTNRST : slbit := '0';
constant sbaddr_swi: slv8 := slv(to_unsigned( 16,8));
constant sbaddr_btn: slv8 := slv(to_unsigned( 17,8));
begin
proc_simbus: process (SB_VAL)
begin
if SB_VAL'event and to_x01(SB_VAL)='1' then
if SB_ADDR = sbaddr_swi then
R_SWI <= to_x01(SB_DATA(R_SWI'range));
end if;
if SB_ADDR = sbaddr_btn then
R_BTN <= to_x01(SB_DATA(R_BTN'range));
R_BTNRST <= to_x01(SB_DATA(5));
end if;
end if;
end process proc_simbus;
I_SWI <= R_SWI;
I_BTN <= R_BTN;
I_BTNRST_N <= not R_BTNRST;
end sim;