SPDX: *.xdc

2026-02-27 01:19:57 +00:00 · 2019-07-26 18:03:23 +02:00
parent 87b21f8aa3
commit 0ebc1c7403
19 changed files with 41 additions and 55 deletions
--- a/rtl/bplib/arty/arty_pclk.xdc
+++ b/rtl/bplib/arty/arty_pclk.xdc
@@ -1,8 +1,7 @@
 # -*- tcl -*-
-# $Id: arty_pclk.xdc 830 2016-12-26 20:25:49Z mueller $
-#
+# $Id: arty_pclk.xdc 1190 2019-07-13 17:05:39Z mueller $
+# SPDX-License-Identifier: GPL-3.0-or-later
 # Copyright 2016- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-# License disclaimer see License.txt in $RETROBASE directory
 #
 # Primary clocks for Digilent Arty
 #
--- a/rtl/bplib/arty/arty_pins.xdc
+++ b/rtl/bplib/arty/arty_pins.xdc
@@ -1,8 +1,7 @@
 # -*- tcl -*-
-# $Id: arty_pins.xdc 830 2016-12-26 20:25:49Z mueller $
-#
+# $Id: arty_pins.xdc 1190 2019-07-13 17:05:39Z mueller $
+# SPDX-License-Identifier: GPL-3.0-or-later
 # Copyright 2016- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-# License disclaimer see License.txt in $RETROBASE directory
 #
 # Digilent Arty core functionality
 # - Configuration setup
--- a/rtl/bplib/artys7/artys7_pclk.xdc
+++ b/rtl/bplib/artys7/artys7_pclk.xdc
@@ -1,8 +1,7 @@
 # -*- tcl -*-
-# $Id: artys7_pclk.xdc 1038 2018-08-11 12:39:52Z mueller $
-#
+# $Id: artys7_pclk.xdc 1190 2019-07-13 17:05:39Z mueller $
+# SPDX-License-Identifier: GPL-3.0-or-later
 # Copyright 2018- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-# License disclaimer see License.txt in $RETROBASE directory
 #
 # Primary clocks for Digilent Arty
 #
--- a/rtl/bplib/artys7/artys7_pins.xdc
+++ b/rtl/bplib/artys7/artys7_pins.xdc
@@ -1,8 +1,7 @@
 # -*- tcl -*-
-# $Id: artys7_pins.xdc 1038 2018-08-11 12:39:52Z mueller $
-#
+# $Id: artys7_pins.xdc 1190 2019-07-13 17:05:39Z mueller $
+# SPDX-License-Identifier: GPL-3.0-or-later
 # Copyright 2018- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-# License disclaimer see License.txt in $RETROBASE directory
 #
 # Digilent Arty core functionality
 # - Configuration setup
--- a/rtl/bplib/basys3/basys3_pclk.xdc
+++ b/rtl/bplib/basys3/basys3_pclk.xdc
@@ -1,8 +1,7 @@
 # -*- tcl -*-
-# $Id: basys3_pclk.xdc 830 2016-12-26 20:25:49Z mueller $
-#
+# $Id: basys3_pclk.xdc 1190 2019-07-13 17:05:39Z mueller $
+# SPDX-License-Identifier: GPL-3.0-or-later
 # Copyright 2015- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-# License disclaimer see License.txt in $RETROBASE directory
 #
 # Primary clocks for Digilent Basys3
 #
--- a/rtl/bplib/basys3/basys3_pins.xdc
+++ b/rtl/bplib/basys3/basys3_pins.xdc
@@ -1,8 +1,7 @@
 # -*- tcl -*-
-# $Id: basys3_pins.xdc 830 2016-12-26 20:25:49Z mueller $
-#
+# $Id: basys3_pins.xdc 1190 2019-07-13 17:05:39Z mueller $
+# SPDX-License-Identifier: GPL-3.0-or-later
 # Copyright 2015-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-# License disclaimer see License.txt in $RETROBASE directory
 #
 # Digilent Basys 3 core functionality
 # - Configuration setup
--- a/rtl/bplib/cmoda7/cmoda7_pclk.xdc
+++ b/rtl/bplib/cmoda7/cmoda7_pclk.xdc
@@ -1,8 +1,7 @@
 # -*- tcl -*-
-# $Id: cmoda7_pclk.xdc 906 2017-06-04 21:59:13Z mueller $
-#
+# $Id: cmoda7_pclk.xdc 1190 2019-07-13 17:05:39Z mueller $
+# SPDX-License-Identifier: GPL-3.0-or-later
 # Copyright 2017- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-# License disclaimer see License.txt in $RETROBASE directory
 #
 # Primary clocks for Digilent CmodA7
 #
--- a/rtl/bplib/cmoda7/cmoda7_pins.xdc
+++ b/rtl/bplib/cmoda7/cmoda7_pins.xdc
@@ -1,8 +1,7 @@
 # -*- tcl -*-
-# $Id: cmoda7_pins.xdc 906 2017-06-04 21:59:13Z mueller $
-#
+# $Id: cmoda7_pins.xdc 1190 2019-07-13 17:05:39Z mueller $
+# SPDX-License-Identifier: GPL-3.0-or-later
 # Copyright 2017- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-# License disclaimer see License.txt in $RETROBASE directory
 #
 # Digilent CmodA7 core functionality
 # - Configuration setup
--- a/rtl/bplib/cmoda7/cmoda7_pins_sram.xdc
+++ b/rtl/bplib/cmoda7/cmoda7_pins_sram.xdc
@@ -1,8 +1,7 @@
 # -*- tcl -*-
-# $Id: cmoda7_pins_sram.xdc 906 2017-06-04 21:59:13Z mueller $
-#
+# $Id: cmoda7_pins_sram.xdc 1190 2019-07-13 17:05:39Z mueller $
+# SPDX-License-Identifier: GPL-3.0-or-later
 # Copyright 2017- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-# License disclaimer see License.txt in $RETROBASE directory
 #
 # Pin locks for CmodA7 sram
 #
--- a/rtl/bplib/nexys4/nexys4_pclk.xdc
+++ b/rtl/bplib/nexys4/nexys4_pclk.xdc
@@ -1,7 +1,7 @@
-# $Id: nexys4_pclk.xdc 830 2016-12-26 20:25:49Z mueller $
-#
+# -*- tcl -*-
+# $Id: nexys4_pclk.xdc 1190 2019-07-13 17:05:39Z mueller $
+# SPDX-License-Identifier: GPL-3.0-or-later
 # Copyright 2015- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-# License disclaimer see License.txt in $RETROBASE directory
 #
 # Primary clocks for Nexys4
 #
--- a/rtl/bplib/nexys4/nexys4_pins.xdc
+++ b/rtl/bplib/nexys4/nexys4_pins.xdc
@@ -1,8 +1,7 @@
 # -*- tcl -*-
-# $Id: nexys4_pins.xdc 830 2016-12-26 20:25:49Z mueller $
-#
+# $Id: nexys4_pins.xdc 1190 2019-07-13 17:05:39Z mueller $
+# SPDX-License-Identifier: GPL-3.0-or-later
 # Copyright 2015-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-# License disclaimer see License.txt in $RETROBASE directory
 #
 # Nexys 4 core functionality
 # - Configuration setup
--- a/rtl/bplib/nexys4/nexys4_pins_cram.xdc
+++ b/rtl/bplib/nexys4/nexys4_pins_cram.xdc
@@ -1,5 +1,7 @@
 # -*- tcl -*-
-# $Id: nexys4_pins_cram.xdc 643 2015-02-07 17:41:53Z mueller $
+# $Id: nexys4_pins_cram.xdc 1190 2019-07-13 17:05:39Z mueller $
+# SPDX-License-Identifier: GPL-3.0-or-later
+# Copyright 2015- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
 #
 # Pin locks for Nexys 4 cram
 #
--- a/rtl/bplib/nexys4d/nexys4d_pclk.xdc
+++ b/rtl/bplib/nexys4d/nexys4d_pclk.xdc
@@ -1,7 +1,7 @@
-# $Id: nexys4d_pclk.xdc 838 2017-01-04 20:57:57Z mueller $
-#
+# -*- tcl -*-
+# $Id: nexys4d_pclk.xdc 1190 2019-07-13 17:05:39Z mueller $
+# SPDX-License-Identifier: GPL-3.0-or-later
 # Copyright 2017- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-# License disclaimer see License.txt in $RETROBASE directory
 #
 # Primary clocks for Nexys4 DDR
 #
--- a/rtl/bplib/nexys4d/nexys4d_pins.xdc
+++ b/rtl/bplib/nexys4d/nexys4d_pins.xdc
@@ -1,8 +1,7 @@
 # -*- tcl -*-
-# $Id: nexys4d_pins.xdc 1099 2018-12-31 09:07:36Z mueller $
-#
+# $Id: nexys4d_pins.xdc 1190 2019-07-13 17:05:39Z mueller $
+# SPDX-License-Identifier: GPL-3.0-or-later
 # Copyright 2017-2018 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-# License disclaimer see License.txt in $RETROBASE directory
 #
 # Nexys 4DDR core functionality
 # - Configuration setup
--- a/rtl/vlib/cdclib/cdc_pulse.xdc
+++ b/rtl/vlib/cdclib/cdc_pulse.xdc
@@ -1,8 +1,7 @@
 # -*- tcl -*-
-# $Id: cdc_pulse.xdc 830 2016-12-26 20:25:49Z mueller $
-#
+# $Id: cdc_pulse.xdc 1190 2019-07-13 17:05:39Z mueller $
+# SPDX-License-Identifier: GPL-3.0-or-later
 # Copyright 2016- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-# License disclaimer see License.txt in $RETROBASE directory
 #
 # cdc constraints for cdc_pulse
 #
--- a/rtl/vlib/cdclib/cdc_signal_s1.xdc
+++ b/rtl/vlib/cdclib/cdc_signal_s1.xdc
@@ -1,8 +1,7 @@
 # -*- tcl -*-
-# $Id: cdc_signal_s1.xdc 830 2016-12-26 20:25:49Z mueller $
-#
+# $Id: cdc_signal_s1.xdc 1190 2019-07-13 17:05:39Z mueller $
+# SPDX-License-Identifier: GPL-3.0-or-later
 # Copyright 2016- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-# License disclaimer see License.txt in $RETROBASE directory
 #
 # cdc constraints for cdc_signal_s1
 #
--- a/rtl/vlib/cdclib/cdc_vector_s0.xdc
+++ b/rtl/vlib/cdclib/cdc_vector_s0.xdc
@@ -1,8 +1,7 @@
 # -*- tcl -*-
-# $Id: cdc_vector_s0.xdc 1101 2019-01-02 21:22:37Z mueller $
-#
+# $Id: cdc_vector_s0.xdc 1190 2019-07-13 17:05:39Z mueller $
+# SPDX-License-Identifier: GPL-3.0-or-later
 # Copyright 2016-2019 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-# License disclaimer see License.txt in $RETROBASE directory
 #
 # cdc constraints for cdc_vector_s0
 #
--- a/rtl/vlib/generic_clk_100mhz.xdc
+++ b/rtl/vlib/generic_clk_100mhz.xdc
@@ -1,8 +1,7 @@
 # -*- tcl -*-
-# $Id: generic_clk_100mhz.xdc 830 2016-12-26 20:25:49Z mueller $
-#
+# $Id: generic_clk_100mhz.xdc 1190 2019-07-13 17:05:39Z mueller $
+# SPDX-License-Identifier: GPL-3.0-or-later
 # Copyright 2016- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-# License disclaimer see License.txt in $RETROBASE directory
 #
 # Generic constraint for pin CLK with a 100 MHz clock
 # Helpful for test benches and generic test synthesis
--- a/rtl/vlib/memlib/fifo_2c_dram2.xdc
+++ b/rtl/vlib/memlib/fifo_2c_dram2.xdc
@@ -1,8 +1,7 @@
 # -*- tcl -*-
-# $Id: fifo_2c_dram2.xdc 830 2016-12-26 20:25:49Z mueller $
-#
+# $Id: fifo_2c_dram2.xdc 1190 2019-07-13 17:05:39Z mueller $
+# SPDX-License-Identifier: GPL-3.0-or-later
 # Copyright 2016- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-# License disclaimer see License.txt in $RETROBASE directory
 #
 # cdc constraints for fifo_2c_dram2 core
 #