Add basic DDR memory support

- arty board support - viv_tools_build: export log and rpt generated in OOC synthesis runs - s7_cmt_sfs_2: dual-channel frequency synthesis MMCM/PLL wrapper - s7_cmt_1ce1ce2c: clocking block for 7-Series: 2 clk+CEs + 2 clk - cdc_signal_s1_as: clock domain crossing for a signal, 2 stage, asyn input - migui_core_gsim: highly simplified MIG UI simulation model
2026-04-03 05:15:12 +00:00 · 2018-12-31 10:00:14 +01:00
parent cf6c0ed8e0
commit 14362b2a56
30 changed files with 2109 additions and 6 deletions
--- a/doc/CHANGELOG.md
+++ b/doc/CHANGELOG.md
@@ -20,6 +20,22 @@ The HEAD version shows the current development. No guarantees that
 software or firmware builds or that the documentation is consistent.
 The full set of tests is only run for tagged releases.

+### Summary
+- add support DDR memory via Vivado MIG cores
+  - arty board support
+
+### New features
+- s7_cmt_sfs_2: dual-channel frequency synthesis MMCM/PLL wrapper
+- s7_cmt_1ce1ce2c: clocking block for 7-Series: 2 clk+CEs + 2 clk
+- cdc_signal_s1_as: clock domain crossing for a signal, 2 stage, asyn input
+- migui_core_gsim: highly simplified MIG UI simulation model
+
+### Changes
+- viv_tools_build: export log and rpt generated in OOC synthesis runs
+
+### Bug Fixes
+### Known issues
+
 <!-- --------------------------------------------------------------------- -->
 ---
 ## <a id="w11a_V0.753">2018-12-29: [w11a_V0.753](https://github.com/wfjm/w11/releases/tag/w11a_V0.753) - rev 1096(wfjm)</a>
--- a/rtl/bplib/README.md
+++ b/rtl/bplib/README.md
@@ -12,6 +12,7 @@ and is organized in
 | [fx2rlink](fx2rlink)   | modules for rlink over Cypress FX2 |
 | [issi](issi)           | simulation models for ISSI components |
 | [micron](micron)       | simulation models for Micron components |
+| [mig](mig)             | interface for MIG cores |
 | [nexys2](nexys2)       | support for Digilent Nexys2 board |
 | [nexys3](nexys3)       | support for Digilent Nexys3 board |
 | [nexys4](nexys4)       | support for Digilent Nexys4 board (cram version) |
--- a/rtl/bplib/arty/artylib.vhd
+++ b/rtl/bplib/arty/artylib.vhd
@@ -1,6 +1,6 @@
-- $Id: artylib.vhd 984 2018-01-02 20:56:27Z mueller $
+-- $Id: artylib.vhd 1063 2018-10-29 18:37:42Z mueller $
 --
-- Copyright 2016- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
+-- Copyright 2016-2018 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
 --
 -- This program is free software; you may redistribute and/or modify it under
 -- the terms of the GNU General Public License as published by the Free
@@ -20,6 +20,7 @@
 --
 -- Revision History: 
 -- Date         Rev Version  Comment
+-- 2018-10-29  1063   1.2    add arty_dram_aif
 -- 2016-03-06   740   1.1    add A_VPWRN/P to baseline config
 -- 2016-01-31   726   1.0    Initial version 
 ------------------------------------------------------------------------------
@@ -48,4 +49,36 @@ component arty_aif is                   -- ARTY, abstract iface, base
  );
 end component;

+component arty_dram_aif is               -- ARTY, abstract iface, base+dram
+  port (
+    I_CLK100 : in slbit;                -- 100 MHz clock
+    I_RXD : in slbit;                   -- receive data (board view)
+    O_TXD : out slbit;                  -- transmit data (board view)
+    I_SWI : in slv4;                    -- arty switches
+    I_BTN : in slv4;                    -- arty buttons
+    O_LED : out slv4;                   -- arty leds
+    O_RGBLED0 : out slv3;               -- arty rgb-led 0
+    O_RGBLED1 : out slv3;               -- arty rgb-led 1
+    O_RGBLED2 : out slv3;               -- arty rgb-led 2
+    O_RGBLED3 : out slv3;               -- arty rgb-led 3
+    A_VPWRN : in slv4;                  -- arty pwrmon (neg)
+    A_VPWRP : in slv4;                  -- arty pwrmon (pos)
+    DDR3_DQ      : inout slv16;         -- dram: data in/out
+    DDR3_DQS_P   : inout slv2;          -- dram: data strobe (diff-p)
+    DDR3_DQS_N   : inout slv2;          -- dram: data strobe (diff-n)
+    DDR3_ADDR    : out   slv14;         -- dram: address
+    DDR3_BA      : out   slv3;          -- dram: bank address
+    DDR3_RAS_N   : out   slbit;         -- dram: row addr strobe    (act.low)
+    DDR3_CAS_N   : out   slbit;         -- dram: column addr strobe (act.low)
+    DDR3_WE_N    : out   slbit;         -- dram: write enable       (act.low)
+    DDR3_RESET_N : out   slbit;         -- dram: reset              (act.low)
+    DDR3_CK_P    : out   slv1;          -- dram: clock (diff-p)
+    DDR3_CK_N    : out   slv1;          -- dram: clock (diff-n)
+    DDR3_CKE     : out   slv1;          -- dram: clock enable
+    DDR3_CS_N    : out   slv1;          -- dram: chip select        (act.low)
+    DDR3_DM      : out   slv2;          -- dram: data input mask
+    DDR3_ODT     : out   slv1           -- dram: on-die termination
+  );
+end component;
+
 end package artylib;
--- a/rtl/bplib/arty/mig_a.prj
+++ b/rtl/bplib/arty/mig_a.prj
@@ -0,0 +1,127 @@
+<?xml version='1.0' encoding='UTF-8'?>
+<!-- IMPORTANT: This is an internal file that has been generated by the MIG software. Any direct editing or changes made to this file may result in unpredictable behavior or data corruption. It is strongly advised that users do not edit the contents of this file. Re-run the MIG GUI with the required settings if any of the options provided below need to be altered. -->
+<Project NoOfControllers="1" >
+    <ModuleName>migui_arty</ModuleName>
+    <dci_inouts_inputs>1</dci_inouts_inputs>
+    <dci_inputs>1</dci_inputs>
+    <Debug_En>OFF</Debug_En>
+    <DataDepth_En>1024</DataDepth_En>
+    <LowPower_En>OFF</LowPower_En>
+    <XADC_En>Disabled</XADC_En>
+    <TargetFPGA>xc7a35ti-csg324/-1L</TargetFPGA>
+    <Version>4.0</Version>
+    <SystemClock>No Buffer</SystemClock>
+    <ReferenceClock>No Buffer</ReferenceClock>
+    <SysResetPolarity>ACTIVE HIGH</SysResetPolarity>
+    <BankSelectionFlag>FALSE</BankSelectionFlag>
+    <InternalVref>1</InternalVref>
+    <dci_hr_inouts_inputs>50 Ohms</dci_hr_inouts_inputs>
+    <dci_cascade>0</dci_cascade>
+    <Controller number="0" >
+        <MemoryDevice>DDR3_SDRAM/Components/MT41K128M16XX-15E</MemoryDevice>
+        <TimePeriod>3000</TimePeriod>
+        <VccAuxIO>1.8V</VccAuxIO>
+        <PHYRatio>4:1</PHYRatio>
+        <InputClkFreq>166.666</InputClkFreq>
+        <UIExtraClocks>0</UIExtraClocks>
+        <MMCM_VCO>666</MMCM_VCO>
+        <MMCMClkOut0> 1.000</MMCMClkOut0>
+        <MMCMClkOut1>1</MMCMClkOut1>
+        <MMCMClkOut2>1</MMCMClkOut2>
+        <MMCMClkOut3>1</MMCMClkOut3>
+        <MMCMClkOut4>1</MMCMClkOut4>
+        <DataWidth>16</DataWidth>
+        <DeepMemory>1</DeepMemory>
+        <DataMask>1</DataMask>
+        <ECC>Disabled</ECC>
+        <Ordering>Strict</Ordering>
+        <BankMachineCnt>2</BankMachineCnt>
+        <CustomPart>FALSE</CustomPart>
+        <NewPartName></NewPartName>
+        <RowAddress>14</RowAddress>
+        <ColAddress>10</ColAddress>
+        <BankAddress>3</BankAddress>
+        <MemoryVoltage>1.35V</MemoryVoltage>
+        <UserMemoryAddressMap>ROW_BANK_COLUMN</UserMemoryAddressMap>
+        <PinSelection>
+            <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="R2" SLEW="" name="ddr3_addr[0]" IN_TERM="" />
+            <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="R6" SLEW="" name="ddr3_addr[10]" IN_TERM="" />
+            <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="U6" SLEW="" name="ddr3_addr[11]" IN_TERM="" />
+            <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="T6" SLEW="" name="ddr3_addr[12]" IN_TERM="" />
+            <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="T8" SLEW="" name="ddr3_addr[13]" IN_TERM="" />
+            <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="M6" SLEW="" name="ddr3_addr[1]" IN_TERM="" />
+            <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="N4" SLEW="" name="ddr3_addr[2]" IN_TERM="" />
+            <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="T1" SLEW="" name="ddr3_addr[3]" IN_TERM="" />
+            <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="N6" SLEW="" name="ddr3_addr[4]" IN_TERM="" />
+            <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="R7" SLEW="" name="ddr3_addr[5]" IN_TERM="" />
+            <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="V6" SLEW="" name="ddr3_addr[6]" IN_TERM="" />
+            <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="U7" SLEW="" name="ddr3_addr[7]" IN_TERM="" />
+            <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="R8" SLEW="" name="ddr3_addr[8]" IN_TERM="" />
+            <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="V7" SLEW="" name="ddr3_addr[9]" IN_TERM="" />
+            <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="R1" SLEW="" name="ddr3_ba[0]" IN_TERM="" />
+            <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="P4" SLEW="" name="ddr3_ba[1]" IN_TERM="" />
+            <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="P2" SLEW="" name="ddr3_ba[2]" IN_TERM="" />
+            <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="M4" SLEW="" name="ddr3_cas_n" IN_TERM="" />
+            <Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL135" PADName="V9" SLEW="" name="ddr3_ck_n[0]" IN_TERM="" />
+            <Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL135" PADName="U9" SLEW="" name="ddr3_ck_p[0]" IN_TERM="" />
+            <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="N5" SLEW="" name="ddr3_cke[0]" IN_TERM="" />
+            <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="U8" SLEW="" name="ddr3_cs_n[0]" IN_TERM="" />
+            <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="L1" SLEW="" name="ddr3_dm[0]" IN_TERM="" />
+            <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="U1" SLEW="" name="ddr3_dm[1]" IN_TERM="" />
+            <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="K5" SLEW="" name="ddr3_dq[0]" IN_TERM="" />
+            <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="U4" SLEW="" name="ddr3_dq[10]" IN_TERM="" />
+            <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="V5" SLEW="" name="ddr3_dq[11]" IN_TERM="" />
+            <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="V1" SLEW="" name="ddr3_dq[12]" IN_TERM="" />
+            <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="T3" SLEW="" name="ddr3_dq[13]" IN_TERM="" />
+            <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="U3" SLEW="" name="ddr3_dq[14]" IN_TERM="" />
+            <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="R3" SLEW="" name="ddr3_dq[15]" IN_TERM="" />
+            <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="L3" SLEW="" name="ddr3_dq[1]" IN_TERM="" />
+            <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="K3" SLEW="" name="ddr3_dq[2]" IN_TERM="" />
+            <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="L6" SLEW="" name="ddr3_dq[3]" IN_TERM="" />
+            <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="M3" SLEW="" name="ddr3_dq[4]" IN_TERM="" />
+            <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="M1" SLEW="" name="ddr3_dq[5]" IN_TERM="" />
+            <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="L4" SLEW="" name="ddr3_dq[6]" IN_TERM="" />
+            <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="M2" SLEW="" name="ddr3_dq[7]" IN_TERM="" />
+            <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="V4" SLEW="" name="ddr3_dq[8]" IN_TERM="" />
+            <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="T5" SLEW="" name="ddr3_dq[9]" IN_TERM="" />
+            <Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL135" PADName="N1" SLEW="" name="ddr3_dqs_n[0]" IN_TERM="" />
+            <Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL135" PADName="V2" SLEW="" name="ddr3_dqs_n[1]" IN_TERM="" />
+            <Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL135" PADName="N2" SLEW="" name="ddr3_dqs_p[0]" IN_TERM="" />
+            <Pin VCCAUX_IO="" IOSTANDARD="DIFF_SSTL135" PADName="U2" SLEW="" name="ddr3_dqs_p[1]" IN_TERM="" />
+            <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="R5" SLEW="" name="ddr3_odt[0]" IN_TERM="" />
+            <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="P3" SLEW="" name="ddr3_ras_n" IN_TERM="" />
+            <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="K6" SLEW="" name="ddr3_reset_n" IN_TERM="" />
+            <Pin VCCAUX_IO="" IOSTANDARD="SSTL135" PADName="P5" SLEW="" name="ddr3_we_n" IN_TERM="" />
+        </PinSelection>
+        <System_Control>
+            <Pin PADName="No connect" Bank="Select Bank" name="sys_rst" />
+            <Pin PADName="No connect" Bank="Select Bank" name="init_calib_complete" />
+            <Pin PADName="No connect" Bank="Select Bank" name="tg_compare_error" />
+        </System_Control>
+        <TimingParameters>
+            <Parameters twtr="7.5" trrd="7.5" trefi="7.8" tfaw="45" trtp="7.5" tcke="5.625" trfc="160" trp="13.5" tras="36" trcd="13.5" />
+        </TimingParameters>
+        <mrBurstLength name="Burst Length" >8 - Fixed</mrBurstLength>
+        <mrBurstType name="Read Burst Type and Length" >Sequential</mrBurstType>
+        <mrCasLatency name="CAS Latency" >5</mrCasLatency>
+        <mrMode name="Mode" >Normal</mrMode>
+        <mrDllReset name="DLL Reset" >No</mrDllReset>
+        <mrPdMode name="DLL control for precharge PD" >Slow Exit</mrPdMode>
+        <emrDllEnable name="DLL Enable" >Enable</emrDllEnable>
+        <emrOutputDriveStrength name="Output Driver Impedance Control" >RZQ/6</emrOutputDriveStrength>
+        <emrMirrorSelection name="Address Mirroring" >Disable</emrMirrorSelection>
+        <emrCSSelection name="Controller Chip Select Pin" >Enable</emrCSSelection>
+        <emrRTT name="RTT (nominal) - On Die Termination (ODT)" >RZQ/6</emrRTT>
+        <emrPosted name="Additive Latency (AL)" >0</emrPosted>
+        <emrOCD name="Write Leveling Enable" >Disabled</emrOCD>
+        <emrDQS name="TDQS enable" >Enabled</emrDQS>
+        <emrRDQS name="Qoff" >Output Buffer Enabled</emrRDQS>
+        <mr2PartialArraySelfRefresh name="Partial-Array Self Refresh" >Full Array</mr2PartialArraySelfRefresh>
+        <mr2CasWriteLatency name="CAS write latency" >5</mr2CasWriteLatency>
+        <mr2AutoSelfRefresh name="Auto Self Refresh" >Enabled</mr2AutoSelfRefresh>
+        <mr2SelfRefreshTempRange name="High Temparature Self Refresh Rate" >Normal</mr2SelfRefreshTempRange>
+        <mr2RTTWR name="RTT_WR - Dynamic On Die Termination (ODT)" >Dynamic ODT off</mr2RTTWR>
+        <PortInterface>NATIVE</PortInterface>
+    </Controller>
+
+</Project>
--- a/rtl/bplib/arty/mig_arty.tcl
+++ b/rtl/bplib/arty/mig_arty.tcl
@@ -0,0 +1,61 @@
+# $Id: mig_arty.tcl 1092 2018-12-24 08:01:50Z mueller $
+#
+# Copyright 2018- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
+# License disclaimer see License.txt in $RETROBASE directory
+#
+# Revision History:
+# Date         Rev Version  Comment
+# 2018-12-19  1090   1.0    Initial version
+# 2018-11-18  1072   0.1    First draft
+#
+
+# defined tested MIG versions with project files
+set tdsc_list { "4.0" "mig_a.prj" \
+                "4.1" "mig_a.prj" \
+                "4.2" "mig_a.prj" }
+
+# determine available MIG version (only latest supported !!)
+set vlnv [get_ipdefs "xilinx.com:ip:mig_7series:*"]
+set vers [lindex [split $vlnv ":"] 3]
+
+# filter out matching MIG version
+
+set mprj {}
+foreach {tver tprj} $tdsc_list {
+  lappend tver_list $tver
+  if {$vers eq $tver} { set mprj $tprj }
+}
+
+puts [format "## tested    MIG versions: %s" [join $tver_list "  "]]
+puts [format "## available MIG version:  %s" $vers]
+
+if {$mprj ne ""} {
+  puts [format "## selected  MIG version:  %s with %s" $vers $mprj]
+} else {
+  error "sramif_mig_arty: no tested MIG version found"
+}
+
+create_ip -vlnv "xilinx.com:ip:mig_7series:$vers" -module_name migui_arty
+
+set ip_dir [get_property IP_DIR [ get_ips ips migui_arty]]
+##puts "ip_dir: $ip_dir"
+puts "## migui: copy $mprj to IP_DIR"
+file copy $mprj "$ip_dir/$mprj"
+
+puts "## migui: set_property"
+set_property -dict [list \
+                      CONFIG.XML_INPUT_FILE $mprj \
+                      CONFIG.RESET_BOARD_INTERFACE {Custom} \
+                      CONFIG.MIG_DONT_TOUCH_PARAM {Custom} \
+                      CONFIG.BOARD_MIG_PARAM {Custom} \
+                     ] \
+                    [get_ips migui_arty]
+
+puts "## migui: generate_target"
+generate_target {instantiation_template} \
+  [get_files "$ip_dir/migui_arty.xci"]
+
+puts "## migui: export_ip_user_files"
+export_ip_user_files -of_objects \
+  [get_files "$ip_dir/migui_arty.xci"] \
+  -no_script -sync -force -quiet
--- a/rtl/bplib/arty/miglib_arty.vbom
+++ b/rtl/bplib/arty/miglib_arty.vbom
@@ -0,0 +1,4 @@
+# libs
+../../vlib/slvtypes.vhd
+../mig/miglib.vbom
+miglib_arty.vhd
--- a/rtl/bplib/arty/miglib_arty.vhd
+++ b/rtl/bplib/arty/miglib_arty.vhd
@@ -0,0 +1,121 @@
+-- $Id: miglib_arty.vhd 1093 2018-12-25 19:52:53Z mueller $
+--
+-- Copyright 2018- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
+--
+-- This program is free software; you may redistribute and/or modify it under
+-- the terms of the GNU General Public License as published by the Free
+-- Software Foundation, either version 3, or (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful, but
+-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
+-- or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for complete details.
+--
+------------------------------------------------------------------------------
+-- Package Name:   miglib_arty
+-- Description:    MIG interface components - for arty
+--
+-- Dependencies:   -
+-- Tool versions:  viv 2017.2; ghdl 0.34
+--
+-- Revision History: 
+-- Date         Rev Version  Comment
+-- 2018-11-17  1071   1.0    Initial version 
+------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+use work.slvtypes.all;
+use work.miglib.all;
+
+package miglib_arty is
+  
+constant mig_bawidth : positive :=  4;               -- byte addr width
+constant mig_mawidth : positive := 28;               -- mem addr width    
+constant mig_mwidth  : positive := 2**mig_bawidth;   -- mask width ( 16)
+constant mig_dwidth  : positive := 8*mig_mwidth;     -- data width (128)
+
+component sramif_mig_arty is            -- SRAM to DDR via MIG for arty
+  port (
+    CLK    : in slbit;                  -- clock
+    RESET  : in slbit;                  -- reset
+    REQ    : in slbit;                  -- request
+    WE     : in slbit;                  -- write enable
+    BUSY   : out slbit;                 -- controller busy
+    ACK_R  : out slbit;                 -- acknowledge read
+    ACK_W  : out slbit;                 -- acknowledge write
+    ACT_R  : out slbit;                 -- signal active read
+    ACT_W  : out slbit;                 -- signal active write
+    ADDR   : in slv20;                  -- address  (32 bit word address)
+    BE     : in slv4;                   -- byte enable
+    DI     : in slv32;                  -- data in  (memory view)
+    DO     : out slv32;                 -- data out (memory view)
+    CLKMIG : in slbit;                  -- sys clock for mig core
+    CLKREF : in slbit;                  -- ref clock for mig core
+    TEMP   : in slv12;                  -- die temperature
+    MONI   : out sramif2migui_moni_type;-- monitor signals
+    DDR3_DQ      : inout slv16;         -- dram: data in/out
+    DDR3_DQS_P   : inout slv2;          -- dram: data strobe (diff-p)
+    DDR3_DQS_N   : inout slv2;          -- dram: data strobe (diff-n)
+    DDR3_ADDR    : out   slv14;         -- dram: address
+    DDR3_BA      : out   slv3;          -- dram: bank address
+    DDR3_RAS_N   : out   slbit;         -- dram: row addr strobe    (act.low)
+    DDR3_CAS_N   : out   slbit;         -- dram: column addr strobe (act.low)
+    DDR3_WE_N    : out   slbit;         -- dram: write enable       (act.low)
+    DDR3_RESET_N : out   slbit;         -- dram: reset              (act.low)
+    DDR3_CK_P    : out   slv1;          -- dram: clock (diff-p)
+    DDR3_CK_N    : out   slv1;          -- dram: clock (diff-n)
+    DDR3_CKE     : out   slv1;          -- dram: clock enable
+    DDR3_CS_N    : out   slv1;          -- dram: chip select        (act.low)
+    DDR3_DM      : out   slv2;          -- dram: data input mask
+    DDR3_ODT     : out   slv1           -- dram: on-die termination
+  );
+end component;
+
+component migui_arty is                 -- MIG generated for arty
+  port (
+    DDR3_DQ      : inout slv16;         -- dram: data in/out
+    DDR3_DQS_P   : inout slv2;          -- dram: data strobe (diff-p)
+    DDR3_DQS_N   : inout slv2;          -- dram: data strobe (diff-n)
+    DDR3_ADDR    : out   slv14;         -- dram: address
+    DDR3_BA      : out   slv3;          -- dram: bank address
+    DDR3_RAS_N   : out   slbit;         -- dram: row addr strobe    (act.low)
+    DDR3_CAS_N   : out   slbit;         -- dram: column addr strobe (act.low)
+    DDR3_WE_N    : out   slbit;         -- dram: write enable       (act.low)
+    DDR3_RESET_N : out   slbit;         -- dram: reset              (act.low)
+    DDR3_CK_P    : out   slv1;          -- dram: clock (diff-p)
+    DDR3_CK_N    : out   slv1;          -- dram: clock (diff-n)
+    DDR3_CKE     : out   slv1;          -- dram: clock enable
+    DDR3_CS_N    : out   slv1;          -- dram: chip select        (act.low)
+    DDR3_DM      : out   slv2;          -- dram: data input mask
+    DDR3_ODT     : out   slv1;          -- dram: on-die termination
+    APP_ADDR            : in  slv(mig_mawidth-1 downto 0); -- MIGUI address
+    APP_CMD             : in  slv3;       -- MIGUI command
+    APP_EN              : in  slbit;      -- MIGUI command enable
+    APP_WDF_DATA        : in  slv(mig_dwidth-1 downto 0); -- MIGUI write data
+    APP_WDF_END         : in  slbit;                      -- MIGUI write end
+    APP_WDF_MASK        : in  slv(mig_mwidth-1 downto 0); -- MIGUI write mask
+    APP_WDF_WREN        : in  slbit;                      -- MIGUI write enable
+    APP_RD_DATA         : out slv(mig_dwidth-1 downto 0); -- MIGUI read data
+    APP_RD_DATA_END     : out slbit;                      -- MIGUI read end
+    APP_RD_DATA_VALID   : out slbit;                      -- MIGUI read valid
+    APP_RDY             : out slbit;      -- MIGUI ready for cmd
+    APP_WDF_RDY         : out slbit;      -- MIGUI ready for data write
+    APP_SR_REQ          : in  slbit;      -- MIGUI reserved (tie to 0)
+    APP_REF_REQ         : in  slbit;      -- MIGUI refresh reques
+    APP_ZQ_REQ          : in  slbit;      -- MIGUI ZQ calibrate request
+    APP_SR_ACTIVE       : out slbit;      -- MIGUI reserved (ignore)
+    APP_REF_ACK         : out slbit;      -- MIGUI refresh acknowledge
+    APP_ZQ_ACK          : out slbit;      -- MIGUI ZQ calibrate acknowledge
+    UI_CLK              : out slbit;      -- MIGUI clock
+    UI_CLK_SYNC_RST     : out slbit;      -- MIGUI reset
+    INIT_CALIB_COMPLETE : out slbit;      -- MIGUI calibration done
+    SYS_CLK_I           : in  slbit;      -- MIGUI system clock
+    CLK_REF_I           : in  slbit;      -- MIGUI reference clock
+    DEVICE_TEMP_I       : in  slv12;      -- MIGUI xadc temperature
+    SYS_RST             : in  slbit       -- MIGUI system reset
+  );
+end component;
+
+end package miglib_arty;
--- a/rtl/bplib/arty/migui_arty_gsim.vbom
+++ b/rtl/bplib/arty/migui_arty_gsim.vbom
@@ -0,0 +1,8 @@
+# libs
+../../vlib/slvtypes.vhd
+../mig/miglib.vbom
+miglib_arty.vbom
+# components
+../mig/migui_core_gsim.vbom
+# design
+migui_arty_gsim.vhd
--- a/rtl/bplib/arty/migui_arty_gsim.vhd
+++ b/rtl/bplib/arty/migui_arty_gsim.vhd
@@ -0,0 +1,137 @@
+-- $Id: migui_arty_gsim.vhd 1093 2018-12-25 19:52:53Z mueller $
+--
+-- Copyright 2018- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
+--
+-- This program is free software; you may redistribute and/or modify it under
+-- the terms of the GNU General Public License as published by the Free
+-- Software Foundation, either version 3, or (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful, but
+-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
+-- or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for complete details.
+-- 
+------------------------------------------------------------------------------
+-- Module Name:    migui_arty - sim
+-- Description:    MIG generated for arty - simple simulator
+--
+-- Dependencies:   bplib/mig/migui_core_gsim
+-- Test bench:     tb_tst_sram_arty
+-- Target Devices: arty board
+-- Tool versions:  viv 2017.2; ghdl 0.34
+--
+-- Revision History: 
+-- Date         Rev Version  Comment
+-- 2018-12-25  1093   1.0    Initial version
+-- 2018-11-17  1071   0.1    First draft
+-- 
+------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+use work.slvtypes.all;
+use work.miglib.all;
+use work.miglib_arty.all;
+
+entity migui_arty is                    -- MIG generated for arty
+  port (
+    DDR3_DQ      : inout slv16;         -- dram: data in/out
+    DDR3_DQS_P   : inout slv2;          -- dram: data strobe (diff-p)
+    DDR3_DQS_N   : inout slv2;          -- dram: data strobe (diff-n)
+    DDR3_ADDR    : out   slv14;         -- dram: address
+    DDR3_BA      : out   slv3;          -- dram: bank address
+    DDR3_RAS_N   : out   slbit;         -- dram: row addr strobe    (act.low)
+    DDR3_CAS_N   : out   slbit;         -- dram: column addr strobe (act.low)
+    DDR3_WE_N    : out   slbit;         -- dram: write enable       (act.low)
+    DDR3_RESET_N : out   slbit;         -- dram: reset              (act.low)
+    DDR3_CK_P    : out   slv1;          -- dram: clock (diff-p)
+    DDR3_CK_N    : out   slv1;          -- dram: clock (diff-n)
+    DDR3_CKE     : out   slv1;          -- dram: clock enable
+    DDR3_CS_N    : out   slv1;          -- dram: chip select        (act.low)
+    DDR3_DM      : out   slv2;          -- dram: data input mask
+    DDR3_ODT     : out   slv1;          -- dram: on-die termination
+    APP_ADDR            : in  slv(mig_mawidth-1 downto 0); -- MIGUI address
+    APP_CMD             : in  slv3;     -- MIGUI command
+    APP_EN              : in  slbit;    -- MIGUI command enable
+    APP_WDF_DATA        : in  slv(mig_dwidth-1 downto 0);-- MIGUI write data
+    APP_WDF_END         : in  slbit;                     -- MIGUI write end
+    APP_WDF_MASK        : in  slv(mig_mwidth-1 downto 0); -- MIGUI write mask
+    APP_WDF_WREN        : in  slbit;      -- MIGUI data write enable
+    APP_RD_DATA         : out slv(mig_dwidth-1 downto 0); -- MIGUI read data
+    APP_RD_DATA_END     : out slbit;                      -- MIGUI read end
+    APP_RD_DATA_VALID   : out slbit;                      -- MIGUI read valid
+    APP_RDY             : out slbit;    -- MIGUI ready for cmd
+    APP_WDF_RDY         : out slbit;    -- MIGUI ready for data write
+    APP_SR_REQ          : in  slbit;    -- MIGUI reserved (tie to 0)
+    APP_REF_REQ         : in  slbit;    -- MIGUI refresh request
+    APP_ZQ_REQ          : in  slbit;    -- MIGUI ZQ calibrate request
+    APP_SR_ACTIVE       : out slbit;    -- MIGUI reserved (ignore)
+    APP_REF_ACK         : out slbit;    -- MIGUI refresh acknowledge
+    APP_ZQ_ACK          : out slbit;    -- MIGUI ZQ calibrate acknowledge
+    UI_CLK              : out slbit;    -- MIGUI clock
+    UI_CLK_SYNC_RST     : out slbit;    -- MIGUI reset
+    INIT_CALIB_COMPLETE : out slbit;    -- MIGUI inital calibration complete
+    SYS_CLK_I           : in  slbit;    -- MIGUI system clock
+    CLK_REF_I           : in  slbit;    -- MIGUI reference clock
+    DEVICE_TEMP_I       : in  slv12;    -- MIGUI xadc temperature
+    SYS_RST             : in  slbit     -- MIGUI system reset
+  );
+end migui_arty;
+
+
+architecture sim of migui_arty is
+  
+begin
+
+  MIG_SIM : migui_core_gsim
+    generic map (
+      BAWIDTH => mig_bawidth,
+      MAWIDTH => mig_mawidth,
+      SAWIDTH => 24,
+      CLKMUI_MUL =>  7,
+      CLKMUI_DIV => 14)
+    port map (
+      SYS_CLK             => SYS_CLK_I,
+      SYS_RST             => SYS_RST,
+      UI_CLK              => UI_CLK,
+      UI_CLK_SYNC_RST     => UI_CLK_SYNC_RST,
+      INIT_CALIB_COMPLETE => INIT_CALIB_COMPLETE,
+      APP_RDY             => APP_RDY,
+      APP_EN              => APP_EN,
+      APP_CMD             => APP_CMD,
+      APP_ADDR            => APP_ADDR,
+      APP_WDF_RDY         => APP_WDF_RDY,
+      APP_WDF_WREN        => APP_WDF_WREN,
+      APP_WDF_DATA        => APP_WDF_DATA,
+      APP_WDF_MASK        => APP_WDF_MASK,
+      APP_WDF_END         => APP_WDF_END,
+      APP_RD_DATA_VALID   => APP_RD_DATA_VALID,
+      APP_RD_DATA         => APP_RD_DATA,
+      APP_RD_DATA_END     => APP_RD_DATA_END,
+      APP_REF_REQ         => APP_REF_REQ,
+      APP_ZQ_REQ          => APP_ZQ_REQ,
+      APP_REF_ACK         => APP_REF_ACK,
+      APP_ZQ_ACK          => APP_ZQ_ACK
+    );
+
+    DDR3_DQ      <= (others=>'Z');
+    DDR3_DQS_P   <= (others=>'Z');
+    DDR3_DQS_N   <= (others=>'Z');
+    DDR3_ADDR    <= (others=>'0');
+    DDR3_BA      <= (others=>'0');
+    DDR3_RAS_N   <= '1';
+    DDR3_CAS_N   <= '1';
+    DDR3_WE_N    <= '1';
+    DDR3_RESET_N <= '1';
+    DDR3_CK_P    <= (others=>'0');
+    DDR3_CK_N    <= (others=>'1');
+    DDR3_CKE     <= (others=>'0');
+    DDR3_CS_N    <= (others=>'1');
+    DDR3_DM      <= (others=>'0');
+    DDR3_ODT     <= (others=>'0');
+  
+    APP_SR_ACTIVE       <= '0';
+
+end sim;
--- a/rtl/bplib/arty/tb/.gitignore
+++ b/rtl/bplib/arty/tb/.gitignore
@@ -1 +1,2 @@
 tb_arty_dummy
+tb_arty_dram_dummy
--- a/rtl/bplib/arty/tb/Makefile
+++ b/rtl/bplib/arty/tb/Makefile
@@ -1,4 +1,4 @@
-# $Id: Makefile 776 2016-06-18 17:22:51Z mueller $
+# $Id: Makefile 1063 2018-10-29 18:37:42Z mueller $
 #
 #  Revision History: 
 # Date         Rev Version  Comment
@@ -6,7 +6,7 @@
 # 2016-04-22   763   1.1    add include dep_vsim
 # 2016-01-31   726   1.0    Initial version
 #
-EXE_all = tb_arty_dummy
+EXE_all = tb_arty_dummy tb_arty_dram_dummy
 #
 include ${RETROBASE}/rtl/make_viv/viv_default_arty.mk
 #
--- a/rtl/bplib/arty/tb/arty_dram_dummy.vbom
+++ b/rtl/bplib/arty/tb/arty_dram_dummy.vbom
@@ -0,0 +1,5 @@
+# libs
+../../../vlib/slvtypes.vhd
+# components
+# design
+arty_dram_dummy.vhd
--- a/rtl/bplib/arty/tb/arty_dram_dummy.vhd
+++ b/rtl/bplib/arty/tb/arty_dram_dummy.vhd
@@ -0,0 +1,95 @@
+-- $Id: arty_dram_dummy.vhd 1063 2018-10-29 18:37:42Z mueller $
+--
+-- Copyright 2018- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
+--
+-- This program is free software; you may redistribute and/or modify it under
+-- the terms of the GNU General Public License as published by the Free
+-- Software Foundation, either version 3, or (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful, but
+-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
+-- or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for complete details.
+-- 
+------------------------------------------------------------------------------
+-- Module Name:    arty_dram_dummy - syn
+-- Description:    arty target (base; serport loopback, dram project)
+--
+-- Dependencies:   -
+-- To test:        tb_arty_dram
+-- Target Devices: generic
+-- Tool versions:  viv 2017.2; ghdl 0.34
+--
+-- Revision History: 
+-- Date         Rev Version  Comment
+-- 2018-10-28  1063   1.0    Initial version (derived from arty_dummy)
+------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+use work.slvtypes.all;
+
+entity arty_dram_dummy is               -- ARTY dummy (base+dram)
+                                        -- implements arty_dram_aif
+  port (
+    I_CLK100 : in slbit;                -- 100 MHz board clock
+    I_RXD : in slbit;                   -- receive data (board view)
+    O_TXD : out slbit;                  -- transmit data (board view)
+    I_SWI : in slv4;                    -- arty switches
+    I_BTN : in slv4;                    -- arty buttons
+    O_LED : out slv4;                   -- arty leds
+    O_RGBLED0 : out slv3;               -- arty rgb-led 0
+    O_RGBLED1 : out slv3;               -- arty rgb-led 1
+    O_RGBLED2 : out slv3;               -- arty rgb-led 2
+    O_RGBLED3 : out slv3;               -- arty rgb-led 3
+    A_VPWRN : in slv4;                  -- arty pwrmon (neg)
+    A_VPWRP : in slv4;                  -- arty pwrmon (pos)
+    DDR3_DQ      : inout slv16;         -- dram: data in/out
+    DDR3_DQS_P   : inout slv2;          -- dram: data strobe (diff-p)
+    DDR3_DQS_N   : inout slv2;          -- dram: data strobe (diff-n)
+    DDR3_ADDR    : out   slv14;         -- dram: address
+    DDR3_BA      : out   slv3;          -- dram: bank address
+    DDR3_RAS_N   : out   slbit;         -- dram: row addr strobe    (act.low)
+    DDR3_CAS_N   : out   slbit;         -- dram: column addr strobe (act.low)
+    DDR3_WE_N    : out   slbit;         -- dram: write enable       (act.low)
+    DDR3_RESET_N : out   slbit;         -- dram: reset              (act.low)
+    DDR3_CK_P    : out   slv1;          -- dram: clock (diff-p)
+    DDR3_CK_N    : out   slv1;          -- dram: clock (diff-n)
+    DDR3_CKE     : out   slv1;          -- dram: clock enable
+    DDR3_CS_N    : out   slv1;          -- dram: chip select        (act.low)
+    DDR3_DM      : out   slv2;          -- dram: data input mask
+    DDR3_ODT     : out   slv1           -- dram: on-die termination
+  );
+end arty_dram_dummy;
+
+architecture syn of arty_dram_dummy is
+  
+begin
+
+  O_TXD    <= I_RXD;                    -- loop back serport
+
+  O_LED    <= I_SWI;                    -- mirror SWI on LED
+
+  O_RGBLED0 <= I_BTN(2 downto 0);       -- mirror BTN on RGBLED0
+  O_RGBLED1 <= (others=>'0');
+  O_RGBLED2 <= (others=>'0');
+  O_RGBLED3 <= (others=>'0');
+  
+  DDR3_DQ      <= (others=>'Z');
+  DDR3_DQS_P   <= (others=>'Z');
+  DDR3_DQS_N   <= (others=>'Z');
+  DDR3_ADDR    <= (others=>'0');
+  DDR3_BA      <= (others=>'0');
+  DDR3_RAS_N   <= '1';
+  DDR3_CAS_N   <= '1';
+  DDR3_WE_N    <= '1';
+  DDR3_RESET_N <= '1';
+  DDR3_CK_P    <= (others=>'0');
+  DDR3_CK_N    <= (others=>'1');
+  DDR3_CKE     <= (others=>'0');
+  DDR3_CS_N    <= (others=>'1');
+  DDR3_DM      <= (others=>'0');
+  DDR3_ODT     <= (others=>'0');
+
+end syn;
--- a/rtl/bplib/arty/tb/tb_arty_dram.vbom
+++ b/rtl/bplib/arty/tb/tb_arty_dram.vbom
@@ -0,0 +1,24 @@
+# Not meant for direct top level usage. Used with 
+# tb_arty_dram_(....)[_ssim].vbom and config
+# lines to generate the different cases.
+#
+# libs
+../../../vlib/slvtypes.vhd
+../../../vlib/rlink/rlinklib.vbom
+../../../vlib/xlib/xlib.vhd
+../artylib.vhd
+../../../vlib/simlib/simlib.vhd
+../../../vlib/simlib/simbus.vhd
+${sys_conf := sys_conf_sim.vhd}
+# components
+${gsr_pulse := ../../../vlib/xlib/gsr_pulse_dummy.vbom}
+../../../vlib/simlib/simclk.vbom
+../../../vlib/simlib/simclkcnt.vbom
+../../../vlib/rlink/tbcore/tbcore_rlink.vbom
+../../../vlib/xlib/sfs_gsim_core.vbom
+tb_arty_core.vbom
+../../../vlib/serport/tb/serport_master_tb.vbom
+${arty_dram_aif := arty_dram_dummy.vbom}  -UUT
+# design
+tb_arty_dram.vhd
+@top:tb_arty_dram
--- a/rtl/bplib/arty/tb/tb_arty_dram.vhd
+++ b/rtl/bplib/arty/tb/tb_arty_dram.vhd
@@ -0,0 +1,217 @@
+-- $Id: tb_arty_dram.vhd 1069 2018-11-16 17:11:30Z mueller $
+--
+-- Copyright 2018- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
+--
+-- This program is free software; you may redistribute and/or modify it under
+-- the terms of the GNU General Public License as published by the Free
+-- Software Foundation, either version 3, or (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful, but
+-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
+-- or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for complete details.
+-- 
+------------------------------------------------------------------------------
+-- Module Name:    tb_arty_dram - sim
+-- Description:    Test bench for arty (base+dram)
+--
+-- Dependencies:   simlib/simclk
+--                 simlib/simclkcnt
+--                 rlink/tbcore/tbcore_rlink
+--                 xlib/sfs_gsim_core
+--                 tb_basys3_core
+--                 serport/tb/serport_master_tb
+--                 arty_dram_aif [UUT]
+--
+-- To test:        generic, any arty_dram_aif target
+--
+-- Target Devices: generic
+-- Tool versions:  viv 2017.2; ghdl 0.34
+--
+-- Revision History: 
+-- Date         Rev Version  Comment
+-- 2018-11-03  1064   1.1.1  use sfs_gsim_core
+-- 2018-10-28  1063   1.0    Initial version (derived from tb_arty)
+------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use ieee.std_logic_textio.all;
+use std.textio.all;
+
+use work.slvtypes.all;
+use work.rlinklib.all;
+use work.xlib.all;
+use work.artylib.all;
+use work.simlib.all;
+use work.simbus.all;
+use work.sys_conf.all;
+
+entity tb_arty_dram is
+end tb_arty_dram;
+
+architecture sim of tb_arty_dram is
+  
+  signal CLKOSC : slbit := '0';         -- board clock (100 Mhz)
+  signal CLKCOM : slbit := '0';         -- communication clock
+
+  signal CLKCOM_CYCLE : integer := 0;
+
+  signal RESET : slbit := '0';
+  signal CLKDIV : slv2 := "00";         -- run with 1 clocks / bit !!
+  signal RXDATA : slv8 := (others=>'0');
+  signal RXVAL : slbit := '0';
+  signal RXERR : slbit := '0';
+  signal RXACT : slbit := '0';
+  signal TXDATA : slv8 := (others=>'0');
+  signal TXENA : slbit := '0';
+  signal TXBUSY : slbit := '0';
+
+  signal I_RXD : slbit := '1';
+  signal O_TXD : slbit := '1';
+  signal I_SWI : slv4 := (others=>'0');
+  signal I_BTN : slv4 := (others=>'0');
+  signal O_LED : slv4 := (others=>'0');
+  signal O_RGBLED0 : slv3 := (others=>'0');
+  signal O_RGBLED1 : slv3 := (others=>'0');
+  signal O_RGBLED2 : slv3 := (others=>'0');
+  signal O_RGBLED3 : slv3 := (others=>'0');
+  
+  signal IO_DDR3_DQ    : slv16 := (others=>'Z');
+  signal IO_DDR3_DQS_P : slv2 := (others=>'Z');
+  signal IO_DDR3_DQS_N : slv2 := (others=>'Z');
+
+  signal R_PORTSEL_XON : slbit := '0';       -- if 1 use xon/xoff
+
+  constant sbaddr_portsel: slv8 := slv(to_unsigned( 8,8));
+
+  constant clock_period : Delay_length :=  10 ns;
+  constant clock_offset : Delay_length := 200 ns;
+
+begin
+
+  GINIT : entity work.gsr_pulse;
+  
+  CLKGEN : simclk
+    generic map (
+      PERIOD => clock_period,
+      OFFSET => clock_offset)
+    port map (
+      CLK      => CLKOSC
+    );
+  
+  CLKGEN_COM : sfs_gsim_core
+    generic map (
+      VCO_DIVIDE   => sys_conf_clkser_vcodivide,
+      VCO_MULTIPLY => sys_conf_clkser_vcomultiply,
+      OUT_DIVIDE   => sys_conf_clkser_outdivide)
+    port map (
+      CLKIN   => CLKOSC,
+      CLKFX   => CLKCOM,
+      LOCKED  => open
+    );
+
+  CLKCNT : simclkcnt port map (CLK => CLKCOM, CLK_CYCLE => CLKCOM_CYCLE);
+
+  TBCORE : entity work.tbcore_rlink
+    port map (
+      CLK      => CLKCOM,
+      RX_DATA  => TXDATA,
+      RX_VAL   => TXENA,
+      RX_HOLD  => TXBUSY,
+      TX_DATA  => RXDATA,
+      TX_ENA   => RXVAL
+    );
+
+  ARTYCORE : entity work.tb_arty_core
+    port map (
+      I_SWI       => I_SWI,
+      I_BTN       => I_BTN
+    );
+
+  UUT : arty_dram_aif
+    port map (
+      I_CLK100     => CLKOSC,
+      I_RXD        => I_RXD,
+      O_TXD        => O_TXD,
+      I_SWI        => I_SWI,
+      I_BTN        => I_BTN,
+      O_LED        => O_LED,
+      O_RGBLED0    => O_RGBLED0,
+      O_RGBLED1    => O_RGBLED1,
+      O_RGBLED2    => O_RGBLED2,
+      O_RGBLED3    => O_RGBLED3,
+      A_VPWRN      => (others=>'0'),
+      A_VPWRP      => (others=>'0'),
+      DDR3_DQ      => IO_DDR3_DQ,
+      DDR3_DQS_P   => IO_DDR3_DQS_P,
+      DDR3_DQS_N   => IO_DDR3_DQS_N,
+      DDR3_ADDR    => open,
+      DDR3_BA      => open,
+      DDR3_RAS_N   => open,
+      DDR3_CAS_N   => open,
+      DDR3_WE_N    => open,
+      DDR3_RESET_N => open,
+      DDR3_CK_P    => open,
+      DDR3_CK_N    => open,
+      DDR3_CKE     => open,
+      DDR3_CS_N    => open,
+      DDR3_DM      => open,
+      DDR3_ODT     => open
+    );
+  
+  SERMSTR : entity work.serport_master_tb
+    generic map (
+      CDWIDTH => CLKDIV'length)
+    port map (
+      CLK     => CLKCOM,
+      RESET   => RESET,
+      CLKDIV  => CLKDIV,
+      ENAXON  => R_PORTSEL_XON,
+      ENAESC  => '0',
+      RXDATA  => RXDATA,
+      RXVAL   => RXVAL,
+      RXERR   => RXERR,
+      RXOK    => '1',
+      TXDATA  => TXDATA,
+      TXENA   => TXENA,
+      TXBUSY  => TXBUSY,
+      RXSD    => O_TXD,
+      TXSD    => I_RXD,
+      RXRTS_N => open,
+      TXCTS_N => '0'
+    );
+
+  proc_moni: process
+    variable oline : line;
+  begin
+    
+    loop
+      wait until rising_edge(CLKCOM);
+
+      if RXERR = '1' then
+        writetimestamp(oline, CLKCOM_CYCLE, " : seen RXERR=1");
+        writeline(output, oline);
+      end if;
+      
+    end loop;
+    
+  end process proc_moni;
+
+  --
+  -- Notes on portsel and XON control:
+  --   - most arty designs will use hardwired XON=1
+  --   - but some (especially basis tests) might not use flow control
+  --   - that's why XON flow control must be optional and configurable !
+  --
+  proc_simbus: process (SB_VAL)
+  begin
+    if SB_VAL'event and to_x01(SB_VAL)='1' then
+      if SB_ADDR = sbaddr_portsel then
+        R_PORTSEL_XON <= to_x01(SB_DATA(1));
+      end if;
+    end if;
+  end process proc_simbus;
+
+end sim;
--- a/rtl/bplib/bpgen/s7_cmt_1ce1ce2c.vbom
+++ b/rtl/bplib/bpgen/s7_cmt_1ce1ce2c.vbom
@@ -0,0 +1,10 @@
+# libs
+../../vlib/slvtypes.vhd
+# components
+[vsyn]../../vlib/xlib/s7_cmt_sfs_unisim.vbom
+[ghdl,vsim]../../vlib/xlib/s7_cmt_sfs_gsim.vbom
+[vsyn]../../vlib/xlib/s7_cmt_sfs_2_unisim.vbom
+[ghdl,vsim]../../vlib/xlib/s7_cmt_sfs_2_gsim.vbom
+../../vlib/genlib/clkdivce.vbom
+# design
+s7_cmt_1ce1ce2c.vhd
--- a/rtl/bplib/bpgen/s7_cmt_1ce1ce2c.vhd
+++ b/rtl/bplib/bpgen/s7_cmt_1ce1ce2c.vhd
@@ -0,0 +1,158 @@
+-- $Id: s7_cmt_1ce1ce2c.vhd 1086 2018-12-16 18:29:55Z mueller $
+--
+-- Copyright 2018- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
+--
+-- This program is free software; you may redistribute and/or modify it under
+-- the terms of the GNU General Public License as published by the Free
+-- Software Foundation, either version 3, or (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful, but
+-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
+-- or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for complete details.
+-- 
+------------------------------------------------------------------------------
+-- Module Name:    s7_cmt_1ce1ce2c - syn
+-- Description:    clocking block for 7-Series: 2 clk+CEs + 2 clk
+--
+-- Dependencies:   s7_cmt_sfs
+--                 s7_cmt_sfs_2
+--                 clkdivce
+-- Test bench:     -
+-- Target Devices: generic 7-Series
+-- Tool versions:  viv 2017.2; ghdl 0.34
+--
+-- Revision History: 
+-- Date         Rev Version  Comment
+-- 2018-12-16  1086   1.0    Initial version 
+------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+use work.slvtypes.all;
+use work.xlib.all;
+use work.genlib.all;
+
+entity s7_cmt_1ce1ce2c  is              -- clocking block: 2 clk+CEs; 2 clk
+  generic (
+    CLKIN_PERIOD  : real := 10.0;       -- CLKIN period (def is 10.0 ns)
+    CLKIN_JITTER  : real := 0.01;       -- CLKIN jitter (def is 10 ps)
+    STARTUP_WAIT  : boolean := false;   -- hold FPGA startup till LOCKED
+    CLK0_VCODIV   : positive := 1;      -- clk0: vco clock divide
+    CLK0_VCOMUL   : positive := 1;      -- clk0: vco clock multiply 
+    CLK0_OUTDIV   : positive := 1;      -- clk0: output divide
+    CLK0_GENTYPE  : string := "PLL";    -- clk0: PLL or MMCM
+    CLK0_CDUWIDTH : positive :=   7;    -- clk0: usec clock divider width
+    CLK0_USECDIV  : positive :=  50;    -- clk0: divider ratio for usec pulse
+    CLK0_MSECDIV  : positive := 1000;   -- clk0: divider ratio for msec pulse
+    CLK1_VCODIV   : positive := 1;      -- clk1: vco clock divide
+    CLK1_VCOMUL   : positive := 1;      -- clk1: vco clock multiply 
+    CLK1_OUTDIV   : positive := 1;      -- clk1: output divide
+    CLK1_GENTYPE  : string := "MMCM";   -- clk1: PLL or MMCM
+    CLK1_CDUWIDTH : positive :=   7;    -- clk1: usec clock divider width
+    CLK1_USECDIV  : positive :=  50;    -- clk1: divider ratio for usec pulse
+    CLK1_MSECDIV  : positive := 1000;   -- clk1: divider ratio for msec pulse
+    CLK23_VCODIV  : positive := 1;      -- clk2+3: vco clock divide
+    CLK23_VCOMUL  : positive := 1;      -- clk2+3: vco clock multiply 
+    CLK2_OUTDIV   : positive := 1;      -- clk2: output divide
+    CLK3_OUTDIV   : positive := 1;      -- clk3: output divide
+    CLK23_GENTYPE : string := "PLL");   -- clk2+3: PLL or MMCM
+  port (
+    CLKIN    : in slbit;                -- clock input
+    CLK0     : out slbit;               -- clk0: clock output
+    CE0_USEC : out slbit;               -- clk0: usec pulse
+    CE0_MSEC : out slbit;               -- clk0: msec pulse
+    CLK1     : out slbit;               -- clk1: clock output
+    CE1_USEC : out slbit;               -- clk1: usec pulse
+    CE1_MSEC : out slbit;               -- clk1: msec pulse
+    CLK2     : out slbit;               -- clk2: clock output
+    CLK3     : out slbit;               -- clk3: clock output
+    LOCKED   : out slbit                -- all PLL/MMCM locked
+  );
+end s7_cmt_1ce1ce2c;
+
+architecture syn of s7_cmt_1ce1ce2c is
+  
+  signal CLK0_L   : slbit := '0';
+  signal CLK1_L   : slbit := '0';
+  signal LOCKED0  : slbit := '0';
+  signal LOCKED1  : slbit := '0';
+  signal LOCKED23 : slbit := '0';
+
+begin
+
+  GEN_CLK0 : s7_cmt_sfs                 -- clock generator 0 -----------------
+    generic map (
+      VCO_DIVIDE     => CLK0_VCODIV,
+      VCO_MULTIPLY   => CLK0_VCOMUL,
+      OUT_DIVIDE     => CLK0_OUTDIV,
+      CLKIN_PERIOD   => CLKIN_PERIOD,
+      CLKIN_JITTER   => CLKIN_JITTER,
+      STARTUP_WAIT   => STARTUP_WAIT,
+      GEN_TYPE       => CLK0_GENTYPE)
+    port map (
+      CLKIN   => CLKIN,
+      CLKFX   => CLK0_L,
+      LOCKED  => LOCKED0
+    );
+
+  DIV_CLK0 : clkdivce                   -- usec/msec clock divider 0 ---------
+    generic map (
+      CDUWIDTH => CLK0_CDUWIDTH,
+      USECDIV  => CLK0_USECDIV,
+      MSECDIV  => CLK0_MSECDIV)
+    port map (
+      CLK     => CLK0_L,
+      CE_USEC => CE0_USEC,
+      CE_MSEC => CE0_MSEC
+    );
+
+  GEN_CLK1 : s7_cmt_sfs                 -- clock generator 1 -----------------
+    generic map (
+      VCO_DIVIDE     => CLK1_VCODIV,
+      VCO_MULTIPLY   => CLK1_VCOMUL,
+      OUT_DIVIDE     => CLK1_OUTDIV,
+      CLKIN_PERIOD   => CLKIN_PERIOD,
+      CLKIN_JITTER   => CLKIN_JITTER,
+      STARTUP_WAIT   => STARTUP_WAIT,
+      GEN_TYPE       => CLK1_GENTYPE)
+    port map (
+      CLKIN   => CLKIN,
+      CLKFX   => CLK1_L,
+      LOCKED  => LOCKED1
+    );
+
+  DIV_CLK1 : clkdivce                   -- usec/msec clock divider 1 ---------
+    generic map (
+      CDUWIDTH => CLK1_CDUWIDTH,
+      USECDIV  => CLK1_USECDIV,
+      MSECDIV  => CLK1_MSECDIV)
+    port map (
+      CLK     => CLK1_L,
+      CE_USEC => CE1_USEC,
+      CE_MSEC => CE1_MSEC
+    );
+
+  GEN_CLK23 : s7_cmt_sfs_2              -- clock generator 2+3 ---------------
+    generic map (
+      VCO_DIVIDE     => CLK23_VCODIV,
+      VCO_MULTIPLY   => CLK23_VCOMUL,
+      OUT0_DIVIDE    => CLK2_OUTDIV,
+      OUT1_DIVIDE    => CLK3_OUTDIV,
+      CLKIN_PERIOD   => CLKIN_PERIOD,
+      CLKIN_JITTER   => CLKIN_JITTER,
+      STARTUP_WAIT   => STARTUP_WAIT,
+      GEN_TYPE       => CLK23_GENTYPE)
+    port map (
+      CLKIN    => CLKIN,
+      CLKOUT0  => CLK2,
+      CLKOUT1  => CLK3,
+      LOCKED   => LOCKED23
+    );
+  
+  CLK0   <= CLK0_L;
+  CLK1   <= CLK1_L;
+  LOCKED <= LOCKED0 and LOCKED1 and LOCKED23;
+  
+end syn;
--- a/rtl/bplib/mig/Makefile
+++ b/rtl/bplib/mig/Makefile
@@ -0,0 +1,37 @@
+# $Id: Makefile 1067 2018-11-11 08:30:29Z mueller $
+#
+#  Revision History: 
+# Date         Rev Version  Comment
+# 2018-11-10  1067   1.0    Initial version
+#
+VBOM_all = $(wildcard *.vbom)
+DCP_all  = $(VBOM_all:.vbom=_syn.dcp)
+#
+# reference board for test synthesis is Artix-7 based Nexys4
+ifndef XTW_BOARD
+  XTW_BOARD=nexys4
+endif
+include ${RETROBASE}/rtl/make_viv/viv_default_$(XTW_BOARD).mk
+#
+.PHONY : catch all clean
+#
+catch :
+	@echo "no default target defined, use"
+	@echo "  make all"
+	@echo "  make <module>_syn.dcp"
+	@exit 1
+#
+all : $(DCP_all)
+#
+clean : viv_clean
+#
+#-----
+#
+include ${RETROBASE}/rtl/make_viv/generic_vivado.mk
+#
+VBOM_all = $(wildcard *.vbom)
+#
+ifndef DONTINCDEP
+include $(VBOM_all:.vbom=.dep_vsyn)
+endif
+#
--- a/rtl/bplib/mig/miglib.vbom
+++ b/rtl/bplib/mig/miglib.vbom
@@ -0,0 +1,3 @@
+# libs
+../../vlib/slvtypes.vhd
+miglib.vhd
--- a/rtl/bplib/mig/miglib.vhd
+++ b/rtl/bplib/mig/miglib.vhd
@@ -0,0 +1,152 @@
+-- $Id: miglib.vhd 1094 2018-12-27 15:18:27Z mueller $
+--
+-- Copyright 2018- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
+--
+-- This program is free software; you may redistribute and/or modify it under
+-- the terms of the GNU General Public License as published by the Free
+-- Software Foundation, either version 3, or (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful, but
+-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
+-- or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for complete details.
+--
+------------------------------------------------------------------------------
+-- Package Name:   miglib
+-- Description:    MIG interface components - generic
+--
+-- Dependencies:   -
+-- Tool versions:  viv 2017.2; ghdl 0.34
+--
+-- Revision History: 
+-- Date         Rev Version  Comment
+-- 2018-12-26  1094   1.0    Initial version 
+-- 2018-11-11  1067   0.1    First draft
+------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+use work.slvtypes.all;
+
+package miglib is
+  
+constant c_migui_cmd_read  : slv3 := "001";
+constant c_migui_cmd_write : slv3 := "000";
+
+type sramif2migui_moni_type is record   -- sramif2migui monitor port
+  rdrhit   : slbit;               -- read row hit
+  wrrhit   : slbit;               -- write row hit
+  wrflush  : slbit;               -- write row flush
+  migcbusy : slbit;               -- mig not ready for command
+  migwbusy : slbit;               -- mig not ready for data write
+  miguirst : slbit;               -- mig UI_CLK_SYNC_RST asserted
+  migcacow : slbit;               -- mig calibration complete wait
+end record sramif2migui_moni_type;
+  
+constant sramif2migui_moni_init : sramif2migui_moni_type := (
+  '0','0','0',                    -- rdrhit,wrrhit,wrflush
+  '0','0','0','0'                 -- migcbusy,migwbusy,miguirst,migcacow
+);
+
+component sramif2migui_core is          -- SRAM to MIG interface core
+  generic (
+    BAWIDTH : positive :=  4;           -- byte address width
+    MAWIDTH : positive := 28);          -- memory address width
+  port (
+    CLK   : in slbit;                   -- clock
+    RESET : in slbit;                   -- reset
+    REQ   : in slbit;                   -- request
+    WE    : in slbit;                   -- write enable
+    BUSY  : out slbit;                  -- controller busy
+    ACK_R : out slbit;                  -- acknowledge read
+    ACK_W : out slbit;                  -- acknowledge write
+    ACT_R : out slbit;                  -- signal active read
+    ACT_W : out slbit;                  -- signal active write
+    ADDR  : in slv20;                   -- address  (32 bit word address)
+    BE    : in slv4;                    -- byte enable
+    DI    : in slv32;                   -- data in  (memory view)
+    DO    : out slv32;                  -- data out (memory view)
+    MONI  : out sramif2migui_moni_type; -- monitor signals
+    UI_CLK              : in  slbit;    -- MIGUI clock
+    UI_CLK_SYNC_RST     : in  slbit;    -- MIGUI reset
+    INIT_CALIB_COMPLETE : in slbit;     -- MIGUI calibration done
+    APP_RDY             : in  slbit;    -- MIGUI ready for cmd
+    APP_EN              : out slbit;    -- MIGUI command enable
+    APP_CMD             : out slv3;     -- MIGUI command
+    APP_ADDR            : out slv(MAWIDTH-1 downto 0); -- MIGUI address
+    APP_WDF_RDY         : in  slbit;      -- MIGUI ready for data write
+    APP_WDF_WREN        : out slbit;      -- MIGUI data write enable
+    APP_WDF_DATA        : out slv(8*(2**BAWIDTH)-1 downto 0);-- MIGUI write data
+    APP_WDF_MASK        : out slv((2**BAWIDTH)-1 downto 0);  -- MIGUI write mask
+    APP_WDF_END         : out slbit;                         -- MIGUI write end
+    APP_RD_DATA_VALID   : in  slbit;                         -- MIGUI read valid
+    APP_RD_DATA         : in  slv(8*(2**BAWIDTH)-1 downto 0);-- MIGUI read data
+    APP_RD_DATA_END     : in  slbit                          -- MIGUI read end
+  );
+end component;
+
+component migui2bram is                 -- MIG to BRAM adapter
+  generic (
+    BAWIDTH    : positive :=  4;        -- byte address width
+    MAWIDTH    : positive := 28;        -- memory address width
+    RAWIDTH    : positive := 19;        -- BRAM memory address width
+    RDELAY     : positive :=  5;        -- read response delay
+    CLKMUI_MUL     : positive :=  6;    -- multiplier for MIG UI clock
+    CLKMUI_DIV     : positive := 12;    -- divider for MIG UI clock
+    CLKMSYS_PERIOD : real := 6.000);    -- MIG SYS_CLK period
+  port (
+    SYS_CLK             : in  slbit;    -- system clock
+    SYS_RST             : in  slbit;    -- system reset
+    UI_CLK              : out slbit;    -- MIGUI clock
+    UI_CLK_SYNC_RST     : out slbit;    -- MIGUI reset
+    INIT_CALIB_COMPLETE : out slbit;    -- MIGUI calibration done
+    APP_RDY             : out slbit;    -- MIGUI ready for cmd
+    APP_EN              : in  slbit;    -- MIGUI command enable
+    APP_CMD             : in  slv3;     -- MIGUI command
+    APP_ADDR            : in  slv(MAWIDTH-1 downto 0); -- MIGUI address
+    APP_WDF_RDY         : out slbit;    -- MIGUI ready for data write
+    APP_WDF_WREN        : in  slbit;    -- MIGUI data write enable
+    APP_WDF_DATA        : in  slv(8*(2**BAWIDTH)-1 downto 0);-- MIGUI write data
+    APP_WDF_MASK        : in  slv((2**BAWIDTH)-1 downto 0);  -- MIGUI write mask
+    APP_WDF_END         : in  slbit;                         -- MIGUI write end
+    APP_RD_DATA_VALID   : out slbit;                         -- MIGUI read valid
+    APP_RD_DATA         : out slv(8*(2**BAWIDTH)-1 downto 0);-- MIGUI read data
+    APP_RD_DATA_END     : out slbit                          -- MIGUI read end
+  );
+end component;
+
+component migui_core_gsim is            -- MIG interface simulation core
+  generic (
+    BAWIDTH    : positive :=  4;        -- byte address width
+    MAWIDTH    : positive := 28;        -- memory address width
+    SAWIDTH    : positive := 24;        -- simulator memory address width
+    CLKMUI_MUL : positive :=  6;        -- multiplier for MIG UI clock
+    CLKMUI_DIV : positive := 12;        -- divider for MIG UI clock
+    CACO_WAIT  : positive := 50);       -- UI_CLK cycles till CALIB_COMP = 1
+  port (
+    SYS_CLK             : in  slbit;    -- system clock
+    SYS_RST             : in  slbit;    -- system reset
+    UI_CLK              : out slbit;    -- MIGUI clock
+    UI_CLK_SYNC_RST     : out slbit;    -- MIGUI reset
+    INIT_CALIB_COMPLETE : out slbit;    -- MIGUI calibration done
+    APP_RDY             : out slbit;    -- MIGUI ready for cmd
+    APP_EN              : in  slbit;    -- MIGUI command enable
+    APP_CMD             : in  slv3;     -- MIGUI command
+    APP_ADDR            : in  slv(MAWIDTH-1 downto 0); -- MIGUI address
+    APP_WDF_RDY         : out slbit;    -- MIGUI ready for data write
+    APP_WDF_WREN        : in  slbit;    -- MIGUI data write enable
+    APP_WDF_DATA        : in  slv(8*(2**BAWIDTH)-1 downto 0);-- MIGUI write data
+    APP_WDF_MASK        : in  slv((2**BAWIDTH)-1 downto 0);  -- MIGUI write mask
+    APP_WDF_END         : in  slbit;                         -- MIGUI write end
+    APP_RD_DATA_VALID   : out slbit;                         -- MIGUI read valid
+    APP_RD_DATA         : out slv(8*(2**BAWIDTH)-1 downto 0);-- MIGUI read data
+    APP_RD_DATA_END     : out slbit;                         -- MIGUI read end
+    APP_REF_REQ         : in  slbit;      -- MIGUI refresh request
+    APP_ZQ_REQ          : in  slbit;      -- MIGUI ZQ calibrate request
+    APP_REF_ACK         : out slbit;      -- MIGUI refresh acknowledge
+    APP_ZQ_ACK          : out slbit       -- MIGUI ZQ calibrate acknowledge
+  );
+end component;
+
+end package miglib;
--- a/rtl/bplib/mig/migui_core_gsim.vbom
+++ b/rtl/bplib/mig/migui_core_gsim.vbom
@@ -0,0 +1,8 @@
+# libs
+../../vlib/slvtypes.vhd
+../../vlib/xlib/xlib.vhd
+miglib.vhd
+# components
+../../vlib/xlib/sfs_gsim_core.vbom
+# design
+migui_core_gsim.vhd
--- a/rtl/bplib/mig/migui_core_gsim.vhd
+++ b/rtl/bplib/mig/migui_core_gsim.vhd
@@ -0,0 +1,356 @@
+-- $Id: migui_core_gsim.vhd 1096 2018-12-29 07:54:17Z mueller $
+--
+-- Copyright 2018- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
+--
+-- This program is free software; you may redistribute and/or modify it under
+-- the terms of the GNU General Public License as published by the Free
+-- Software Foundation, either version 3, or (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful, but
+-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
+-- or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for complete details.
+-- 
+------------------------------------------------------------------------------
+-- Module Name:    migui_core_gsim - sim
+-- Description:    MIG interface simulation core
+--
+-- Dependencies:   sfs_gsim_core
+-- Test bench:     tb/tb_sramif2migui_core
+-- Target Devices: generic
+-- Tool versions:  viv 2017.2; ghdl 0.34
+--
+-- Revision History: 
+-- Date         Rev Version  Comment
+-- 2018-12-28  1096   1.0    Initial version
+-- 2018-11-10  1067   0.1    First draft 
+-- 
+------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+use work.slvtypes.all;
+use work.xlib.all;
+use work.miglib.all;
+
+entity migui_core_gsim is               -- MIG interface simulation core
+  generic (
+    BAWIDTH    : positive :=  4;        -- byte address width
+    MAWIDTH    : positive := 28;        -- memory address width
+    SAWIDTH    : positive := 24;        -- simulator memory address width
+    CLKMUI_MUL : positive :=  6;        -- multiplier for MIG UI clock
+    CLKMUI_DIV : positive := 12;        -- divider for MIG UI clock
+    CACO_WAIT  : positive := 50);       -- UI_CLK cycles till CALIB_COMP = 1
+  port (
+    SYS_CLK             : in  slbit;    -- system clock
+    SYS_RST             : in  slbit;    -- system reset
+    UI_CLK              : out slbit;    -- MIGUI clock
+    UI_CLK_SYNC_RST     : out slbit;    -- MIGUI reset
+    INIT_CALIB_COMPLETE : out slbit;    -- MIGUI calibration done
+    APP_RDY             : out slbit;    -- MIGUI ready for cmd
+    APP_EN              : in  slbit;    -- MIGUI command enable
+    APP_CMD             : in  slv3;     -- MIGUI command
+    APP_ADDR            : in  slv(MAWIDTH-1 downto 0); -- MIGUI address
+    APP_WDF_RDY         : out slbit;      -- MIGUI ready for data write
+    APP_WDF_WREN        : in  slbit;      -- MIGUI data write enable
+    APP_WDF_DATA        : in  slv(8*(2**BAWIDTH)-1 downto 0);-- MIGUI write data
+    APP_WDF_MASK        : in  slv((2**BAWIDTH)-1 downto 0);  -- MIGUI write mask
+    APP_WDF_END         : in  slbit;                         -- MIGUI write end
+    APP_RD_DATA_VALID   : out slbit;                         -- MIGUI read valid
+    APP_RD_DATA         : out slv(8*(2**BAWIDTH)-1 downto 0);-- MIGUI read data
+    APP_RD_DATA_END     : out slbit;                         -- MIGUI read end
+    APP_REF_REQ         : in  slbit;      -- MIGUI refresh request
+    APP_ZQ_REQ          : in  slbit;      -- MIGUI ZQ calibrate request
+    APP_REF_ACK         : out slbit;      -- MIGUI refresh acknowledge
+    APP_ZQ_ACK          : out slbit       -- MIGUI ZQ calibrate acknowledge
+  );
+end migui_core_gsim;
+
+
+architecture sim of migui_core_gsim is
+  
+  constant mwidth : positive   := 2**BAWIDTH;    -- mask width (8 or 16)
+  constant dwidth : positive   := 8*mwidth;      -- data width (64 or 128)
+
+  -- row/col split only relevant for timing simulation
+  -- use 16kbit->2kByte column width as used in MT41K128M16 on arty board
+  constant colwidth : positive := 11;
+  constant rowwidth : positive := MAWIDTH-colwidth;
+  subtype  addr_f_row is integer range MAWIDTH-1 downto colwidth;
+
+  subtype bv8 is bit_vector(7 downto 0);
+  constant memsize : positive := 2**SAWIDTH;
+  constant datzero : bv8 := (others=>'0');
+  type ram_type is array (0 to memsize-1) of bv8;
+  
+  -- timing constants
+  constant c_rdwait_rhit : positive :=  2; -- read wait row match
+  constant c_rdwait_rmis : positive :=  5; -- read wait row miss
+  constant c_wrwait_rhit : positive :=  2; -- write wait row match
+  constant c_wrwait_rmis : positive :=  5; -- write wait row miss
+  constant c_wrwait_max  : positive := c_wrwait_rmis; -- write wait maximum
+  -- the REF and ZQ delays are as observed for arty board
+  constant c_refwait     : positive := 10;    -- REF_REQ to REF_ACK delay
+  constant c_zqwait      : positive :=  8;    -- ZQ_REQ  to ZQ_ACK  delay
+  -- the RDY pattern gives 23% busy (4 out of 13 cycles)
+  -- good enough for simulation; observed pattern on arty shows ~6% busy,
+  constant c_crdy_init   : slv13    := "0001111110111";  -- block 4 of 13;
+
+  type regs_type is record
+    cacowait : natural;                  -- CACO wait down counter
+    enacaco  : slbit;                    -- CACO enable
+    enardy   : slbit;                    -- RDY  enable
+    rowaddr  : slv(rowwidth-1 downto 0); -- current row address
+    rdwait   : natural;                  -- read wait cycles pending
+    wrwait   : natural;                  -- write wait cycles pending
+    crdypat  : slv13;                    -- crdy pattern
+    refwait  : natural;                  -- req_ack wait counter
+    zqwait   : natural;                  -- zq_ack  wait counter
+  end record regs_type;
+  
+  constant rowaddr_init   : slv(rowwidth-1 downto 0) := (others=>'1');
+
+  constant regs_init : regs_type := (
+    CACO_WAIT,'0','0',                  -- cacowait,enacaco,enardy
+    rowaddr_init,                       -- rowaddr
+    0,0,                                -- rdwait,wrwait
+    c_crdy_init,                        -- crdypat
+    0,0                                 -- refwait,zqwait
+  );
+
+  signal CLK : slbit;                   -- local copy of UI_CLK
+
+  signal R_REGS : regs_type := regs_init;
+  signal N_REGS : regs_type;            -- don't init (vivado fix for fsm infer)
+  
+  signal CLKFX : slbit;
+
+  signal MEM_EN : slbit := '0';         -- sim mem enable
+  signal MEM_WE : slbit := '0';         -- sim mem write enable
+  signal MEM_ADDR : slv(SAWIDTH-BAWIDTH-1 downto 0); -- sim mem base address
+  signal R_MEMDO  : slv(dwidth-1 downto 0) := (others=>'0');
+
+
+begin
+  
+  assert BAWIDTH = 3 or BAWIDTH = 4
+    report "assert( BAWIDTH = 3 or 4 )"
+    severity failure;
+  
+  UICLKGEN : sfs_gsim_core              -- mig ui clock generator
+    generic map (
+      VCO_DIVIDE   => 1,
+      VCO_MULTIPLY => CLKMUI_MUL,
+      OUT_DIVIDE   => CLKMUI_DIV)
+    port map (
+      CLKIN  => SYS_CLK,
+      CLKFX  => CLKFX,
+      LOCKED => open
+    );
+
+  CLK    <= CLKFX;                      -- !! copy both local CLK and exported 
+  UI_CLK <= CLKFX;                      -- !! UI_CLK to avoid delta cycle diff
+  UI_CLK_SYNC_RST <= '0';
+  
+  proc_regs: process (CLK)
+  begin
+
+    if rising_edge(CLK) then
+      if SYS_RST = '1' then
+        R_REGS <= regs_init;
+      else
+        R_REGS <= N_REGS;
+      end if;
+    end if;
+
+  end process proc_regs;
+
+  proc_next: process (R_REGS, APP_EN, APP_ADDR, APP_CMD,
+                      APP_WDF_WREN, APP_WDF_END,
+                      APP_REF_REQ,APP_ZQ_REQ, R_MEMDO)
+
+    variable r : regs_type := regs_init;
+    variable n : regs_type := regs_init;
+
+    variable iappcrdy   : slbit := '0';
+    variable iappwrdy   : slbit := '0';
+    variable iapprefack : slbit := '0';
+    variable iappzqack  : slbit := '0';
+    variable imemen  : slbit := '0';
+    variable imemwe  : slbit := '0';
+    variable irdval  : slbit := '0';
+
+  begin
+
+    r := R_REGS;
+    n := R_REGS;
+
+    iappcrdy   := '1';
+    iappwrdy   := '1';
+    iapprefack := '0';
+    iappzqack  := '0';
+    imemen   := '0';
+    imemwe   := '0';
+    irdval   := '0';
+
+    n.crdypat := r.crdypat(11 downto 0) & r.crdypat(12); -- circular right shift
+
+    -- simulate CACO wait
+    if r.cacowait > 0 then
+      n.cacowait := r.cacowait - 1;
+      if r.cacowait <= CACO_WAIT/2 then         -- half of CACO wait reached ?
+        n.enardy := '1';                          -- enable RDY's
+      end if;
+      if r.cacowait = 1 then                    -- CACO wait ended ?
+        n.enacaco := '1';                         -- assert CACO
+      end if;
+    end if;
+    
+    -- process cmd requests
+    if r.wrwait >= c_wrwait_max then
+      iappcrdy := '0';
+      iappwrdy := '0';
+    elsif r.rdwait > 0 then
+      iappcrdy := '0';
+    elsif r.enardy='0' or r.crdypat(0)='0' then
+      iappcrdy := '0';
+      
+    else      
+      if APP_EN = '1' then
+        if APP_CMD = c_migui_cmd_read then
+          imemen := '1';
+          if r.rowaddr = APP_ADDR(addr_f_row) then
+            n.rdwait  := r.rdwait + c_rdwait_rhit;
+          else
+            n.rdwait  := r.rdwait + c_rdwait_rmis;
+            n.rowaddr := APP_ADDR(addr_f_row);
+          end if;
+        elsif APP_CMD = c_migui_cmd_write then
+          imemen := '1';
+          imemwe := '1';
+          if r.rowaddr = APP_ADDR(addr_f_row) then
+            n.wrwait  := r.wrwait + c_wrwait_rhit;
+          else
+            n.wrwait  := r.wrwait + c_wrwait_rmis;
+            n.rowaddr := APP_ADDR(addr_f_row);
+          end if;
+        else
+        end if;
+      end if;      
+    end if;
+
+    -- handle cmd waits, issue read responses
+    if r.enacaco = '1' then               -- process commands only after CACO
+      if r.wrwait > 0 then                  -- first wait for pending writes
+        n.wrwait := r.wrwait - 1;
+      else
+        if r.rdwait > 0 then                -- next of for pending reads
+          n.rdwait := r.rdwait - 1;
+          if r.rdwait = 1 then
+            irdval := '1';
+          end if;
+        end if;
+      end if;      
+    end if;
+    
+    -- process ref_req requests
+    if APP_REF_REQ = '1' then
+      n.refwait := c_refwait;
+    else
+      if r.refwait > 0 then
+        n.refwait := r.refwait -1;
+        if r.refwait = 1 then
+          iapprefack := '1';
+        end if;
+      end if;
+    end if;
+    
+    -- process zq_req requests
+    if APP_ZQ_REQ = '1' then
+      n.zqwait := c_zqwait;
+    else
+      if r.zqwait > 0 then
+        n.zqwait := r.zqwait -1;
+        if r.zqwait = 1 then
+          iappzqack := '1';
+        end if;
+      end if;
+    end if;
+    
+    N_REGS <= n;
+
+    INIT_CALIB_COMPLETE <= r.enacaco;
+    
+    APP_RDY           <= iappcrdy;
+    APP_WDF_RDY       <= iappwrdy;
+    APP_RD_DATA_VALID <= irdval;
+    APP_RD_DATA_END   <= irdval;
+    APP_REF_ACK       <= iapprefack;
+    APP_ZQ_ACK        <= iappzqack;
+    if irdval = '1' then                -- only in the RD_DATA_END cycle
+      APP_RD_DATA <= R_MEMDO;             -- export the data
+    else                                -- otherwise
+      APP_RD_DATA <= (others=>'1');       -- send all ones
+    end if;
+    MEM_EN     <= imemen;
+    MEM_WE     <= imemwe;
+    MEM_ADDR   <= APP_ADDR(SAWIDTH-1 downto BAWIDTH);
+
+  end process proc_next;
+
+  proc_mem: process (CLK)
+    variable ram : ram_type := (others=>datzero);
+    variable membase : integer := 0;
+  begin
+    if rising_edge(CLK) then
+      if MEM_EN = '1' then
+        membase := mwidth*to_integer(unsigned(MEM_ADDR));
+        -- write to memory
+        if APP_WDF_WREN = '1' then
+          for i in 0 to mwidth-1 loop
+            if APP_WDF_MASK(i) = '0'  then      -- WE = not MASK !!
+              ram(membase + i) :=
+                to_bitvector(to_x01(APP_WDF_DATA(8*i+7 downto 8*i)));
+            end if;
+          end loop;
+        end if;
+        -- read from memory
+        for i in 0 to mwidth-1 loop
+          R_MEMDO(8*i+7 downto 8*i) <= to_stdlogicvector(ram(membase + i));
+        end loop;
+        
+      end if;
+    end if;
+  end process proc_mem;
+
+  proc_moni: process (CLK)
+  begin
+    if rising_edge(CLK) then
+      if SYS_RST = '0' then
+        if APP_EN = '1' then
+          assert APP_CMD = c_migui_cmd_read or
+                 APP_CMD = c_migui_cmd_write
+            report "migui_core_gsim: FAIL: APP_CMD not 000 or 001"
+            severity error;
+          
+          assert unsigned(APP_ADDR(MAWIDTH-1 downto SAWIDTH)) = 0
+            report "migui_core_gsim: FAIL: out of sim-memory size access"
+            severity error;
+        end if;
+
+        if APP_EN = '1' and APP_CMD = c_migui_cmd_write then 
+          assert APP_WDF_WREN='1' and APP_WDF_END='1'
+            report "migui_core_gsim: FAIL: APP_WDF_(END,WREN) missed on write"
+            severity error;
+        else
+          assert APP_WDF_WREN='0' and APP_WDF_END='0'
+            report "migui_core_gsim: FAIL: spurious APP_WDF_(END,WREN)"
+            severity error;
+        end if;
+      end if;
+    end if;
+  end process proc_moni;
+
+end sim;
--- a/rtl/vlib/cdclib/cdc_signal_s1_as.vbom
+++ b/rtl/vlib/cdclib/cdc_signal_s1_as.vbom
@@ -0,0 +1,4 @@
+# libs
+../slvtypes.vhd
+# design
+cdc_signal_s1_as.vhd
--- a/rtl/vlib/cdclib/cdc_signal_s1_as.vhd
+++ b/rtl/vlib/cdclib/cdc_signal_s1_as.vhd
@@ -0,0 +1,68 @@
+-- $Id: cdc_signal_s1_as.vhd 984 2018-01-02 20:56:27Z mueller $
+--
+-- Copyright 2016- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
+--
+-- This program is free software; you may redistribute and/or modify it under
+-- the terms of the GNU General Public License as published by the Free
+-- Software Foundation, either version 3, or (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful, but
+-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
+-- or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for complete details.
+-- 
+------------------------------------------------------------------------------
+-- Module Name:    cdc_signal_s1_as - syn
+-- Description:    clock domain crossing for a signal, 2 stage, asyn input
+--
+-- Dependencies:   -
+-- Test bench:     -
+-- Target Devices: generic
+-- Tool versions:  viv 2016.2; ghdl 0.33
+-- Revision History: 
+-- Date         Rev Version    Comment
+-- 2016-06-10   774   1.0      Initial version (copy of cdc_signal_s1)
+-- 
+------------------------------------------------------------------------------
+-- Logic is identical to cdc_signal_s1 !
+-- but no scoped xdc with max_delay for input associated
+--
+library ieee;
+use ieee.std_logic_1164.all;
+
+use work.slvtypes.all;
+
+entity cdc_signal_s1_as is               -- cdc for signal (2 stage), asyn input
+  generic (
+    INIT : slbit := '0');               -- initial state
+  port (
+    CLKO : in slbit;                     -- O|output clock
+    DI   : in slbit;                     -- I|input data
+    DO   : out slbit                     -- O|output data
+  );
+end entity cdc_signal_s1_as;
+
+
+architecture syn of cdc_signal_s1_as is
+
+  signal R_DO_S0 : slbit := INIT;
+  signal R_DO_S1 : slbit := INIT;
+
+  attribute ASYNC_REG: string;
+
+  attribute ASYNC_REG of R_DO_S0   : signal is "true";
+  attribute ASYNC_REG of R_DO_S1   : signal is "true";
+
+begin
+
+  proc_regs: process (CLKO)
+  begin
+    if rising_edge(CLKO) then
+      R_DO_S0 <= DI;                -- synch 0: CLKI->CLKO
+      R_DO_S1 <= R_DO_S0;           -- synch 1: CLKO
+    end if;
+  end process proc_regs;
+
+  DO <= R_DO_S1;
+
+end syn;
--- a/rtl/vlib/xlib/s7_cmt_sfs_2_gsim.vbom
+++ b/rtl/vlib/xlib/s7_cmt_sfs_2_gsim.vbom
@@ -0,0 +1,7 @@
+# libs
+../slvtypes.vhd
+xlib.vhd
+# components
+sfs_gsim_core.vbom
+# design
+s7_cmt_sfs_2_gsim.vhd
--- a/rtl/vlib/xlib/s7_cmt_sfs_2_gsim.vhd
+++ b/rtl/vlib/xlib/s7_cmt_sfs_2_gsim.vhd
@@ -0,0 +1,172 @@
+-- $Id: s7_cmt_sfs_2_gsim.vhd 1072 2018-11-18 22:27:35Z mueller $
+--
+-- Copyright 2018- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
+--
+-- This program is free software; you may redistribute and/or modify it under
+-- the terms of the GNU General Public License as published by the Free
+-- Software Foundation, either version 3, or (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful, but
+-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
+-- or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for complete details.
+--
+------------------------------------------------------------------------------
+-- Module Name:    s7_cmt_sfs_2 - sim
+-- Description:    Series-7 CMT  for dual-channel frequency synthesis
+--                 simple vhdl model, without Xilinx UNISIM primitives
+--
+-- Dependencies:   -
+-- Test bench:     -
+-- Target Devices: generic Series-7
+-- Tool versions:  viv 2017.2; ghdl 0.34
+--
+-- Revision History: 
+-- Date         Rev Version  Comment
+-- 2018-11-18  1072   1.0    Initial version (derived from s7_cmt_sfs_3_gsim)
+------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+use work.slvtypes.all;
+use work.xlib.all;
+
+entity s7_cmt_sfs_2 is                  -- 7-Series CMT for dual freq. synth.
+  generic (
+    VCO_DIVIDE   : positive := 1;       -- vco clock divide
+    VCO_MULTIPLY : positive := 1;       -- vco clock multiply 
+    OUT0_DIVIDE  : positive := 1;       -- output 0 divide
+    OUT1_DIVIDE  : positive := 1;       -- output 1 divide
+    CLKIN_PERIOD : real := 10.0;        -- CLKIN period (def is 10.0 ns)
+    CLKIN_JITTER : real := 0.01;        -- CLKIN jitter (def is 10 ps)
+    STARTUP_WAIT : boolean := false;    -- hold FPGA startup till LOCKED
+    GEN_TYPE     : string := "PLL");    -- PLL or MMCM
+  port (
+    CLKIN   : in slbit;                 -- clock input
+    CLKOUT0 : out slbit;                -- clock output 0
+    CLKOUT1 : out slbit;                -- clock output 1
+    LOCKED  : out slbit                 -- pll/mmcm locked
+  );
+end s7_cmt_sfs_2;
+
+
+architecture sim of s7_cmt_sfs_2 is
+  signal LOCKED0 : slbit := '1';
+  signal LOCKED1 : slbit := '1';
+begin
+
+  proc_init : process
+
+    -- currently frequency limits taken from Artix-7 speed grade -1
+    constant f_vcomin_pll  : integer :=  800;
+    constant f_vcomax_pll  : integer := 1600;
+    constant f_pdmin_pll   : integer :=   19;
+    constant f_pdmax_pll   : integer :=  450;
+
+    constant f_vcomin_mmcm : integer :=  600;
+    constant f_vcomax_mmcm : integer := 1200;
+    constant f_pdmin_mmcm  : integer :=   10;
+    constant f_pdmax_mmcm  : integer :=  450;
+
+    variable t_vco : Delay_length := 0 ns;
+    variable t_vcomin : Delay_length := 0 ns;
+    variable t_vcomax : Delay_length := 0 ns;
+    variable t_pd : Delay_length := 0 ns;
+    variable t_pdmin : Delay_length := 0 ns;
+    variable t_pdmax : Delay_length := 0 ns;
+
+  begin
+    
+    -- validate generics
+    if not (GEN_TYPE = "PLL" or GEN_TYPE = "MMCM") then
+      report "assert(GEN_TYPE='PLL' or GEN_TYPE='MMCM')"
+        severity failure;
+    end if;
+
+    if VCO_DIVIDE/=1 or VCO_MULTIPLY/=1 or
+       OUT0_DIVIDE/=1 or OUT1_DIVIDE/=1 then
+
+      if GEN_TYPE = "PLL" then
+        -- check DIV/MULT parameter range
+        if VCO_DIVIDE<1   or VCO_DIVIDE>56 or
+          VCO_MULTIPLY<2 or VCO_MULTIPLY>64 or
+          OUT0_DIVIDE<1   or OUT0_DIVIDE>128 or
+          OUT1_DIVIDE<1   or OUT1_DIVIDE>128
+        then
+          report
+          "assert(VCO_DIVIDE in 1:56 VCO_MULTIPLY in 2:64 OUTx_DIVIDE in 1:128)"
+            severity failure;
+        end if;
+        -- setup VCO and PD range check boundaries
+        t_vcomin := (1000 ns / f_vcomax_pll) - 1 ps;
+        t_vcomax := (1000 ns / f_vcomin_pll) + 1 ps;
+        t_pdmin  := (1000 ns / f_pdmax_pll) - 1 ps;
+        t_pdmax  := (1000 ns / f_pdmin_pll) + 1 ps;
+
+      end if; -- GEN_TYPE = "PLL"
+
+      if GEN_TYPE = "MMCM" then
+        -- check DIV/MULT parameter range
+        if VCO_DIVIDE<1   or VCO_DIVIDE>106 or
+           VCO_MULTIPLY<2 or VCO_MULTIPLY>64 or
+           OUT0_DIVIDE<1   or OUT0_DIVIDE>128 or
+           OUT1_DIVIDE<1   or OUT1_DIVIDE>128
+        then
+          report
+          "assert(VCO_DIVIDE in 1:106 VCO_MULTIPLY in 2:64 OUTx_DIVIDE in 1:128)"
+            severity failure;
+        end if;
+        -- setup VCO and PD range check boundaries
+        t_vcomin := (1000 ns / f_vcomax_mmcm) - 1 ps;
+        t_vcomax := (1000 ns / f_vcomin_mmcm) + 1 ps;
+        t_pdmin  := (1000 ns / f_pdmax_mmcm) - 1 ps;
+        t_pdmax  := (1000 ns / f_pdmin_mmcm) + 1 ps;
+
+      end if; -- GEN_TYPE = "MMCM"
+
+      -- now common check whether VCO and PD frequency is in range
+      t_pd  := (1 ps * (1000.0*CLKIN_PERIOD)) * VCO_DIVIDE;
+      t_vco := t_pd / VCO_MULTIPLY;
+
+      if t_vco<t_vcomin or t_vco>t_vcomax then
+        report "assert(VCO frequency out of range)"
+          severity failure;
+      end if;
+      
+      if t_pd<t_pdmin or t_pd>t_pdmax then
+        report "assert(PD frequency out of range)"
+          severity failure;
+      end if;
+
+    end if;  -- one factor /= 1
+      
+    wait;
+  end process proc_init;
+
+  -- generate clock
+  SFS0: sfs_gsim_core
+    generic map (
+      VCO_DIVIDE   => VCO_DIVIDE,
+      VCO_MULTIPLY => VCO_MULTIPLY,
+      OUT_DIVIDE   => OUT0_DIVIDE)
+    port map (
+      CLKIN   => CLKIN,
+      CLKFX   => CLKOUT0,
+      LOCKED  => LOCKED0
+    );
+  
+  SFS1: sfs_gsim_core
+    generic map (
+      VCO_DIVIDE   => VCO_DIVIDE,
+      VCO_MULTIPLY => VCO_MULTIPLY,
+      OUT_DIVIDE   => OUT1_DIVIDE)
+    port map (
+      CLKIN   => CLKIN,
+      CLKFX   => CLKOUT1,
+      LOCKED  => LOCKED1
+    );
+  
+  LOCKED <= LOCKED0 and LOCKED1;
+  
+end sim;
--- a/rtl/vlib/xlib/s7_cmt_sfs_2_unisim.vbom
+++ b/rtl/vlib/xlib/s7_cmt_sfs_2_unisim.vbom
@@ -0,0 +1,5 @@
+# libs
+../slvtypes.vhd
+@lib:unisim
+# design
+s7_cmt_sfs_2_unisim.vhd
--- a/rtl/vlib/xlib/s7_cmt_sfs_2_unisim.vhd
+++ b/rtl/vlib/xlib/s7_cmt_sfs_2_unisim.vhd
@@ -0,0 +1,220 @@
+-- $Id: s7_cmt_sfs_2_unisim.vhd 1072 2018-11-18 22:27:35Z mueller $
+--
+-- Copyright 2018- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
+--
+-- This program is free software; you may redistribute and/or modify it under
+-- the terms of the GNU General Public License as published by the Free
+-- Software Foundation, either version 3, or (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful, but
+-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
+-- or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+-- for complete details.
+--
+------------------------------------------------------------------------------
+-- Module Name:    s7_cmt_sfs_2 - syn
+-- Description:    Series-7 CMT for dual frequency synthesis
+--                 Direct instantiation of Xilinx UNISIM primitives
+--
+-- Dependencies:   -
+-- Test bench:     -
+-- Target Devices: generic Series-7
+-- Tool versions:  viv 2017.2; ghdl 0.34
+--
+-- Revision History: 
+-- Date         Rev Version  Comment
+-- 2018-11-18  1072   1.0    Initial version (derived from s7_cmt_sfs_3_unisim)
+------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+library unisim;
+use unisim.vcomponents.ALL;
+
+use work.slvtypes.all;
+
+entity s7_cmt_sfs_2 is                  -- 7-Series CMT for dual freq. synth.
+  generic (
+    VCO_DIVIDE   : positive := 1;       -- vco clock divide
+    VCO_MULTIPLY : positive := 1;       -- vco clock multiply 
+    OUT0_DIVIDE  : positive := 1;       -- output divide
+    OUT1_DIVIDE  : positive := 1;       -- output divide
+    CLKIN_PERIOD : real := 10.0;        -- CLKIN period (def is 10.0 ns)
+    CLKIN_JITTER : real := 0.01;        -- CLKIN jitter (def is 10 ps)
+    STARTUP_WAIT : boolean := false;    -- hold FPGA startup till LOCKED
+    GEN_TYPE     : string := "PLL");    -- PLL or MMCM
+  port (
+    CLKIN   : in slbit;                 -- clock input
+    CLKOUT0 : out slbit;                -- clock output 0
+    CLKOUT1 : out slbit;                -- clock output 1
+    LOCKED  : out slbit                 -- pll/mmcm locked
+  );
+end s7_cmt_sfs_2;
+
+
+architecture syn of s7_cmt_sfs_2 is
+
+begin
+    
+  assert GEN_TYPE = "PLL" or GEN_TYPE = "MMCM"
+    report "assert(GEN_TYPE='PLL' or GEN_TYPE='MMCM')"
+    severity failure;
+
+  NOGEN: if VCO_DIVIDE=1 and VCO_MULTIPLY=1 and
+            OUT0_DIVIDE=1 and OUT1_DIVIDE=1 generate
+    CLKOUT0 <= CLKIN;
+    CLKOUT1 <= CLKIN;
+    LOCKED  <= '1';
+  end generate NOGEN;
+
+  USEPLL: if GEN_TYPE = "PLL" and
+            not (VCO_DIVIDE=1 and VCO_MULTIPLY=1 and
+                 OUT0_DIVIDE=1 and OUT1_DIVIDE=1) generate
+
+    signal CLKFBOUT         : slbit;
+    signal CLKFBOUT_BUF     : slbit;
+    signal CLKOUT0_PLL      : slbit;
+    signal CLKOUT1_PLL      : slbit;
+    signal CLKOUT2_UNUSED   : slbit;
+    signal CLKOUT3_UNUSED   : slbit;
+    signal CLKOUT4_UNUSED   : slbit;
+    signal CLKOUT5_UNUSED   : slbit;
+    signal CLKOUT6_UNUSED   : slbit;
+
+    pure function bool2string (val : boolean) return string is
+    begin
+      if val then
+        return "TRUE";
+      else
+        return "FALSE";
+      end if;
+    end function bool2string;
+      
+  begin
+
+    PLL : PLLE2_BASE
+      generic map (
+        BANDWIDTH            => "OPTIMIZED",
+        DIVCLK_DIVIDE        => VCO_DIVIDE,
+        CLKFBOUT_MULT        => VCO_MULTIPLY,
+        CLKFBOUT_PHASE       => 0.000,
+        CLKOUT0_DIVIDE       => OUT0_DIVIDE,
+        CLKOUT0_PHASE        => 0.000,
+        CLKOUT0_DUTY_CYCLE   => 0.500,
+        CLKOUT1_DIVIDE       => OUT1_DIVIDE,
+        CLKOUT1_PHASE        => 0.000,
+        CLKOUT1_DUTY_CYCLE   => 0.500,
+        CLKIN1_PERIOD        => CLKIN_PERIOD,
+        REF_JITTER1          => CLKIN_JITTER,
+        STARTUP_WAIT         => bool2string(STARTUP_WAIT))
+      port map (
+        CLKFBOUT            => CLKFBOUT,
+        CLKOUT0             => CLKOUT0_PLL,
+        CLKOUT1             => CLKOUT1_PLL,
+        CLKOUT2             => CLKOUT2_UNUSED,
+        CLKOUT3             => CLKOUT3_UNUSED,
+        CLKOUT4             => CLKOUT4_UNUSED,
+        CLKOUT5             => CLKOUT5_UNUSED,
+        CLKFBIN             => CLKFBOUT_BUF,
+        CLKIN1              => CLKIN,
+        LOCKED              => LOCKED,
+        PWRDWN              => '0',
+        RST                 => '0'
+      );
+
+    BUFG_CLKFB : BUFG
+      port map (
+        I => CLKFBOUT,
+        O => CLKFBOUT_BUF
+      );
+
+    BUFG_CLKOUT0 : BUFG
+      port map (
+        I => CLKOUT0_PLL,
+        O => CLKOUT0
+      );
+    BUFG_CLKOUT1 : BUFG
+      port map (
+        I => CLKOUT1_PLL,
+        O => CLKOUT1
+      );
+
+  end generate USEPLL;
+   
+  USEMMCM: if GEN_TYPE = "MMCM" and
+             not (VCO_DIVIDE=1 and VCO_MULTIPLY=1 and
+                  OUT0_DIVIDE=1 and OUT1_DIVIDE=1) generate
+
+    signal CLKFBOUT         : slbit;
+    signal CLKFBOUT_BUF     : slbit;
+    signal CLKFBOUTB_UNUSED : slbit;
+    signal CLKOUT0_MMCM     : slbit;
+    signal CLKOUT0B_UNUSED  : slbit;
+    signal CLKOUT1_MMCM     : slbit;
+    signal CLKOUT1B_UNUSED  : slbit;
+    signal CLKOUT2_UNUSED   : slbit;
+    signal CLKOUT2B_UNUSED  : slbit;
+    signal CLKOUT3_UNUSED   : slbit;
+    signal CLKOUT3B_UNUSED  : slbit;
+    signal CLKOUT4_UNUSED   : slbit;
+    signal CLKOUT5_UNUSED   : slbit;
+    signal CLKOUT6_UNUSED   : slbit;
+
+  begin
+
+    MMCM : MMCME2_BASE
+      generic map (
+        BANDWIDTH            => "OPTIMIZED",
+        DIVCLK_DIVIDE        => VCO_DIVIDE,
+        CLKFBOUT_MULT_F      => real(VCO_MULTIPLY),
+        CLKFBOUT_PHASE       => 0.000,
+        CLKOUT0_DIVIDE_F     => real(OUT0_DIVIDE),
+        CLKOUT0_PHASE        => 0.000,
+        CLKOUT0_DUTY_CYCLE   => 0.500,
+        CLKOUT1_DIVIDE       => OUT1_DIVIDE,
+        CLKOUT1_PHASE        => 0.000,
+        CLKOUT1_DUTY_CYCLE   => 0.500,
+        CLKIN1_PERIOD        => CLKIN_PERIOD,
+        REF_JITTER1          => CLKIN_JITTER,
+        STARTUP_WAIT         => STARTUP_WAIT)
+      port map (
+        CLKFBOUT            => CLKFBOUT,
+        CLKFBOUTB           => CLKFBOUTB_UNUSED,
+        CLKOUT0             => CLKOUT0_MMCM,
+        CLKOUT0B            => CLKOUT0B_UNUSED,
+        CLKOUT1             => CLKOUT1_MMCM,
+        CLKOUT1B            => CLKOUT1B_UNUSED,
+        CLKOUT2             => CLKOUT2_UNUSED,
+        CLKOUT2B            => CLKOUT2B_UNUSED,
+        CLKOUT3             => CLKOUT3_UNUSED,
+        CLKOUT3B            => CLKOUT3B_UNUSED,
+        CLKOUT4             => CLKOUT4_UNUSED,
+        CLKOUT5             => CLKOUT5_UNUSED,
+        CLKFBIN             => CLKFBOUT_BUF,
+        CLKIN1              => CLKIN,
+        LOCKED              => LOCKED,
+        PWRDWN              => '0',
+        RST                 => '0'
+      );
+
+    BUFG_CLKFB : BUFG
+      port map (
+        I => CLKFBOUT,
+        O => CLKFBOUT_BUF
+      );
+
+    BUFG_CLKOUT0 : BUFG
+      port map (
+        I => CLKOUT0_MMCM,
+        O => CLKOUT0
+      );
+    BUFG_CLKOUT1 : BUFG
+      port map (
+        I => CLKOUT1_MMCM,
+        O => CLKOUT1
+      );
+    
+  end generate USEMMCM;
+   
+end syn;
--- a/rtl/vlib/xlib/xlib.vhd
+++ b/rtl/vlib/xlib/xlib.vhd
@@ -1,4 +1,4 @@
-- $Id: xlib.vhd 1065 2018-11-04 11:32:06Z mueller $
+-- $Id: xlib.vhd 1072 2018-11-18 22:27:35Z mueller $
 --
 -- Copyright 2007-2018 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
 --
@@ -19,6 +19,7 @@
 -- Tool versions:  ise 8.2-14.7; viv 2014.4-2018.2; ghdl 0.18-0.34
 -- Revision History: 
 -- Date         Rev Version  Comment
+-- 2018-11-18  1072   1.1.1  add s7_cmt_sfs_3 and s7_cmt_sfs_2
 -- 2018-11-03  1064   1.1    add sfs_gsim_core
 -- 2016-04-02   758   1.0.11 add usr_access_unisim
 -- 2013-10-06   538   1.0.10 add s6_cmt_sfs
@@ -200,6 +201,44 @@ component s7_cmt_sfs is                 -- 7-Series CMT for simple freq. synth.
  );
 end component;

+component s7_cmt_sfs_2 is               -- 7-Series CMT for dual freq. synth.
+  generic (
+    VCO_DIVIDE   : positive := 1;       -- vco clock divide
+    VCO_MULTIPLY : positive := 1;       -- vco clock multiply 
+    OUT0_DIVIDE  : positive := 1;       -- output 0 divide
+    OUT1_DIVIDE  : positive := 1;       -- output 1 divide
+    CLKIN_PERIOD : real := 10.0;        -- CLKIN period (def is 10.0 ns)
+    CLKIN_JITTER : real := 0.01;        -- CLKIN jitter (def is 10 ps)
+    STARTUP_WAIT : boolean := false;    -- hold FPGA startup till LOCKED
+    GEN_TYPE     : string := "PLL");    -- PLL or MMCM
+  port (
+    CLKIN   : in slbit;                 -- clock input
+    CLKOUT0 : out slbit;                -- clock output 0
+    CLKOUT1 : out slbit;                -- clock output 1
+    LOCKED  : out slbit                 -- pll/mmcm locked
+  );
+end component;
+
+component s7_cmt_sfs_3 is               -- 7-Series CMT for tripple freq. synth.
+  generic (
+    VCO_DIVIDE   : positive := 1;       -- vco clock divide
+    VCO_MULTIPLY : positive := 1;       -- vco clock multiply 
+    OUT0_DIVIDE  : positive := 1;       -- output 0 divide
+    OUT1_DIVIDE  : positive := 1;       -- output 1 divide
+    OUT2_DIVIDE  : positive := 1;       -- output 2 divide
+    CLKIN_PERIOD : real := 10.0;        -- CLKIN period (def is 10.0 ns)
+    CLKIN_JITTER : real := 0.01;        -- CLKIN jitter (def is 10 ps)
+    STARTUP_WAIT : boolean := false;    -- hold FPGA startup till LOCKED
+    GEN_TYPE     : string := "PLL");    -- PLL or MMCM
+  port (
+    CLKIN   : in slbit;                 -- clock input
+    CLKOUT0 : out slbit;                -- clock output 0
+    CLKOUT1 : out slbit;                -- clock output 1
+    CLKOUT2 : out slbit;                -- clock output 2
+    LOCKED  : out slbit                 -- pll/mmcm locked
+  );
+end component;
+
 component s6_cmt_sfs is                 -- Spartan-6 CMT for simple freq. synth.
  generic (
    VCO_DIVIDE   : positive := 1;       -- vco clock divide
--- a/tools/vivado/viv_tools_build.tcl
+++ b/tools/vivado/viv_tools_build.tcl
@@ -1,10 +1,11 @@
-# $Id: viv_tools_build.tcl 1072 2018-11-18 22:27:35Z mueller $
+# $Id: viv_tools_build.tcl 1090 2018-12-21 12:17:35Z mueller $
 #
 # Copyright 2015-2018 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
 # License disclaimer see License.txt in $RETROBASE directory
 #
 # Revision History:
 # Date         Rev Version  Comment
+# 2018-12-19  1090   1.2.3  export log and rpt generated in OOC synthesis runs
 # 2018-11-18  1072   1.2.2  increase message limits (all 200, some 5000)
 # 2016-09-18   809   1.2.1  keep hierarchy for synthesis only runs 
 # 2016-05-22   767   1.2    cleaner setup handling; use explore flows
@@ -234,6 +235,19 @@ proc rvtb_default_build {stem step} {
  rvtb_cp_file "$path_syn1/${stem}_utilization_synth.rpt" "${stem}_syn_util.rpt"
  rvtb_cp_file "$path_syn1/${stem}.dcp"                   "${stem}_syn.dcp"

+  # export log and syn_util generated in OOC synthesis runs
+  set ooc_dirs [glob -nocomplain -dir $path_runs -tails -type d "*_synth_1"]
+  foreach ooc_dir $ooc_dirs {
+    puts "# process OOC build $ooc_dir"
+    set ooc_core [regsub -- {_synth_1$} $ooc_dir {}]
+    rvtb_cp_file \
+      "${path_runs}/${ooc_dir}/runme.log" \
+      "${stem}_${ooc_core}_syn.log"
+    rvtb_cp_file \
+      "${path_runs}/${ooc_dir}/${ooc_core}_utilization_synth.rpt" \
+      "${stem}_${ooc_core}_syn_util.rpt"
+  }
+  
  if {$step eq "syn"} {return [rvtb_build_check $step]}

  # build: implement -------------------------------------------------