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docu and comment updates [skip ci]
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@@ -13,10 +13,12 @@ ones are listed here:
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- instruction behavior
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- [SimH: `SPL` doesn't have 11/70 behavior](simh_diff_spl.md)
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- [SimH: State of N and Z and registers after a `DIV` abort with `V=1`](simh_diff_div_after_v1.md)
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- [SimH: `JSR SP` pushes modified `SP` value](simh_diff_jsr_sp.md)
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- stack limit and stack error behavior
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- [SimH: stack limit check and addressing modes](simh_diff_stklim_amode.md)
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- [SimH: stack limit check and vector push aborts](simh_diff_stklim_vpush.md)
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- [SimH: Red stack zone PSW protection](simh_diff_red_psw.md)
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- [SimH: No unconditional instruction fetch after stack error abort](simh_diff_ser_forced_fetch.md)
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- instruction abort handling
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- [SimH: condition codes are not always unchanged after an abort](simh_diff_cc_and_aborts.md)
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- service order and trap handling
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@@ -29,3 +31,6 @@ ones are listed here:
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- [SimH: MMU traps not suppressed when MMU register accessed](simh_diff_mmu_trap_suppression.md)
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- [SimH: The 'instruction completed flag' in `MMR0` is not implemented](simh_diff_instruction_complete.md)
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- [SimH: MMU aborts have priority over NXM aborts](simh_diff_mmu_nxm_prio.md)
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- not implemented 11/70 features
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- [SimH: 18-bit UNIBUS address space not mapped](simh_diff_unibus_mapping.md)
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- [SimH: MMU maintenance mode not implemented](simh_diff_mmu_no_maint.md)
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