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conclude cc and abort review, accept s_opg_gen handling

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- tools/tcode/cpu_details.mac: add B3.4
This commit is contained in:
wfjm
2023-01-03 09:27:13 +01:00
parent 26daa71634
commit 6831d1cda5
3 changed files with 93 additions and 7 deletions
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10
doc/ECO-039-cc_and_aborts.md
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@@ -52,6 +52,16 @@ In a second round, the `MTP*` and `MFP*` instructions, which use the `dsta`
flow, were fixed. Again, the `ndpcntl.psr_ccwe := '1';` was moved to the
last `*_w` state of the respective flows.
The condition code update for `dstr` flows, used by general operate instructions
like `BIS` or `INC`, is done in state `s_opg_gen` _before_ the concluding write
of the _read-modify-write_ sequence. This is considered acceptable since all
address errors have already been caught before in the read phase. The only
possible cause for aborting of the write phase is an `ibus` timeout. This is
highly unlikely since reading the same register worked. In addition,
instructions that access `ibus` registers shouldn't be re-executed anyway since
device registers don't have memory semantics and a read operation can already
change the device state.
### Hindsight
Further analysis showed that this bug had in practice no consequences
- `MOV` and `CLR` don't depend on the cc state, so a re-execution with a

9
rtl/w11a/pdp11_sequencer.vhd
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@@ -1,4 +1,4 @@
-- $Id: pdp11_sequencer.vhd 1342 2023-01-02 15:18:19Z mueller $
-- $Id: pdp11_sequencer.vhd 1343 2023-01-02 18:03:39Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2006-2023 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@@ -13,7 +13,7 @@
--
-- Revision History:
-- Date Rev Version Comment
-- 2023-01-01 1342 1.6.27 BUGFIX: cc state unchanged after abort
-- 2023-01-02 1342 1.6.27 BUGFIX: cc state unchanged after abort
-- 2022-12-26 1337 1.6.26 tbit logic overhaul 2, now fully 11/70 compatible
-- 2022-12-12 1330 1.6.25 implement MMR0,MMR2 instruction complete
-- 2022-12-10 1329 1.6.24 BUGFIX: get correct PS after vector push abort
@@ -1812,7 +1812,10 @@ begin
ndpcntl.gr_bytop := '0'; -- no bytop, do sign extend
end if;
ndpcntl.psr_ccwe := '1';
ndpcntl.psr_ccwe := '1'; -- acceptable even here though before the final
-- write which is a macc completion. That can
-- only fail due to a ibus timeout, all other
-- errors were caught during initial read.
if R_IDSTAT.is_dstw_reg = '1' then
ndpcntl.gr_we := '1';

81
tools/tcode/cpu_details.mac
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@@ -1,10 +1,10 @@
; $Id: cpu_details.mac 1342 2023-01-02 15:18:19Z mueller $
; $Id: cpu_details.mac 1343 2023-01-02 18:03:39Z mueller $
; SPDX-License-Identifier: GPL-3.0-or-later
; Copyright 2022-2023 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
;
; Revision History:
; Date Rev Version Comment
; 2023-01-02 1342 1.0 Initial version
; 2023-01-02 1343 1.0 Initial version
; 2022-07-18 1259 0.1 First draft
;
; Test CPU details
@@ -1550,6 +1550,9 @@ ta0404: mov #vhtbpt,v..bpt ; BPT handler
; part 4: check cc for MOV after abort for all modes
; B3.2 mtp and cc after abort
; B3.3 mfp and cc after abort
; B3.4 dstr flow and cc
; part 1: check cc for INC for all modes
; part 2: check cc for INC after abort for all modes
;
; Test B1: address mode torture tests +++++++++++++++++++++++++++++++++++++++
; This sub-section tests peculiar address node usage
@@ -1829,7 +1832,7 @@ tb0301: mov #123,r0 ; src for MOV
hcmpeq #cpnzvc,2(sp) ; check PS cc untouched
rti ; continue (possible here!)
;
4200$: hcmpeq #7.,r5 ; check that all 7 mov get address error
4200$: hcmpeq #7.,r5 ; check that all 7 mov got address error
mov #v..iit+2,v..iit ; restore
;
9999$: iot ; end of test B3.1
@@ -1878,6 +1881,76 @@ tb0303: cmpb systyp,#sy.sih ; skip on SimH
;
9999$: iot ; end of test B3.3
;
; Test B3.4 -- dstr flow and cc ++++++++++++++++++++++++++++++++++++++
; Verifies dstr flow and uses INC as easy to handle test case.
;
tb0304: clr r0 ; src for INC
mov #100$,r1 ; dst for (r1),(r1)+,-(r1),0(r1)
mov #200$,r2 ; dst for @(r2)+,@-(r2),@0(r2)
mov #cp.psw,r3 ; ptr to PSW
br 1000$
;
100$: .word 0 ; dst target
200$: .word 100$ ; ptr to dst
300$: .word 1 ; odd address ptr
;
; part 1: check cc for INC for all modes
;
1000$: scc
inc r0
hcmpeq #cp000c,(r3) ; NZV=0 and keep C
scc
inc (r1) ; mode 1
hcmpeq #cp000c,(r3) ; N=0,Z=0,V=0 and keep C
scc
inc (r1)+ ; mode 2
hcmpeq #cp000c,(r3) ; N=0,Z=0,V=0 and keep C
scc
inc -(r1) ; mode 4
hcmpeq #cp000c,(r3) ; N=0,Z=0,V=0 and keep C
scc
inc 0(r1) ; mode 6
hcmpeq #cp000c,(r3) ; N=0,Z=0,V=0 and keep C
scc
inc @(r2)+ ; mode 3
hcmpeq #cp000c,(r3) ; N=0,Z=0,V=0 and keep C
scc
inc @-(r2) ; mode 5
hcmpeq #cp000c,(r3) ; N=0,Z=0,V=0 and keep C
scc
inc @0(r2) ; mode 7
hcmpeq #cp000c,(r3) ; N=0,Z=0,V=0 and keep C
;
hcmpeq #7.,(r1) ; check that 7 inc's done
;
; part 2: check cc for INC after abort for all memory modes
;
2000$: clr r5
mov #2100$,v..iit ; set up iit handler
mov #1,r1 ; odd dst for (r1),(r1)+,-(r1),0(r1)
mov #300$,r2 ; odd dst for @(r2)+,@-(r2),@0(r2)
scc
;
inc (r1) ; mode 1
inc (r1)+ ; mode 2
mov #3,r1 ; restore r1
scc
inc -(r1) ; mode 4
inc 0(r1) ; mode 6
inc @(r2)+ ; mode 3
inc @-(r2) ; mode 5
inc @0(r2) ; mode 7
br 2200$
;
2100$: inc r5 ; bump counter
hcmpeq #cpnzvc,2(sp) ; check PS cc untouched
rti ; continue (possible here!)
;
2200$: hcmpeq #7.,r5 ; check that all 7 inc got address error
mov #v..iit+2,v..iit ; restore
;
9999$: iot ; end of test B3.4
;
; Section C: 11/70 specifics =================================================
; C1 Implementation differences
; C1.1 Register used as source and changed in dst flow
@@ -1936,7 +2009,7 @@ tc0103: mov #vhugen,v..iit ; set iit handler
; END OF ALL TESTS - loop closure ============================================
;
mov tstno,r0 ; hack, for easy monitoring ...
hcmpeq tstno,#32. ; all tests done ?
hcmpeq tstno,#33. ; all tests done ?
;
jmp loop
;