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add forgotten tb_c7_sram_memctl
This commit is contained in:
wfjm
11
rtl/bplib/cmoda7/tb/tb_c7_sram_memctl.vbom
Normal file
11
rtl/bplib/cmoda7/tb/tb_c7_sram_memctl.vbom
Normal file
@@ -0,0 +1,11 @@
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# libs
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../../../vlib/slvtypes.vhd
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../cmoda7lib.vhd
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../../../vlib/simlib/simlib.vhd
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# components
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../../../vlib/simlib/simclk.vbom
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../../../vlib/simlib/simclkcnt.vbom
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../../issi/is61wv5128bll.vbom
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${uut := ../c7_sram_memctl.vbom}
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# design
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tb_c7_sram_memctl.vhd
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334
rtl/bplib/cmoda7/tb/tb_c7_sram_memctl.vhd
Normal file
334
rtl/bplib/cmoda7/tb/tb_c7_sram_memctl.vhd
Normal file
@@ -0,0 +1,334 @@
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-- $Id: tb_c7_sram_memctl.vhd 984 2018-01-02 20:56:27Z mueller $
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--
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-- Copyright 2017- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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-- This program is free software; you may redistribute and/or modify it under
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-- the terms of the GNU General Public License as published by the Free
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-- Software Foundation, either version 3, or (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful, but
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-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
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-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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-- for complete details.
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--
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------------------------------------------------------------------------------
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-- Module Name: tb_c7_sram_memctl - sim
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-- Description: Test bench for c7_sram_memctl
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--
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-- Dependencies: vlib/simlib/simclk
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-- vlib/simlib/simclkcnt
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-- bplib/issi/is61wv5128bll
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-- c7_sram_memctl [UUT]
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--
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-- To test: c7_sram_memctl
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--
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-- Verified (with tb_c7_sram_memctl_stim.dat):
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-- Date Rev Code ghdl viv Target Comment
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-- 2017-06-11 912 _ssim 0.34 2017.1 xx xx
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--
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-- Target Devices: generic
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-- Tool versions: viv 2017.1; ghdl 0.34
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--
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-- Revision History:
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-- Date Rev Version Comment
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-- 2017-06-13 913 1.0 Initial version (derived from tb_s3_sram_memctl)
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------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.std_logic_textio.all;
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use std.textio.all;
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use work.slvtypes.all;
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use work.cmoda7lib.all;
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use work.simlib.all;
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entity tb_c7_sram_memctl is
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end tb_c7_sram_memctl;
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architecture sim of tb_c7_sram_memctl is
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signal CLK : slbit := '0';
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signal RESET : slbit := '0';
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signal REQ : slbit := '0';
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signal WE : slbit := '0';
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signal BUSY : slbit := '0';
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signal ACK_R : slbit := '0';
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signal ACK_W : slbit := '0';
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signal ACT_R : slbit := '0';
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signal ACT_W : slbit := '0';
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signal ADDR : slv17 := (others=>'0');
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signal BE : slv4 := (others=>'0');
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signal DI : slv32 := (others=>'0');
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signal DO : slv32 := (others=>'0');
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signal O_MEM_CE_N : slbit := '0';
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signal O_MEM_WE_N : slbit := '0';
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signal O_MEM_OE_N : slbit := '0';
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signal O_MEM_ADDR : slv19 := (others=>'0');
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signal IO_MEM_DATA : slv8 := (others=>'0');
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signal R_MEMON : slbit := '0';
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signal N_CHK_DATA : slbit := '0';
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signal N_REF_DATA : slv32 := (others=>'0');
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signal N_REF_ADDR : slv17 := (others=>'0');
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signal R_CHK_DATA_AL : slbit := '0';
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signal R_REF_DATA_AL : slv32 := (others=>'0');
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signal R_REF_ADDR_AL : slv17 := (others=>'0');
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signal R_CHK_DATA_DL : slbit := '0';
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signal R_REF_DATA_DL : slv32 := (others=>'0');
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signal R_REF_ADDR_DL : slv17 := (others=>'0');
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signal CLK_STOP : slbit := '0';
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signal CLK_CYCLE : integer := 0;
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constant clock_period : Delay_length := 20 ns;
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constant clock_offset : Delay_length := 200 ns;
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constant setup_time : Delay_length := 5 ns;
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constant c2out_time : Delay_length := 10 ns;
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begin
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CLKGEN : simclk
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generic map (
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PERIOD => clock_period,
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OFFSET => clock_offset)
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port map (
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CLK => CLK,
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CLK_STOP => CLK_STOP
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);
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CLKCNT : simclkcnt port map (CLK => CLK, CLK_CYCLE => CLK_CYCLE);
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MEM : entity work.is61wv5128bll
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port map (
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CE_N => O_MEM_CE_N,
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OE_N => O_MEM_OE_N,
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WE_N => O_MEM_WE_N,
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ADDR => O_MEM_ADDR,
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DATA => IO_MEM_DATA
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);
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UUT : c7_sram_memctl
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port map (
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CLK => CLK,
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RESET => RESET,
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REQ => REQ,
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WE => WE,
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BUSY => BUSY,
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ACK_R => ACK_R,
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ACK_W => ACK_W,
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ACT_R => ACT_R,
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ACT_W => ACT_W,
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ADDR => ADDR,
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BE => BE,
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DI => DI,
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DO => DO,
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O_MEM_CE_N => O_MEM_CE_N,
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O_MEM_WE_N => O_MEM_WE_N,
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O_MEM_OE_N => O_MEM_OE_N,
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O_MEM_ADDR => O_MEM_ADDR,
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IO_MEM_DATA => IO_MEM_DATA
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);
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proc_stim: process
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file fstim : text open read_mode is "tb_c7_sram_memctl_stim";
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variable iline : line;
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variable oline : line;
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variable ok : boolean;
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variable dname : string(1 to 6) := (others=>' ');
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variable idelta : integer := 0;
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variable iaddr : slv17 := (others=>'0');
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variable idata : slv32 := (others=>'0');
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variable ibe : slv4 := (others=>'0');
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variable ival : slbit := '0';
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variable nbusy : integer := 0;
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begin
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wait for clock_offset - setup_time;
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file_loop: while not endfile(fstim) loop
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readline (fstim, iline);
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readcomment(iline, ok);
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next file_loop when ok;
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readword(iline, dname, ok);
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if ok then
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case dname is
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when ".memon" => -- .memon
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read_ea(iline, ival);
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R_MEMON <= ival;
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wait for 2*clock_period;
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when ".reset" => -- .reset
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write(oline, string'(".reset"));
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writeline(output, oline);
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RESET <= '1';
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wait for clock_period;
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RESET <= '0';
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wait for 9*clock_period;
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when ".wait " => -- .wait
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read_ea(iline, idelta);
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wait for idelta*clock_period;
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when "read " => -- read
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readgen_ea(iline, iaddr, 16);
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readgen_ea(iline, idata, 16);
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ADDR <= iaddr;
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REQ <= '1';
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WE <= '0';
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writetimestamp(oline, CLK_CYCLE, ": stim read ");
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writegen(oline, iaddr, right, 6, 16);
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write(oline, string'(" "));
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writegen(oline, idata, right, 9, 16);
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wait for clock_period;
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REQ <= '0';
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N_CHK_DATA <= '1', '0' after clock_period;
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N_REF_DATA <= idata;
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N_REF_ADDR <= iaddr;
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nbusy := 0;
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while BUSY = '1' loop
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nbusy := nbusy + 1;
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wait for clock_period;
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end loop;
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write(oline, string'(" nbusy="));
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write(oline, nbusy, right, 2);
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writeline(output, oline);
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when "write " => -- write
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readgen_ea(iline, iaddr, 16);
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read_ea(iline, ibe);
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readgen_ea(iline, idata, 16);
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ADDR <= iaddr;
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BE <= ibe;
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DI <= idata;
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REQ <= '1';
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WE <= '1';
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writetimestamp(oline, CLK_CYCLE, ": stim write");
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writegen(oline, iaddr, right, 6, 16);
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writegen(oline, ibe , right, 5, 2);
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writegen(oline, idata, right, 9, 16);
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wait for clock_period;
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REQ <= '0';
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WE <= '0';
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nbusy := 0;
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while BUSY = '1' loop
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nbusy := nbusy + 1;
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wait for clock_period;
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end loop;
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write(oline, string'(" nbusy="));
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write(oline, nbusy, right, 2);
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writeline(output, oline);
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when others => -- bad directive
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write(oline, string'("?? unknown directive: "));
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write(oline, dname);
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writeline(output, oline);
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report "aborting" severity failure;
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end case;
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else
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report "failed to find command" severity failure;
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end if;
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testempty_ea(iline);
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end loop; -- file fstim
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wait for 10*clock_period;
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writetimestamp(oline, CLK_CYCLE, ": DONE ");
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writeline(output, oline);
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CLK_STOP <= '1';
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wait; -- suspend proc_stim forever
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-- clock is stopped, sim will end
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end process proc_stim;
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proc_moni: process
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variable oline : line;
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begin
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loop
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wait until rising_edge(CLK);
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if ACK_R = '1' then
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writetimestamp(oline, CLK_CYCLE, ": moni ");
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writegen(oline, DO, right, 9, 16);
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if R_CHK_DATA_DL = '1' then
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write(oline, string'(" CHECK"));
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if R_REF_DATA_DL = DO then
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write(oline, string'(" OK"));
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else
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write(oline, string'(" FAIL, exp="));
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writegen(oline, R_REF_DATA_DL, right, 9, 16);
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write(oline, string'(" for a="));
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writegen(oline, R_REF_ADDR_DL, right, 5, 16);
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end if;
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R_CHK_DATA_DL <= '0';
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end if;
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writeline(output, oline);
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end if;
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if R_CHK_DATA_AL = '1' then
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R_CHK_DATA_DL <= R_CHK_DATA_AL;
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R_REF_DATA_DL <= R_REF_DATA_AL;
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R_REF_ADDR_DL <= R_REF_ADDR_AL;
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R_CHK_DATA_AL <= '0';
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end if;
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if N_CHK_DATA = '1' then
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R_CHK_DATA_AL <= N_CHK_DATA;
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R_REF_DATA_AL <= N_REF_DATA;
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R_REF_ADDR_AL <= N_REF_ADDR;
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end if;
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end loop;
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end process proc_moni;
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proc_memon: process
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variable oline : line;
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begin
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loop
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wait until rising_edge(CLK);
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if R_MEMON = '1' then
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writetimestamp(oline, CLK_CYCLE, ": mem ");
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write(oline, string'(" ce="));
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write(oline, not O_MEM_CE_N, right, 2);
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write(oline, string'(" we="));
|
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write(oline, not O_MEM_WE_N, right);
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write(oline, string'(" oe="));
|
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write(oline, not O_MEM_OE_N, right);
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write(oline, string'(" a="));
|
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writegen(oline, O_MEM_ADDR, right, 5, 16);
|
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write(oline, string'(" d="));
|
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writegen(oline, IO_MEM_DATA, right, 8, 16);
|
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writeline(output, oline);
|
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end if;
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||||
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end loop;
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||||
|
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end process proc_memon;
|
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|
||||
|
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end sim;
|
||||
176
rtl/bplib/cmoda7/tb/tb_c7_sram_memctl_stim.dat
Normal file
176
rtl/bplib/cmoda7/tb/tb_c7_sram_memctl_stim.dat
Normal file
@@ -0,0 +1,176 @@
|
||||
# $Id: tb_c7_sram_memctl_stim.dat 912 2017-06-11 18:30:03Z mueller $
|
||||
#
|
||||
.memon 0
|
||||
#
|
||||
C write full word 16 cells
|
||||
#
|
||||
write 00000 1111 30201000
|
||||
write 00001 1111 31211101
|
||||
write 00002 1111 32221202
|
||||
write 00003 1111 33231303
|
||||
write 00004 1111 34241404
|
||||
write 00005 1111 35251505
|
||||
write 00006 1111 36261606
|
||||
write 00007 1111 37271707
|
||||
write 00008 1111 38281808
|
||||
write 00009 1111 39291909
|
||||
write 0000a 1111 3a2a1a0a
|
||||
write 0000b 1111 3b2b1b0b
|
||||
write 0000c 1111 3c2c1c0c
|
||||
write 0000d 1111 3d2d1d0d
|
||||
write 0000e 1111 3e2e1e0e
|
||||
write 0000f 1111 3f2f1f0f
|
||||
#
|
||||
C read 16 cells
|
||||
#
|
||||
read 00000 30201000
|
||||
read 00001 31211101
|
||||
read 00002 32221202
|
||||
read 00003 33231303
|
||||
read 00004 34241404
|
||||
read 00005 35251505
|
||||
read 00006 36261606
|
||||
read 00007 37271707
|
||||
read 00008 38281808
|
||||
read 00009 39291909
|
||||
read 0000a 3a2a1a0a
|
||||
read 0000b 3b2b1b0b
|
||||
read 0000c 3c2c1c0c
|
||||
read 0000d 3d2d1d0d
|
||||
read 0000e 3e2e1e0e
|
||||
read 0000f 3f2f1f0f
|
||||
#
|
||||
C write selected bytes in first 16 cells
|
||||
#
|
||||
write 00000 0000 70605040
|
||||
write 00001 0001 71615141
|
||||
write 00002 0010 72625242
|
||||
write 00003 0011 73635343
|
||||
write 00004 0100 74645444
|
||||
write 00005 0101 75655545
|
||||
write 00006 0110 76665646
|
||||
write 00007 0111 77675747
|
||||
write 00008 1000 78685848
|
||||
write 00009 1001 79695949
|
||||
write 0000a 1010 7a6a5a4a
|
||||
write 0000b 1011 7b6b5b4b
|
||||
write 0000c 1100 7c6c5c4c
|
||||
write 0000d 1101 7d6d5d4d
|
||||
write 0000e 1110 7e6e5e4e
|
||||
write 0000f 1111 7f6f5f4f
|
||||
#
|
||||
C read back
|
||||
#
|
||||
read 00000 30201000
|
||||
read 00001 31211141
|
||||
read 00002 32225202
|
||||
read 00003 33235343
|
||||
read 00004 34641404
|
||||
read 00005 35651545
|
||||
read 00006 36665606
|
||||
read 00007 37675747
|
||||
read 00008 78281808
|
||||
read 00009 79291949
|
||||
read 0000a 7a2a5a0a
|
||||
read 0000b 7b2b5b4b
|
||||
read 0000c 7c6c1c0c
|
||||
read 0000d 7d6d1d4d
|
||||
read 0000e 7e6e5e0e
|
||||
read 0000f 7f6f5f4f
|
||||
#
|
||||
C read and write with waits
|
||||
#
|
||||
.wait 3
|
||||
write 00010 1111 30201000
|
||||
.wait 2
|
||||
write 00011 1111 31211101
|
||||
.wait 1
|
||||
write 00012 1111 32221202
|
||||
write 00013 1111 33231303
|
||||
#
|
||||
.wait 3
|
||||
read 00010 30201000
|
||||
.wait 2
|
||||
read 00011 31211101
|
||||
.wait 1
|
||||
read 0000e 7e6e5e0e
|
||||
read 0000f 7f6f5f4f
|
||||
#
|
||||
C read and write mixed, with waits
|
||||
#
|
||||
.wait 2
|
||||
write 00014 1111 34241404
|
||||
.wait 2
|
||||
read 00012 32221202
|
||||
.wait 2
|
||||
write 00015 1111 35251505
|
||||
.wait 2
|
||||
read 00013 33231303
|
||||
#
|
||||
.wait 1
|
||||
write 00016 1111 36261606
|
||||
.wait 1
|
||||
read 00014 34241404
|
||||
.wait 1
|
||||
write 00017 1111 37271707
|
||||
.wait 1
|
||||
read 00015 35251505
|
||||
#
|
||||
write 00018 1111 38281808
|
||||
read 00016 36261606
|
||||
write 00019 1111 39291909
|
||||
read 00017 37271707
|
||||
#
|
||||
.wait 2
|
||||
write 0001a 1111 3a2a1a0a
|
||||
write 0001b 1111 3b2b1b0b
|
||||
.wait 2
|
||||
read 00018 38281808
|
||||
read 00019 39291909
|
||||
.wait 2
|
||||
write 0001c 1111 3c2c1c0c
|
||||
write 0001d 1111 3d2d1d0d
|
||||
.wait 2
|
||||
read 0001a 3a2a1a0a
|
||||
read 0001b 3b2b1b0b
|
||||
#
|
||||
.wait 1
|
||||
write 0001e 1111 3e2e1e0e
|
||||
write 0001f 1111 3f2f1f0f
|
||||
.wait 1
|
||||
read 0001c 3c2c1c0c
|
||||
read 0001d 3d2d1d0d
|
||||
.wait 1
|
||||
write 00014 0100 74645444
|
||||
write 00015 0101 75655545
|
||||
.wait 1
|
||||
read 0001e 3e2e1e0e
|
||||
read 0001f 3f2f1f0f
|
||||
#
|
||||
write 00016 0110 76665646
|
||||
write 00017 0111 77675747
|
||||
read 00010 30201000
|
||||
read 00011 31211101
|
||||
write 00018 1000 78685848
|
||||
write 00019 1001 79695949
|
||||
read 00012 32221202
|
||||
read 00013 33231303
|
||||
#
|
||||
write 0001a 1010 7a6a5a4a
|
||||
write 0001b 1011 7b6b5b4b
|
||||
write 0001c 1100 7c6c5c4c
|
||||
read 00014 34641404
|
||||
read 00015 35651545
|
||||
read 00016 36665606
|
||||
write 0001d 1101 7d6d5d4d
|
||||
write 0001e 1110 7e6e5e4e
|
||||
write 0001f 1111 7f6f5f4f
|
||||
read 00017 37675747
|
||||
read 00018 78281808
|
||||
read 00019 79291949
|
||||
read 0001a 7a2a5a0a
|
||||
read 0001b 7b2b5b4b
|
||||
read 0001c 7c6c1c0c
|
||||
read 0001d 7d6d1d4d
|
||||
read 0001e 7e6e5e0e
|
||||
read 0001f 7f6f5f4f
|
||||
Reference in New Issue
Block a user