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6
README.md
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@@ -18,8 +18,8 @@ For more information look into:
- [change log](doc/CHANGELOG.md)
and [installation notes](doc/INSTALL.md)
- guides to build bit files and test benches
with [Xilinx Vivado](doc/README_buildsystem_Vivado.md.html)
and [Xilinx ISE](doc/README_buildsystem_ISE.md.html)
with [Xilinx Vivado](doc/README_buildsystem_Vivado.md)
and [Xilinx ISE](doc/README_buildsystem_ISE.md)
- guides to [run test benches](doc/w11a_tb_guide.md)
and to [boot operating systems](doc/w11a_os_guide.md)
- known issues [general](doc/README_known_issues.md)
@@ -51,7 +51,7 @@ all files contain the disclaimer:
This program is free software; you may redistribute and/or modify
it under the terms of the GNU General Public License version 3.
See Licence.txt in distribition directory for further details.
See License.txt in distribition directory for further details.
The full text of the GPL license is in this directory as
[License.txt](License.txt).

30
doc/CHANGELOG-w11a_V0.50-w11a_V0.60.md
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@@ -39,7 +39,7 @@
<!-- --------------------------------------------------------------------- -->
---
## 2014-06-06: w11a_V0.60 - svn rev 25(oc) 559+(wfjm) <a name="w11a_V0.60"></a>
## <a id="w11a_V0.60">2014-06-06: w11a_V0.60 - svn rev 25(oc) 559+(wfjm)</a>
### Summary
- many documentation updates; no functional changes
@@ -61,7 +61,7 @@
<!-- --------------------------------------------------------------------- -->
---
## 2014-05-29: w11a_V0.581 - svn rev 22(oc) 556(wfjm) <a name="w11a_V0.581"></a>
## <a id="w11a_V0.581">2014-05-29: w11a_V0.581 - svn rev 22(oc) 556(wfjm)</a>
### Summary
- new reference system
@@ -117,7 +117,7 @@
<!-- --------------------------------------------------------------------- -->
---
## 2013-05-12: w11a_V0.58 - svn rev 21(oc) 518+(wfjm) <a name="w11a_V0.58"></a>
## <a id="w11a_V0.58">2013-05-12: w11a_V0.58 - svn rev 21(oc) 518+(wfjm)</a>
### Summary
- C++ and Tcl based backend server now fully functional, supports with
@@ -155,7 +155,7 @@
<!-- --------------------------------------------------------------------- -->
---
## 2013-04-27: w11a_V0.57 - svn rev 20(oc) 511(wfjm) <a name="w11a_V0.57"></a>
## <a id="w11a_V0.57">2013-04-27: w11a_V0.57 - svn rev 20(oc) 511(wfjm)</a>
### Summary
- new C++ and Tcl based backend server supports now RK11 handling
@@ -188,7 +188,7 @@
<!-- --------------------------------------------------------------------- -->
---
## 2013-04-13: w11a_V0.562 - svn rev 19(oc) 505(wfjm) <a name="w11a_V0.562"></a>
## <a id="w11a_V0.562">2013-04-13: w11a_V0.562 - svn rev 19(oc) 505(wfjm)</a>
### Summary
- V0.53 introduced a new C++ and Tcl based backend server, but only the
@@ -230,7 +230,7 @@
<!-- --------------------------------------------------------------------- -->
---
## 2013-01-06: w11a_V0.561 - svn rev 18(oc) 472(wfjm) <a name="w11a_V0.561"></a>
## <a id="w11a_V0.561">2013-01-06: w11a_V0.561 - svn rev 18(oc) 472(wfjm)</a>
### Summary
- Added simple simulation model of Cypress FX2 and test benches for
@@ -254,7 +254,7 @@
<!-- --------------------------------------------------------------------- -->
---
## 2013-01-02: w11a_V0.56 - svn rev 17(oc) 467(wfjm) <a name="w11a_V0.56"></a>
## <a id="w11a_V0.56">2013-01-02: w11a_V0.56 - svn rev 17(oc) 467(wfjm)</a>
### Summary
- re-organized handling of board and derived clocks in test benches
@@ -316,7 +316,7 @@ The version of several key tools and libraries changed:
<!-- --------------------------------------------------------------------- -->
---
## 2011-12-23: w11a_V0.55 - svn rev 16(oc) 442(wfjm) <a name="w11a_V0.55"></a>
## <a id="w11a_V0.55">2011-12-23: w11a_V0.55 - svn rev 16(oc) 442(wfjm)</a>
### Summary
- added xon/xoff (software flow control) support to serport library
@@ -352,7 +352,7 @@ The version of several key tools and libraries changed:
<!-- --------------------------------------------------------------------- -->
---
## 2011-12-04: w11a_V0.54 - svn rev 15(oc) 436(wfjm) <a name="w11a_V0.54"></a>
## <a id="w11a_V0.54">2011-12-04: w11a_V0.54 - svn rev 15(oc) 436(wfjm)</a>
### Summary
- added support for nexys3 board for w11a
@@ -374,7 +374,7 @@ The version of several key tools and libraries changed:
<!-- --------------------------------------------------------------------- -->
---
## 2011-11-20: w11a_V0.532 - svn rev 14(oc) 428(wfjm) <a name="w11a_V0.532"></a>
## <a id="w11a_V0.532">2011-11-20: w11a_V0.532 - svn rev 14(oc) 428(wfjm)</a>
### Summary
- generalized the 'human I/O' interface for s3board,nexys2/3 and atlys
@@ -401,7 +401,7 @@ The version of several key tools and libraries changed:
<!-- --------------------------------------------------------------------- -->
---
## 2011-09-11: w11a_V0.531 - svn rev 12(oc) 409(wfjm) <a name="w11a_V0.531"></a>
## <a id="w11a_V0.531">2011-09-11: w11a_V0.531 - svn rev 12(oc) 409(wfjm)</a>
### Summary
- Many small changes to prepare upcoming support for
@@ -432,7 +432,7 @@ The version of several key tools and libraries changed:
<!-- --------------------------------------------------------------------- -->
---
## 2011-04-17: w11a_V0.53 - svn rev 11(oc) 376(wfjm) <a name="w11a_V0.53"></a>
## <a id="w11a_V0.53">2011-04-17: w11a_V0.53 - svn rev 11(oc) 376(wfjm)</a>
### Summary
- Introduce C++ and Tcl based backend server. A set of C++ classes provide
@@ -482,7 +482,7 @@ The version of several key tools and libraries changed:
<!-- --------------------------------------------------------------------- -->
---
## 2011-01-02: w11a_V0.52 - svn rev 9(oc) 352(wfjm) <a name="w11a_V0.52"></a>
## <a id="w11a_V0.52">2011-01-02: w11a_V0.52 - svn rev 9(oc) 352(wfjm)</a>
### Summary
- Introduce rbus protocol V3
@@ -558,7 +558,7 @@ The version of several key tools and libraries changed:
<!-- --------------------------------------------------------------------- -->
---
## 2010-11-28: w11a_V0.51 - svn rev 8(oc) 341(wfjm) <a name="w11a_V0.51"></a>
## <a id="w11a_V0.51">2010-11-28: w11a_V0.51 - svn rev 8(oc) 341(wfjm)</a>
### Summary
- Introduce ibus protocol V2
@@ -599,7 +599,7 @@ The version of several key tools and libraries changed:
<!-- --------------------------------------------------------------------- -->
---
## 2010-07-23: w11a_V0.5 <a name="w11a_V0.5"></a>
## <a id="w11a_V0.5">2010-07-23: w11a_V0.5</a>
### Initial release with
- w11a CPU core

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doc/CHANGELOG-w11a_V0.60-w11a_V0.70.md
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@@ -31,7 +31,7 @@
<!-- --------------------------------------------------------------------- -->
---
## 2015-06-21: w11a_V0.70 - svn rev 33(oc) 693(wfjm) <a name="w11a_V0.70"></a>
## <a id="w11a_V0.70">2015-06-21: w11a_V0.70 - svn rev 33(oc) 693(wfjm)</a>
### Preface
- resolved known issue V0.66-2: operation with multiple RP or RM disks
@@ -86,7 +86,7 @@
<!-- --------------------------------------------------------------------- -->
---
## 2015-06-05: w11a_V0.66 - svn rev 31(oc) 687(wfjm) <a name="w11a_V0.66"></a>
## <a id="w11a_V0.66">2015-06-05: w11a_V0.66 - svn rev 31(oc) 687(wfjm)</a>
### Preface
- Since the previous release a full set of small, medium and large sized
@@ -161,7 +161,7 @@
<!-- --------------------------------------------------------------------- -->
---
## 2015-05-14: w11a_V0.65 - svn rev 30(oc) 681(wfjm) <a name="w11a_V0.65"></a>
## <a id="w11a_V0.65">2015-05-14: w11a_V0.65 - svn rev 30(oc) 681(wfjm)</a>
### Preface
- With small RK05 or RL02 sized disks only quite reduced OS setups could
@@ -290,7 +290,7 @@
<!-- --------------------------------------------------------------------- -->
---
## 2015-03-01: w11a_V0.64 - svn rev 29(oc) 655(wfjm) <a name="w11a_V0.64"></a>
## <a id="w11a_V0.64">2015-03-01: w11a_V0.64 - svn rev 29(oc) 655(wfjm)</a>
### Preface
- The w11 project started on a Spartan-3 based Digilent S3board, and soon
@@ -439,7 +439,7 @@
<!-- --------------------------------------------------------------------- -->
---
## 2015-01-04: w11a_V0.63 - svn rev 28(oc) 629(wfjm) <a name="w11a_V0.63"></a>
## <a id="w11a_V0.63">2015-01-04: w11a_V0.63 - svn rev 28(oc) 629(wfjm)</a>
### Summary
- the w11a rbus interface used so far a narrow dynamically adjusted
@@ -495,7 +495,7 @@
<!-- --------------------------------------------------------------------- -->
---
## 2014-12-20: w11a_V0.62 - svn rev 27(oc) 614(wfjm) <a name="w11a_V0.62"></a>
## <a id="w11a_V0.62">2014-12-20: w11a_V0.62 - svn rev 27(oc) 614(wfjm)</a>
### Summary
- migrate to rlink protocol version 4
@@ -581,7 +581,7 @@ Notes:
<!-- --------------------------------------------------------------------- -->
---
## 2014-08-08: w11a_V0.61 - svn rev 25(oc) 579(wfjm) <a name="w11a_V0.61"></a>
## <a id="w11a_V0.61">2014-08-08: w11a_V0.61 - svn rev 25(oc) 579(wfjm)</a>
### Summary
- The `div` instruction gave wrong results in some corner cases when either
divisor or quotient were the largest negative integer (100000 or -32768).

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@@ -28,7 +28,7 @@
<!-- --------------------------------------------------------------------- -->
---
## 2016-10-02: w11a_V0.74 - svn rev 37(oc) 811(wfjm) <a name="w11a_V0.74"></a>
## <a id="w11a_V0.74">2016-10-02: w11a_V0.74 - svn rev 37(oc) 811(wfjm)</a>
### Preface
- the current version of the memory controller for the micron `mt45w8mw16b`
'cellular ram' used on nexys2, nexys3, and nexys4 uses the asynchronous
@@ -183,7 +183,7 @@
<!-- --------------------------------------------------------------------- -->
---
## 2016-06-26: w11a_V0.73 - svn rev 36(oc) 779(wfjm) <a name="w11a_V0.73"></a>
## <a id="w11a_V0.73">2016-06-26: w11a_V0.73 - svn rev 36(oc) 779(wfjm)</a>
### Preface
- the 'basic vivado support' added with V0.64 was a minimal effort port of
the code base used under ISE, leading to sub-optimal results under vivado.
@@ -390,7 +390,7 @@
<!-- --------------------------------------------------------------------- -->
---
## 2016-03-19: w11a_V0.72 - svn rev 35(oc) 746(wfjm) <a name="w11a_V0.72"></a>
## <a id="w11a_V0.72">2016-03-19: w11a_V0.72 - svn rev 35(oc) 746(wfjm)</a>
### Preface
- The new low-cost Digilent Arty board is a very attractive platform.
The DDR3 memory will take some time to integrate, in this release thus
@@ -498,7 +498,7 @@
<!-- --------------------------------------------------------------------- -->
---
## 2015-12-30: w11a_V0.71 - svn rev 34(oc) 722(wfjm) <a name="w11a_V0.71"></a>
## <a id="w11a_V0.71">2015-12-30: w11a_V0.71 - svn rev 34(oc) 722(wfjm)</a>
### Preface
- the w11a so far lacked any 'hardware debugger' support, which made the
debugging of CPU core issues a bit tedious. This release added a first

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doc/CHANGELOG.md
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@@ -10,7 +10,7 @@
<!-- --------------------------------------------------------------------- -->
---
## HEAD <a name="head"></a>
## <a id="head">HEAD</a>
### General Proviso
The HEAD version shows the current development. No guarantees that
software or firmware builds or that the documentation is consistent.
@@ -22,7 +22,7 @@ The full set of tests is only run for tagged releases.
They are now consistent with the License.txt file, which refers to GPL V3.
- Added Unix 7th Edition oskit; rename 5th Edition kit
- u5ed_rk: renamed from unix-v5_rk
- u7ed_rp: added, very preliminary, boots on CmodA7, further testing be be done
- u7ed_rp: added, very preliminary, boots on CmodA7, further testing needed
- Add Digilent Cmod A7 (35 die size) support
- general board support
- c7_sram_memctl: SRAM memory controller (incl tb)
@@ -55,7 +55,7 @@ The full set of tests is only run for tagged releases.
<!-- --------------------------------------------------------------------- -->
---
## 2017-06-04: [w11a_V0.75](https://github.com/wfjm/w11/releases/tag/w11a_V0.75) - rev 904(wfjm) <a name="w11a_V0.75"></a>
## <a id="w11a_V0.75">2017-06-04: [w11a_V0.75](https://github.com/wfjm/w11/releases/tag/w11a_V0.75) - rev 904(wfjm)</a>
### Summary
- the only device class missing so far for the w11 was *network interfaces*.
@@ -237,7 +237,7 @@ The full set of tests is only run for tagged releases.
<!-- --------------------------------------------------------------------- -->
---
## 2017-01-07: [w11a_V0.742](https://github.com/wfjm/w11/releases/tag/w11a_V0.742) - rev 841(wfjm) <a name="w11a_V0.742"></a>
## <a id="w11a_V0.742">2017-01-07: [w11a_V0.742](https://github.com/wfjm/w11/releases/tag/w11a_V0.742) - rev 841(wfjm)</a>
### Summary
- fixes for Vivado 2016.4; all designs build under vivado 2016.4
@@ -249,7 +249,7 @@ The full set of tests is only run for tagged releases.
<!-- --------------------------------------------------------------------- -->
---
## 2016-12-23: [w11a_V0.741](https://github.com/wfjm/w11/releases/tag/w11a_V0.741) - rev 826(wfjm) <a name="w11a_V0.741"></a>
## <a id="w11a_V0.741">2016-12-23: [w11a_V0.741](https://github.com/wfjm/w11/releases/tag/w11a_V0.741) - rev 826(wfjm)</a>
### Summary
- moved w11 repository from OpenCores to GitHub
[wfjm/w11](https://github.com/wfjm/w11/)

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doc/INSTALL.md
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@@ -14,7 +14,7 @@
- [Available bitkits with bit and log files](#user-content-bitkits)
- [Generate Doxygen based source code view](#user-content-build-doxy)
### Download <a name="download"></a>
### <a id="download">Download</a>
All instructions below assume that the project files reside in a
working directory with the name represented as `<install-dir>`
@@ -43,7 +43,7 @@ Prior to October 2016 the project was maintained on OpenCores, access
to the legacy svn repository is described in
[INSTALL_from_opencores.md](INSTALL_from_opencores.md).
### System requirements <a name="sysreq"></a>
### <a id="sysreq">System requirements</a>
This project contains not only VHDL code but also support software. Therefore
quite a few software packages are expected to be installed. The following
@@ -78,7 +78,7 @@ distributions should be straight forward.
required, version 1.8.3.1 or later
### Setup environment variables <a name="envvar"></a>
### <a id="envvar">Setup environment variables</a>
The make flows for building test benches (ghdl, Vivado xsim or ISE ISim based)
and FPGA bit files (with Vivado or ISE) as well as the support software
@@ -121,7 +121,7 @@ read next section.
For Cypress FX2 (on Nexys2/3) related setup see
[INSTALL_fx2_support.md](INSTALL_fx2_support.md).
### Compile UNISIM/UNIMACRO/SIMPRIM libraries for ghdl <a name="ghdl-lib"></a>
### <a id="ghdl-lib">Compile UNISIM/UNIMACRO/SIMPRIM libraries for ghdl</a>
The build system for test benches also supports test benches run against the
gate level models derived after synthesis or place&route. In this case ghdl
@@ -130,9 +130,9 @@ The details are described in
- [README_buildsystem_Vivado.md](README_buildsystem_Vivado.md#user-content-ghdllibs)
- [README_buildsystem_ISE.md](README_buildsystem_ISE.md#user-content-ghdllibs)
### Compile and install the support software <a name="build-tools"></a>
### <a id="build-tools">Compile and install the support software</a>
#### Compile sharable libraries <a name="build-cpp"></a>
#### <a id="build-cpp">Compile sharable libraries</a>
Note: some `c++11` features are used in the code
@@ -175,7 +175,7 @@ To cleanup, e.g. before a re-build
rm_dep
make realclean
#### Setup Tcl environment <a name="build-tcl"></a>
#### <a id="build-tcl">Setup Tcl environment</a>
The Tcl files are organized in several packages. To create the Tcl
package files (`pkgIndex.tcl`)
@@ -200,7 +200,7 @@ To use them simply copy them into your home directory (or soft link them)
ln -s $RETROBASE/tools/tcl/.tclshrc .
ln -s $RETROBASE/tools/tcl/.wishrc .
### The build system <a name="build-system"></a>
### <a id="build-system">The build system</a>
The generation of FPGA firmware and test benches is based on make flows.
@@ -215,7 +215,7 @@ can be found under
- [README_buildsystem_ISE.md](README_buildsystem_ISE.md)
for Spartan-3 and Spartan-6 based designs
### Available designs <a name="build-fpga"></a>
### <a id="build-fpga">Available designs</a>
Ready to build designs are organized in the directories
@@ -242,7 +242,7 @@ with in most cases
- `<dtype>` = `<design>`
- `<code>` = 2 letter abbreviation for the board, e.g. n4 for nexys4.
### Available bitkits with bit and log files <a name="bitkits"></a>
### <a id="bitkits">Available bitkits with bit and log files</a>
Tarballs with ready to use bit files and all logfiles from the tool
chain can be downloaded from
@@ -281,7 +281,7 @@ file names contain information about release, Xlinix tool, and design:
xtwi config_wrapper --board=s3board iconfig <design>.bit
### Generate Doxygen based source code view <a name="build-doxy"></a>
### <a id="build-doxy">Generate Doxygen based source code view</a>
Currently there is not much real documentation included in the source
files. The doxygen generated html output is nevertheless very useful

8
doc/INSTALL_fx2_support.md
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@@ -12,7 +12,7 @@ installation of tools, environment setup and generation of the FX2 firmware.
- [Setup USB access](#user-content-usb-access)
- [Rebuild Cypress FX2 firmware](#user-content-fx2-firmware)
### System requirements <a name="sysreq"></a>
### <a id="sysreq">System requirements</a>
the download contains pre-build firmware images for the Cypress FX2
USB Interface. Re-building them requires
@@ -23,7 +23,7 @@ USB Interface. Re-building them requires
is **broken in Ubuntu 16.04**.
See [INSTALL_urjtag.md](INSTALL_urjtag.md) for installation from sources !!
### Setup environment variables <a name="envvar"></a>
### <a id="envvar">Setup environment variables</a>
The default USB VID and PID is defined by two environment variables.
For internal lab use one can use
@@ -36,7 +36,7 @@ For internal lab use one can use
> misuse of the defaults provided with the project sources.
> Usage of this VID/PID in any commercial product is forbidden.**
### Setup USB access <a name="usb-access"></a>
### <a id="usb-access">Setup USB access</a>
For using the Cypress FX2 USB interface on Digilent Nexys2, Nexys3 and
Atlys boards `udev` rules must be setup to allow user level access to
@@ -51,7 +51,7 @@ Notes:
described above. If a different VID/PID is used the file must be modified.
- your user account must be in group `plugdev` (should be the default).
### Rebuild Cypress FX2 firmware <a name="fx2-firmware"></a>
### <a id="fx2-firmware">Rebuild Cypress FX2 firmware</a>
The download includes pre-build firmware images for the Cypress FX2
USB interface used on the Digilent Nexys2, Nexys3 and Atlys Boards.

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@@ -14,7 +14,7 @@
- [Configuring FPGAs (directly via config_wrapper)](#user-content-config-wrap)
- [Note on Artix-7 based designs](#user-content-artix)
### Concept <a name="concept"></a>
### <a id="concept">Concept</a>
This projects uses GNU make to
- generate bit files (synthesis with xst and place&route with par)
@@ -58,9 +58,9 @@ maintained.
For more details on vbomconv consult the man page.
### Setup system environment <a name="sysenv"></a>
### <a id="sysenv">Setup system environment</a>
#### Setup environment variables <a name="envvar"></a>
#### <a id="envvar">Setup environment variables</a>
The build flows require the environment variables:
- `RETROBASE`: must refer to the installation root directory
@@ -78,7 +78,7 @@ Notes:
- don't run the ISE setup scripts ..../settings(32|64).sh in your working
shell. Setup only `XTWI_PATH` !
#### Compile UNISIM/UNIMACRO/SIMPRIM libraries for ghdl <a name="ghdllibs"></a>
#### <a id="ghdllibs">Compile UNISIM/UNIMACRO/SIMPRIM libraries for ghdl</a>
A few entities use `UNISIM` or `UNIMACRO` primitives, and models derived after
the par step require also `SIMPRIM` primitives. In these cases ghdl has to
@@ -99,13 +99,13 @@ Two helper scripts will create these libraries:
Run these scripts for each ISE version which is installed.
### Building test benches <a name="buildtb"></a>
### <a id="buildtb">Building test benches</a>
The build flows support two simulators
- ghdl -> open source, with VHPI support, doesn't accept sdf files
- ISE ISim -> limited to 50k lines in WebPack, no VHPI support
#### With ghdl <a name="buildtb-ghdl"></a>
#### <a id="buildtb-ghdl">With ghdl</a>
To compile a ghdl based test bench named `<tbench>` all is needed is
@@ -138,7 +138,7 @@ Notes:
- post-par simulations without timing annotation often fail, most likely
due to clocking and delta cycle issues due to inserted clock buffers.
#### With ISE ISim <a name="buildtb-isim"></a>
#### <a id="buildtb-isim">With ISE ISim</a>
To compile a ISE ISim based test bench named `<tbench>` all is needed is
@@ -165,7 +165,7 @@ Notes:
Since VHPI is used in the rlink simulation all system test benches with
an rlink interface, thus most, will only run with ghdl and not with ISim.
### Building FPGA bit files <a name="buildfpga"></a>
### <a id="buildfpga">Building FPGA bit files</a>
To generate a bit file for a system named `<sys>` all is needed is
@@ -203,7 +203,7 @@ use the make target
after a re-build.
### Configuring FPGAs (via make flow) <a name="config-make"></a>
### <a id="config-make">Configuring FPGAs (via make flow)</a>
The make flow supports also loading the bitstream into FPGAs, either
via Xilinx Impact, or via the Cypress FX2 USB controller is available.
@@ -223,7 +223,7 @@ to a version matching the FPGA design, generate a .svf file from the
.bit file, and configure the FPGA. In case the bit file is out-of-date
the whole design will be re-implemented before.
### Configuring FPGAs (directly via `config_wrapper`) <a name="config-wrap"></a>
### <a id="config-wrap">Configuring FPGAs (directly via `config_wrapper`)</a>
The make flow described above uses two scripts
@@ -233,7 +233,7 @@ The make flow described above uses two scripts
which can be used directly for loading available bit or svf files into
the FPGA. For detailed documentation see the respective man pages.
### Note on Artix-7 based designs <a name="artix"></a>
### <a id="artix">Note on Artix-7 based designs</a>
The development for Nexys4 started with ISE, but has now fully moved to
Vivado. The make files for the ISE build flows have been kept for comparison

22
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@@ -14,7 +14,7 @@
- [Configuring FPGAs (via make flow)](#user-content-config-fpga)
- [Note on ISE](#user-content-ise)
### Concept <a name="concept"></a>
### <a id="concept">Concept</a>
This projects uses GNU `make` to
- generate bit files (with Vivado synthesis)
@@ -60,9 +60,9 @@ maintained.
For more details on `vbomconv` consult the man page.
### Setup system environment <a name="sysenv"></a>
### <a id="sysenv">Setup system environment</a>
#### Setup environment variables <a name="envvar"></a>
#### <a id="envvar">Setup environment variables</a>
The build flows require the environment variables:
- `RETROBASE`: must refer to the installation root directory
@@ -77,7 +77,7 @@ Notes:
- don't run the Vivado setup scripts ..../settings(32|64).sh in your working
shell. Setup only XTWV_PATH !
#### Compile UNISIM/UNIMACRO libraries for ghdl <a name="ghdllibs"></a>
#### <a id="ghdllibs">Compile UNISIM/UNIMACRO libraries for ghdl</a>
A few entities use `UNISIM` or `UNIMACRO` primitives, and post synthesis models
require also `UNISIM` primitives. In these cases ghdl has to link against a
@@ -103,11 +103,11 @@ Notes:
However: under ISE `SIMPRIM` was available in vhdl, but ghdl did never
accept the sdf files, making ghdl timing simulations impossible under ISE too.
### Building test benches <a name="buildtb"></a>
### <a id="buildtb">Building test benches</a>
The build flows currently supports ghdl and the vivado simulator xsim.
#### With ghdl <a name="buildtb-ghdl"></a>
#### <a id="buildtb-ghdl">With ghdl</a>
To compile a ghdl based test bench named `<tbench>` all is needed is
@@ -143,7 +143,7 @@ Notes:
- Many post-synthesis functional currently fail due to startup and
initialization problems (see issue V0.73-2).
#### With Vivado xsim <a name="buildtb-xsim"></a>
#### <a id="buildtb-xsim">With Vivado xsim</a>
To compile a Vivado xsim based test bench named <tbench> all is needed is
@@ -174,7 +174,7 @@ Notes:
simulations currently fail due to startup and initialization problems
(see issue V0.73-2).
### Building FPGA bit files <a name="buildfpga"></a>
### <a id="buildfpga">Building FPGA bit files</a>
To generate a bit file for a system named `<sys>` all is needed is
@@ -215,7 +215,7 @@ If only the post synthesis, optimize or route design checkpoints are wanted
make <sys>_opt.dcp
make <sys>_rou.dcp
### Building vivado projects, creating gate level models <a name="buildviv"></a>
### <a id="buildviv">Building vivado projects, creating gate level models</a>
Vivado is used in 'project mode', whenever one of the targets mentioned
above is build a vivado project is freshly created in the directory
@@ -250,7 +250,7 @@ Specifically
For timing model verilog file an associated sdf file is also generated.
### Configuring FPGAs <a name="config-fpga"></a>
### <a id="config-fpga">Configuring FPGAs</a>
The make flow supports also loading the bitstream into FPGAs via the
Vivado hardware server. Simply use
@@ -259,7 +259,7 @@ Vivado hardware server. Simply use
Note: works with Arty, Basys3, and Nexys4, only one board must connected.
### Note on ISE <a name="ise"></a>
### <a id="ise">Note on ISE</a>
The development for Nexys4 started with ISE, but has now fully moved to
Vivado. The make files for the ISE build flows have been kept for comparison

6
doc/w11a_known_issues.md
View File

@@ -11,7 +11,7 @@ This file descibes issues of the w11 CPU.
- [Known limitations](#user-content-lim)
- [Known bugs](#user-content-bug)
### Known differences between w11a and KB11-C (11/70) <a name="diff"></a>
### <a id="diff">Known differences between w11a and KB11-C (11/70)</a>
- the `SPL` instruction in the 11/70 always fetched the next instruction
regardless of pending device or even console interrupts. This is known
@@ -43,7 +43,7 @@ All four points relate to very 11/70 specific behaviour, no operating system
depends on them, therefore they are considered acceptable implementation
differences.
### Known limitations <a name="lim"></a>
### <a id="lim">Known limitations</a>
- some programs use timing loops based on the execution speed of the
original processors. This can lead to spurious timeouts, especially
@@ -56,7 +56,7 @@ differences.
**--> a 'watch dog' mechanism will be added in a future version which
suspends the CPU when the server doesn't respond fast enough.**
### Known bugs <a name="bug"></a>
### <a id="bug">Known bugs</a>
- **TCK-038 pri=H: DL11: output chars lost**
Part of the output can be lost when `xxdp` test `eqkce1` is run on FPGA, also

14
doc/w11a_os_guide.md
View File

@@ -10,7 +10,7 @@
- [Unix systems](#user-content-oskits-unix)
- [DEC operating systems](#user-content-oskits-dec)
### I/O emulation setup <a name="io-emu"></a>
### <a id="io-emu">I/O emulation setup</a>
All UNIBUS peripherals which exchange data (currently DL11, LP11, PC11, RK11,
RL11, RPRH, TM11, and DENUA ) are currently emulated via a backend process. The
@@ -61,7 +61,7 @@ Recommended setup for best performance (boards ordered by vintage):
| Nexys2 | Cypress FX2 USB | USB2.0 speed | 30000 kB/sec |
| S3board | RS232+USB-RS232 cable | 460k Baud | 41 kB/sec |
### FPGA Board setup <a name="fpga-setup"></a>
### <a id="fpga-setup">FPGA Board setup</a>
Recommended setups
@@ -95,7 +95,7 @@ Recommended setups
- connect a JTAG programmer (e.g. Xilinx USB Cable II) to JTAG pins
- to configure via ISE Impact `make <sys>.iconfig`
### Rlink and Backend Server setup <a name="rlink"></a>
### <a id="rlink">Rlink and Backend Server setup</a>
All examples below use the same basic setup
@@ -190,7 +190,7 @@ All examples below use the same basic setup
0 -> DISPREG
1 -> DR emulation
### simh simulator setup <a name="simh"></a>
### <a id="simh">simh simulator setup</a>
Sometimes it is good to compare the w11a behavior with the PDP-11 software
emulator from the simh project (see http://simh.trailing-edge.com/).
@@ -222,7 +222,7 @@ All examples below use the same basic setup
pdp11 <oskit-name>_boot.scmd
### oskits <a name="oskits"></a>
### <a id="oskits">oskits</a>
Ready to be used 'oskits' are provided under
@@ -231,7 +231,7 @@ Ready to be used 'oskits' are provided under
The tarballs with the disk images are provided from a web server
and have to be installed separately.
### Unix systems <a name="oskits-unix"></a>
### <a id="oskits-unix">Unix systems</a>
#### Legal and license issues
@@ -258,7 +258,7 @@ Several oskits are provided:
For further details consult the `README.md` file in the oskit directory.
### DEC operating systems <a name="oskits-dec"></a>
### <a id="oskits-dec">DEC operating systems</a>
#### Legal and license issues

14
doc/w11a_tb_guide.md
View File

@@ -18,7 +18,7 @@
- For timing simulations only Vivado xsim can be used.
- ISE isim is also available, but considered legacy support
### Tests bench environment <a name="env"></a>
### <a id="env">Tests bench environment</a>
All test benches have the same simple structure:
@@ -53,7 +53,7 @@ All test benches have the same simple structure:
of the vivado flow and
[README_buildsystem_ISE.md](README_buildsystem_ISE.md) for the ISE flow.
### Unit test benches <a name="tb-unit"></a>
### <a id="tb-unit">Unit test benches</a>
All unit test are executed via `tbw` (test bench warpper) script.
@@ -73,7 +73,7 @@ All unit test are executed via `tbw` (test bench warpper) script.
tbw|tbfilt pipe. This script also checks with `make` whether the
test bench is up-to-date or must be (re)-compiled.
### System test benches <a name="tb-sys"></a>
### <a id="tb-sys">System test benches</a>
The system tests allow to verify to verify a full system design.
In this case vhdl test bench code contains
@@ -93,7 +93,7 @@ In general the script `tbrun_tbwrri` is used to generate the quite lengthy
command to properly setup the tbw|tbfilt pipe. This script also checks
with `make` whether the test bench is up-to-date or must be (re)-compiled.
### Test bench driver <a name="tb-driver"></a>
### <a id="tb-driver">Test bench driver</a>
All available tests (unit and system test benches) are described in a
set of descriptor files, usually called `tbrun.yml`. The top level file
@@ -123,7 +123,7 @@ selection via `--tag`. Very helpful is
which gives a listing of all available test. The tag list as well as
the shell commands to execute the test are shown.
### Execute all available tests <a name="tb-exec"></a>
### <a id="tb-exec">Execute all available tests</a>
As stated above it is in general better to to separate the model building
(make phase) made model execution (run phase). The currently recommended
@@ -162,7 +162,7 @@ It should look like
76m 0m00.083s c 1121 0 PASS tb_pdp11core_bsim_ubmap.log
76m 0m00.068s c 1031 0 PASS tb_rlink_tba_pdp11core_bsim_ibdr.log
### Available unit test benches <a name="list-tb-unit"></a>
### <a id="list-tb-unit">Available unit test benches</a>
tbrun --tag=comlib # comlib unit tests
tbrun --tag=serport # serport unit tests
@@ -173,7 +173,7 @@ It should look like
tbrun --tag=cram_memctl # CRAM controller unit tests
tbrun --tag=w11a # w11a unit tests
### Available system test benches <a name="list-tb-sys"></a>
### <a id="list-tb-sys">Available system test benches</a>
tbrun --tag=sys_tst_serloop.* # all sys_tst_serloop designs
tbrun --tag=sys_tst_rlink # all sys_tst_rlink designs