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finalize IDEC and PERFEXT wiring

Browse Source 
- ibdr_maxisys: add IDEC port, connect to EXTEVT of KW11P
- sys_w11a_*.vhd: use DM_STAT_EXP; IDEC to maxisys; setup PERFEXT
- kw11p and dmpcnt now fully setup
This commit is contained in:
wfjm
2018-10-14 15:02:45 +02:00
parent 3eedd7f5c8
commit 37b2d63281
12 changed files with 123 additions and 101 deletions
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3
doc/CHANGELOG.md
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@@ -60,7 +60,8 @@ The full set of tests is only run for tagged releases.
- pdp11_sequencer: drive DM_STAT_SE.(cpbusy,idec,pcload,itimer), drop ITIMER
- pdp11_cache: drop CHIT, add DM_STAT_CA port, add detailed monitoring
- pdp11_tmu(_sb): use DM_STAT_CA instead of DM_STAT_SY
- sys_w11a_*.vhd: use DM_STAT_EXP
- ibdr_maxisys: add IDEC port, connect to EXTEVT of KW11P
- sys_w11a_*.vhd: use DM_STAT_EXP; IDEC to maxisys; setup PERFEXT
- RtclRw11Unit: fix for clang: M_virt() now public
- backend code review:
- use for C++ compiles also `-Wpedantic`

4
rtl/ibus/ibdlib.vhd
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@@ -1,4 +1,4 @@
-- $Id: ibdlib.vhd 1043 2018-09-09 10:20:12Z mueller $
-- $Id: ibdlib.vhd 1056 2018-10-13 16:01:17Z mueller $
--
-- Copyright 2008-2018 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@@ -19,6 +19,7 @@
-- Tool versions: ise 8.2-14.7; viv 2014.4-2018.2; ghdl 0.18-0.34
-- Revision History:
-- Date Rev Version Comment
-- 2018-10-13 1055 1.3.2 update ibdr_maxisys (add IDEC port)
-- 2018-09-08 1043 1.3.1 update ibd_kw11p
-- 2017-01-29 847 1.3.1 add ibdr_deuna
-- 2015-05-09 676 1.3 start/stop/suspend overhaul
@@ -301,6 +302,7 @@ component ibdr_maxisys is -- ibus(rem) full system
RESET : in slbit; -- reset
BRESET : in slbit; -- ibus reset
ITIMER : in slbit; -- instruction timer
IDEC : in slbit; -- instruction decode
CPUSUSP : in slbit; -- cpu suspended
RB_LAM : out slv16_1; -- remote attention vector
IB_MREQ : in ib_mreq_type; -- ibus request

9
rtl/ibus/ibdr_maxisys.vhd
View File

@@ -1,4 +1,4 @@
-- $Id: ibdr_maxisys.vhd 1043 2018-09-09 10:20:12Z mueller $
-- $Id: ibdr_maxisys.vhd 1056 2018-10-13 16:01:17Z mueller $
--
-- Copyright 2009-2018 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@@ -32,10 +32,11 @@
-- ib_intmap24
-- Test bench: -
-- Target Devices: generic
-- Tool versions: ise 8.2-14.7; viv 2014.4-2016.4; ghdl 0.18-0.33
-- Tool versions: ise 8.2-14.7; viv 2014.4-2018.2; ghdl 0.18-0.34
--
-- Synthesized:
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2018-10-13 1055 14.7 131013 xc6slx16-2 774 1720 30 584 s 8.5 +KW11P
-- 2017-01-29 847 14.7 131013 xc6slx16-2 712 1628 30 599 s 8.5 +DEUNA
-- 2017-01-28 846 14.7 131013 xc6slx16-2 668 1562 30 577 s 8.5 intmap24
-- 2017-01-28 683 viv 2016.4 xc7a100t-1 683 1684 48 - -
@@ -48,6 +49,7 @@
--
-- Revision History:
-- Date Rev Version Comment
-- 2018-10-13 1055 1.5 add IDEC port, connect to EXTEVT of KW11P
-- 2018-09-08 1043 1.4.2 add KW11P;
-- 2017-01-29 847 1.4.1 add DEUNA; rename generic labels
-- 2017-01-28 846 1.4 use ib_intmap24
@@ -112,6 +114,7 @@ entity ibdr_maxisys is -- ibus(rem) full system
RESET : in slbit; -- reset
BRESET : in slbit; -- ibus reset
ITIMER : in slbit; -- instruction timer
IDEC : in slbit; -- instruction decode
CPUSUSP : in slbit; -- cpu suspended
RB_LAM : out slv16_1; -- remote attention vector
IB_MREQ : in ib_mreq_type; -- ibus request
@@ -276,7 +279,7 @@ begin
CE_MSEC => CE_MSEC,
RESET => RESET,
BRESET => BRESET,
EXTEVT => '0',
EXTEVT => IDEC,
CPUSUSP => CPUSUSP,
IB_MREQ => IB_MREQ,
IB_SRES => IB_SRES_KW11P,

22
rtl/sys_gen/w11a/arty_bram/sys_w11a_br_arty.vhd
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@@ -1,4 +1,4 @@
-- $Id: sys_w11a_br_arty.vhd 1055 2018-10-12 17:53:52Z mueller $
-- $Id: sys_w11a_br_arty.vhd 1056 2018-10-13 16:01:17Z mueller $
--
-- Copyright 2016-2018 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@@ -37,6 +37,7 @@
--
-- Synthesized:
-- Date Rev viv Target flop lutl lutm bram slic
-- 2018-10-13 1055 2017.2 xc7a35t-1 2560 5499 170 47.5 1699 +dmpcnt
-- 2018-09-15 1045 2017.2 xc7a35t-1 2337 5188 138 47.5 1611 +KW11P
-- 2018-08-11 1038 2018.2 xc7a35t-1 2283 5190 138 47.5 1602
-- 2018-08-11 1038 2018.1 xc7a35t-1 2283 5193 138 47.5 1616
@@ -53,7 +54,7 @@
--
-- Revision History:
-- Date Rev Version Comment
-- 2018-10-07 1054 1.3 use DM_STAT_EXP
-- 2018-10-13 1055 1.3 use DM_STAT_EXP; IDEC to maxisys; setup PERFEXT
-- 2016-04-02 758 1.2.1 add rbd_usracc (bitfile+jtag timestamp access)
-- 2016-03-28 755 1.2 use serport_2clock2
-- 2016-03-19 748 1.1.2 define rlink SYSID
@@ -314,14 +315,14 @@ begin
SER_MONI => SER_MONI
);
PERFEXT(0) <= '0';
PERFEXT(1) <= '0';
PERFEXT(2) <= '0';
PERFEXT(3) <= '0';
PERFEXT(4) <= '0';
PERFEXT(5) <= '0';
PERFEXT(6) <= '0';
PERFEXT(7) <= CE_USEC;
PERFEXT(0) <= '0'; -- unused (ext_rdrhit)
PERFEXT(1) <= '0'; -- unused (ext_wrrhit)
PERFEXT(2) <= '0'; -- unused (ext_wrflush)
PERFEXT(3) <= SER_MONI.rxact; -- ext_rlrxact
PERFEXT(4) <= not SER_MONI.rxok; -- ext_rlrxback
PERFEXT(5) <= SER_MONI.txact; -- ext_rltxact
PERFEXT(6) <= not SER_MONI.txok; -- ext_rltxback
PERFEXT(7) <= CE_USEC; -- ext_usec
SYS70 : pdp11_sys70 -- 1 cpu system ----------------------
port map (
@@ -361,6 +362,7 @@ begin
RESET => GRESET,
BRESET => BRESET,
ITIMER => DM_STAT_EXP.se_itimer,
IDEC => DM_STAT_EXP.se_idec,
CPUSUSP => CP_STAT.cpususp,
RB_LAM => RB_LAM(15 downto 1),
IB_MREQ => IB_MREQ,

21
rtl/sys_gen/w11a/artys7_bram/sys_w11a_br_as7.vhd
View File

@@ -1,4 +1,4 @@
-- $Id: sys_w11a_br_as7.vhd 1055 2018-10-12 17:53:52Z mueller $
-- $Id: sys_w11a_br_as7.vhd 1056 2018-10-13 16:01:17Z mueller $
--
-- Copyright 2018- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@@ -45,7 +45,7 @@
--
-- Revision History:
-- Date Rev Version Comment
-- 2018-10-07 1054 1.1 use DM_STAT_EXP
-- 2018-10-13 1055 1.1 use DM_STAT_EXP; IDEC to maxisys; setup PERFEXT
-- 2018-08-11 1038 1.0 Initial version (derived from sys_w11a_aa7)
------------------------------------------------------------------------------
--
@@ -293,14 +293,14 @@ begin
SER_MONI => SER_MONI
);
PERFEXT(0) <= '0';
PERFEXT(1) <= '0';
PERFEXT(2) <= '0';
PERFEXT(3) <= '0';
PERFEXT(4) <= '0';
PERFEXT(5) <= '0';
PERFEXT(6) <= '0';
PERFEXT(7) <= CE_USEC;
PERFEXT(0) <= '0'; -- unused (ext_rdrhit)
PERFEXT(1) <= '0'; -- unused (ext_wrrhit)
PERFEXT(2) <= '0'; -- unused (ext_wrflush)
PERFEXT(3) <= SER_MONI.rxact; -- ext_rlrxact
PERFEXT(4) <= not SER_MONI.rxok; -- ext_rlrxback
PERFEXT(5) <= SER_MONI.txact; -- ext_rltxact
PERFEXT(6) <= not SER_MONI.txok; -- ext_rltxback
PERFEXT(7) <= CE_USEC; -- ext_usec
SYS70 : pdp11_sys70 -- 1 cpu system ----------------------
port map (
@@ -340,6 +340,7 @@ begin
RESET => GRESET,
BRESET => BRESET,
ITIMER => DM_STAT_EXP.se_itimer,
IDEC => DM_STAT_EXP.se_idec,
CPUSUSP => CP_STAT.cpususp,
RB_LAM => RB_LAM(15 downto 1),
IB_MREQ => IB_MREQ,

22
rtl/sys_gen/w11a/basys3/sys_w11a_b3.vhd
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@@ -1,4 +1,4 @@
-- $Id: sys_w11a_b3.vhd 1055 2018-10-12 17:53:52Z mueller $
-- $Id: sys_w11a_b3.vhd 1056 2018-10-13 16:01:17Z mueller $
--
-- Copyright 2015-2018 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@@ -36,6 +36,7 @@
--
-- Synthesized:
-- Date Rev viv Target flop lutl lutm bram slic
-- 2018-10-13 1055 2017.2 xc7a35t-1 2698 5636 170 47.5 1723 +dmpcnt
-- 2018-09-15 1045 2017.2 xc7a35t-1 2475 5282 138 47.5 1643 +KW11P
-- 2017-04-16 881 2016.4 xc7a35t-1 2412 5228 138 47.5 1608 +DEUNA
-- 2017-01-29 846 2016.4 xc7a35t-1 2362 5239 138 47.5 1619 +int24
@@ -50,7 +51,7 @@
--
-- Revision History:
-- Date Rev Version Comment
-- 2018-10-07 1054 2.4 use DM_STAT_EXP
-- 2018-10-13 1055 2.4 use DM_STAT_EXP; IDEC to maxisys; setup PERFEXT
-- 2016-04-02 758 2.3.1 add rbd_usracc (bitfile+jtag timestamp access)
-- 2016-03-28 755 2.3 use serport_2clock2
-- 2016-03-19 748 2.2.2 define rlink SYSID
@@ -312,14 +313,14 @@ begin
SER_MONI => SER_MONI
);
PERFEXT(0) <= '0';
PERFEXT(1) <= '0';
PERFEXT(2) <= '0';
PERFEXT(3) <= '0';
PERFEXT(4) <= '0';
PERFEXT(5) <= '0';
PERFEXT(6) <= '0';
PERFEXT(7) <= CE_USEC;
PERFEXT(0) <= '0'; -- unused (ext_rdrhit)
PERFEXT(1) <= '0'; -- unused (ext_wrrhit)
PERFEXT(2) <= '0'; -- unused (ext_wrflush)
PERFEXT(3) <= SER_MONI.rxact; -- ext_rlrxact
PERFEXT(4) <= not SER_MONI.rxok; -- ext_rlrxback
PERFEXT(5) <= SER_MONI.txact; -- ext_rltxact
PERFEXT(6) <= not SER_MONI.txok; -- ext_rltxback
PERFEXT(7) <= CE_USEC; -- ext_usec
SYS70 : pdp11_sys70 -- 1 cpu system ----------------------
port map (
@@ -359,6 +360,7 @@ begin
RESET => GRESET,
BRESET => BRESET,
ITIMER => DM_STAT_EXP.se_itimer,
IDEC => DM_STAT_EXP.se_idec,
CPUSUSP => CP_STAT.cpususp,
RB_LAM => RB_LAM(15 downto 1),
IB_MREQ => IB_MREQ,

22
rtl/sys_gen/w11a/cmoda7/sys_w11a_c7.vhd
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@@ -1,4 +1,4 @@
-- $Id: sys_w11a_c7.vhd 1055 2018-10-12 17:53:52Z mueller $
-- $Id: sys_w11a_c7.vhd 1056 2018-10-13 16:01:17Z mueller $
--
-- Copyright 2017-2018 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@@ -38,6 +38,7 @@
--
-- Synthesized:
-- Date Rev viv Target flop lutl lutm bram slic
-- 2018-10-13 1055 2017.2 xc7a35t-1 3107 6215 182 50.0 1889 +dmpcnt
-- 2018-09-15 1045 2017.2 xc7a35t-1 2883 5891 150 50.0 1826 +KW11P
-- 2017-06-27 918 2017.1 xc7a35t-1 2823 5827 150 50.0 1814 16kB cache
-- 2017-06-25 916 2017.1 xc7a35t-1 2823 5796 150 47.5 1744 +BRAM
@@ -45,7 +46,7 @@
--
-- Revision History:
-- Date Rev Version Comment
-- 2018-10-07 1054 1.2 use DM_STAT_EXP
-- 2018-10-13 1055 1.2 use DM_STAT_EXP; IDEC to maxisys; setup PERFEXT
-- 2017-06-27 918 1.1.1 use 16 kB cache (all BRAM's used up)
-- 2017-06-25 916 1.1 add bram_memctl for 672 kB total memory
-- 2017-06-24 914 1.0 Initial version (derived from sys_w11a_n4)
@@ -284,14 +285,14 @@ begin
SER_MONI => SER_MONI
);
PERFEXT(0) <= '0';
PERFEXT(1) <= '0';
PERFEXT(2) <= '0';
PERFEXT(3) <= '0';
PERFEXT(4) <= '0';
PERFEXT(5) <= '0';
PERFEXT(6) <= '0';
PERFEXT(7) <= CE_USEC;
PERFEXT(0) <= '0'; -- unused (ext_rdrhit)
PERFEXT(1) <= '0'; -- unused (ext_wrrhit)
PERFEXT(2) <= '0'; -- unused (ext_wrflush)
PERFEXT(3) <= SER_MONI.rxact; -- ext_rlrxact
PERFEXT(4) <= not SER_MONI.rxok; -- ext_rlrxback
PERFEXT(5) <= SER_MONI.txact; -- ext_rltxact
PERFEXT(6) <= not SER_MONI.txok; -- ext_rltxback
PERFEXT(7) <= CE_USEC; -- ext_usec
SYS70 : pdp11_sys70 -- 1 cpu system ----------------------
port map (
@@ -331,6 +332,7 @@ begin
RESET => GRESET,
BRESET => BRESET,
ITIMER => DM_STAT_EXP.se_itimer,
IDEC => DM_STAT_EXP.se_idec,
CPUSUSP => CP_STAT.cpususp,
RB_LAM => RB_LAM(15 downto 1),
IB_MREQ => IB_MREQ,

22
rtl/sys_gen/w11a/nexys2/sys_w11a_n2.vhd
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@@ -1,4 +1,4 @@
-- $Id: sys_w11a_n2.vhd 1055 2018-10-12 17:53:52Z mueller $
-- $Id: sys_w11a_n2.vhd 1056 2018-10-13 16:01:17Z mueller $
--
-- Copyright 2010-2018 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@@ -34,6 +34,7 @@
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2018-10-13 1055 14.7 131013 xc3s1200e-4 3097 8484 510 5471 ok: +dmpcnt
-- 2018-09-15 1045 14.7 131013 xc3s1200e-4 2860 7983 446 5098 ok: +KW11P
-- 2017-04-30 888 14.7 131013 xc3s1200e-4 2806 7865 446 5043 ok: +fx2dbg
-- 2017-03-04 858 14.7 131013 xc3s1200e-4 2740 7713 446 4912 ok: +DEUNA
@@ -71,7 +72,7 @@
--
-- Revision History:
-- Date Rev Version Comment
-- 2018-10-07 1054 2.3 use DM_STAT_EXP
-- 2018-10-13 1055 2.3 use DM_STAT_EXP; IDEC to maxisys; setup PERFEXT
-- 2017-04-30 888 2.2 use SWI(7:6) to allow fx2 debug via LEDs
-- 2016-03-19 748 2.1.1 define rlink SYSID
-- 2015-05-09 677 2.1 start/stop/suspend overhaul; reset overhaul
@@ -400,14 +401,14 @@ begin
IO_FX2_DATA => IO_FX2_DATA
);
PERFEXT(0) <= '0';
PERFEXT(1) <= '0';
PERFEXT(2) <= '0';
PERFEXT(3) <= '0';
PERFEXT(4) <= '0';
PERFEXT(5) <= '0';
PERFEXT(6) <= '0';
PERFEXT(7) <= CE_USEC;
PERFEXT(0) <= '0'; -- unused (ext_rdrhit)
PERFEXT(1) <= '0'; -- unused (ext_wrrhit)
PERFEXT(2) <= '0'; -- unused (ext_wrflush)
PERFEXT(3) <= RLB_MONI.rxval and not RLB_MONI.rxhold; -- ext_rlrxact
PERFEXT(4) <= RLB_MONI.rxhold; -- ext_rlrxback
PERFEXT(5) <= RLB_MONI.txena and not RLB_MONI.txbusy; -- ext_rltxact
PERFEXT(6) <= RLB_MONI.txbusy; -- ext_rltxback
PERFEXT(7) <= CE_USEC; -- ext_usec
SYS70 : pdp11_sys70 -- 1 cpu system ----------------------
port map (
@@ -446,6 +447,7 @@ begin
RESET => GRESET,
BRESET => BRESET,
ITIMER => DM_STAT_EXP.se_itimer,
IDEC => DM_STAT_EXP.se_idec,
CPUSUSP => CP_STAT.cpususp,
RB_LAM => RB_LAM(15 downto 1),
IB_MREQ => IB_MREQ,

22
rtl/sys_gen/w11a/nexys3/sys_w11a_n3.vhd
View File

@@ -1,4 +1,4 @@
-- $Id: sys_w11a_n3.vhd 1055 2018-10-12 17:53:52Z mueller $
-- $Id: sys_w11a_n3.vhd 1056 2018-10-13 16:01:17Z mueller $
--
-- Copyright 2011-2018 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@@ -34,6 +34,7 @@
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2018-10-13 1055 14.7 131013 xc6slx16-2 3057 5822 201 2064 ok: +dmpcnt 90%
-- 2018-09-15 1045 14.7 131013 xc6slx16-2 2851 5453 177 1932 ok: +KW11P 84%
-- 2017-03-30 888 14.7 131013 xc6slx16-2 2790 5352 177 1943 ok: +fx2dbg 85%
-- 2017-03-04 858 14.7 131013 xc6slx16-2 2717 5273 177 1885 ok: +deuna 82%
@@ -56,7 +57,7 @@
--
-- Revision History:
-- Date Rev Version Comment
-- 2018-10-07 1054 2.3 use DM_STAT_EXP
-- 2018-10-13 1055 2.3 use DM_STAT_EXP; IDEC to maxisys; setup PERFEXT
-- 2017-04-30 888 2.2 use SWI(7:6) to allow fx2 debug via LEDs
-- 2016-03-19 748 2.1.1 define rlink SYSID
-- 2015-05-09 677 2.1 start/stop/suspend overhaul; reset overhaul
@@ -372,14 +373,14 @@ begin
IO_FX2_DATA => IO_FX2_DATA
);
PERFEXT(0) <= '0';
PERFEXT(1) <= '0';
PERFEXT(2) <= '0';
PERFEXT(3) <= '0';
PERFEXT(4) <= '0';
PERFEXT(5) <= '0';
PERFEXT(6) <= '0';
PERFEXT(7) <= CE_USEC;
PERFEXT(0) <= '0'; -- unused (ext_rdrhit)
PERFEXT(1) <= '0'; -- unused (ext_wrrhit)
PERFEXT(2) <= '0'; -- unused (ext_wrflush)
PERFEXT(3) <= RLB_MONI.rxval and not RLB_MONI.rxhold; -- ext_rlrxact
PERFEXT(4) <= RLB_MONI.rxhold; -- ext_rlrxback
PERFEXT(5) <= RLB_MONI.txena and not RLB_MONI.txbusy; -- ext_rltxact
PERFEXT(6) <= RLB_MONI.txbusy; -- ext_rltxback
PERFEXT(7) <= CE_USEC; -- ext_usec
SYS70 : pdp11_sys70 -- 1 cpu system ----------------------
port map (
@@ -418,6 +419,7 @@ begin
RESET => GRESET,
BRESET => BRESET,
ITIMER => DM_STAT_EXP.se_itimer,
IDEC => DM_STAT_EXP.se_idec,
CPUSUSP => CP_STAT.cpususp,
RB_LAM => RB_LAM(15 downto 1),
IB_MREQ => IB_MREQ,

24
rtl/sys_gen/w11a/nexys4/sys_w11a_n4.vhd
View File

@@ -1,4 +1,4 @@
-- $Id: sys_w11a_n4.vhd 1055 2018-10-12 17:53:52Z mueller $
-- $Id: sys_w11a_n4.vhd 1056 2018-10-13 16:01:17Z mueller $
--
-- Copyright 2013-2018 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@@ -36,7 +36,8 @@
--
-- Synthesized:
-- Date Rev viv Target flop lutl lutm bram slic MHz
-- 2019-09-15 1045 2017.2 xc7a100t-1 2926 5904 150 17.0 1884 80 +KW11P
-- 2018-10-13 1045 2017.2 xc7a100t-1 3146 6228 182 17.0 1979 80 +dmpcnt
-- 2018-09-15 1045 2017.2 xc7a100t-1 2926 5904 150 17.0 1884 80 +KW11P
-- 2017-04-22 885 2016.4 xc7a100t-1 2862 5859 150 12.0 1900 80 +dmcmon
-- 2017-04-16 881 2016.4 xc7a100t-1 2645 5621 138 12.0 1804 80 +DEUNA
-- 2017-01-29 846 2016.4 xc7a100t-1 2574 5496 138 12.0 1750 80 +int24
@@ -53,7 +54,7 @@
--
-- Revision History:
-- Date Rev Version Comment
-- 2018-10-07 1054 2.4 use DM_STAT_EXP
-- 2018-10-13 1055 2.4 use DM_STAT_EXP; IDEC to maxisys; setup PERFEXT
-- 2016-04-02 758 2.3.1 add rbd_usracc (bitfile+jtag timestamp access)
-- 2016-03-28 755 2.3 use serport_2clock2
-- 2016-03-19 748 2.2.1 define rlink SYSID
@@ -348,14 +349,14 @@ begin
SER_MONI => SER_MONI
);
PERFEXT(0) <= '0';
PERFEXT(1) <= '0';
PERFEXT(2) <= '0';
PERFEXT(3) <= '0';
PERFEXT(4) <= '0';
PERFEXT(5) <= '0';
PERFEXT(6) <= '0';
PERFEXT(7) <= CE_USEC;
PERFEXT(0) <= '0'; -- unused (ext_rdrhit)
PERFEXT(1) <= '0'; -- unused (ext_wrrhit)
PERFEXT(2) <= '0'; -- unused (ext_wrflush)
PERFEXT(3) <= SER_MONI.rxact; -- ext_rlrxact
PERFEXT(4) <= not SER_MONI.rxok; -- ext_rlrxback
PERFEXT(5) <= SER_MONI.txact; -- ext_rltxact
PERFEXT(6) <= not SER_MONI.txok; -- ext_rltxback
PERFEXT(7) <= CE_USEC; -- ext_usec
SYS70 : pdp11_sys70 -- 1 cpu system ----------------------
port map (
@@ -394,6 +395,7 @@ begin
RESET => GRESET,
BRESET => BRESET,
ITIMER => DM_STAT_EXP.se_itimer,
IDEC => DM_STAT_EXP.se_idec,
CPUSUSP => CP_STAT.cpususp,
RB_LAM => RB_LAM(15 downto 1),
IB_MREQ => IB_MREQ,

21
rtl/sys_gen/w11a/nexys4d_bram/sys_w11a_br_n4d.vhd
View File

@@ -1,4 +1,4 @@
-- $Id: sys_w11a_br_n4d.vhd 1055 2018-10-12 17:53:52Z mueller $
-- $Id: sys_w11a_br_n4d.vhd 1056 2018-10-13 16:01:17Z mueller $
--
-- Copyright 2017-2018 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@@ -42,7 +42,7 @@
--
-- Revision History:
-- Date Rev Version Comment
-- 2018-10-07 1054 1.1 use DM_STAT_EXP
-- 2018-10-13 1055 1.1 use DM_STAT_EXP; IDEC to maxisys; setup PERFEXT
-- 2017-01-04 838 1.0 Initial version (derived from sys_w11a_br_n4)
------------------------------------------------------------------------------
--
@@ -308,14 +308,14 @@ begin
SER_MONI => SER_MONI
);
PERFEXT(0) <= '0';
PERFEXT(1) <= '0';
PERFEXT(2) <= '0';
PERFEXT(3) <= '0';
PERFEXT(4) <= '0';
PERFEXT(5) <= '0';
PERFEXT(6) <= '0';
PERFEXT(7) <= CE_USEC;
PERFEXT(0) <= '0'; -- unused (ext_rdrhit)
PERFEXT(1) <= '0'; -- unused (ext_wrrhit)
PERFEXT(2) <= '0'; -- unused (ext_wrflush)
PERFEXT(3) <= SER_MONI.rxact; -- ext_rlrxact
PERFEXT(4) <= not SER_MONI.rxok; -- ext_rlrxback
PERFEXT(5) <= SER_MONI.txact; -- ext_rltxact
PERFEXT(6) <= not SER_MONI.txok; -- ext_rltxback
PERFEXT(7) <= CE_USEC; -- ext_usec
SYS70 : pdp11_sys70 -- 1 cpu system ----------------------
port map (
@@ -354,6 +354,7 @@ begin
RESET => GRESET,
BRESET => BRESET,
ITIMER => DM_STAT_EXP.se_itimer,
IDEC => DM_STAT_EXP.se_idec,
CPUSUSP => CP_STAT.cpususp,
RB_LAM => RB_LAM(15 downto 1),
IB_MREQ => IB_MREQ,

32
rtl/sys_gen/w11a/s3board/sys_w11a_s3.vhd
View File

@@ -1,4 +1,4 @@
-- $Id: sys_w11a_s3.vhd 1055 2018-10-12 17:53:52Z mueller $
-- $Id: sys_w11a_s3.vhd 1056 2018-10-13 16:01:17Z mueller $
--
-- Copyright 2007-2018 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@@ -33,11 +33,12 @@
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2018-09-15 1045 14.7 131013 xc3s1000-4 2670 7721 382 4851 OK: +KP11P 63%
-- 2017-03-04 858 14.7 131013 xc3s1000-4 2576 7471 382 4716 OK: +DEUNA 61%
-- 2017-01-29 846 14.7 131013 xc3s1000-4 2538 7355 382 4635 OK: +int24 60%
-- 2015-06-04 686 14.7 131013 xc3s1000-4 2158 6453 350 3975 OK: +TM11 51%
-- 2015-05-14 680 14.7 131013 xc3s1000-4 2087 6316 350 3928 OK: +RHRP 51%
-- 2018-10-13 1055 14.7 131013 xc3s1000-4 2890 8217 446 5177 OK: +dmpcnt 67%
-- 2018-09-15 1045 14.7 131013 xc3s1000-4 2670 7721 382 4851 OK: +KP11P 63%
-- 2017-03-04 858 14.7 131013 xc3s1000-4 2576 7471 382 4716 OK: +DEUNA 61%
-- 2017-01-29 846 14.7 131013 xc3s1000-4 2538 7355 382 4635 OK: +int24 60%
-- 2015-06-04 686 14.7 131013 xc3s1000-4 2158 6453 350 3975 OK: +TM11 51%
-- 2015-05-14 680 14.7 131013 xc3s1000-4 2087 6316 350 3928 OK: +RHRP 51%
-- 2015-02-21 649 14.7 131013 xc3s1000-4 1643 5124 318 3176 OK: +RL11
-- 2014-12-22 619 14.7 131013 xc3s1000-4 1569 4768 302 2994 OK: +rbmon
-- 2014-12-20 614 14.7 131013 xc3s1000-4 1455 4523 302 2807 OK: -RL11,rlv4
@@ -77,7 +78,7 @@
--
-- Revision History:
-- Date Rev Version Comment
-- 2018-10-07 1054 2.2 use DM_STAT_EXP
-- 2018-10-13 1055 2.2 use DM_STAT_EXP; IDEC to maxisys; setup PERFEXT
-- 2016-03-19 748 2.1.1 define rlink SYSID
-- 2015-05-09 677 2.1 start/stop/suspend overhaul; reset overhaul
-- 2015-05-02 673 2.0 use pdp11_sys70 and pdp11_hio70; now in std form
@@ -350,14 +351,14 @@ begin
SER_MONI => SER_MONI
);
PERFEXT(0) <= '0';
PERFEXT(1) <= '0';
PERFEXT(2) <= '0';
PERFEXT(3) <= '0';
PERFEXT(4) <= '0';
PERFEXT(5) <= '0';
PERFEXT(6) <= '0';
PERFEXT(7) <= CE_USEC;
PERFEXT(0) <= '0'; -- unused (ext_rdrhit)
PERFEXT(1) <= '0'; -- unused (ext_wrrhit)
PERFEXT(2) <= '0'; -- unused (ext_wrflush)
PERFEXT(3) <= SER_MONI.rxact; -- ext_rlrxact
PERFEXT(4) <= not SER_MONI.rxok; -- ext_rlrxback
PERFEXT(5) <= SER_MONI.txact; -- ext_rltxact
PERFEXT(6) <= not SER_MONI.txok; -- ext_rltxback
PERFEXT(7) <= CE_USEC; -- ext_usec
SYS70 : pdp11_sys70 -- 1 cpu system ----------------------
port map (
@@ -396,6 +397,7 @@ begin
RESET => GRESET,
BRESET => BRESET,
ITIMER => DM_STAT_EXP.se_itimer,
IDEC => DM_STAT_EXP.se_idec,
CPUSUSP => CP_STAT.cpususp,
RB_LAM => RB_LAM(15 downto 1),
IB_MREQ => IB_MREQ,