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add M9312 (boot prom) emulation

Browse Source 
- ibus/ibdr_maxisys: instantiate ibd_m9312
- ibus/ibd_m9312: added, boot prom emulation
- librw11/Rw11Cpu: add m9312 setup and HasM9312()
- tbench
  - m9312: added, tbench for ibd_m9312
  - kw11p: renamed from w11a_kw11p
This commit is contained in:
wfjm 2019-05-05 09:00:04 +02:00
parent 6c7fa2fd11
commit 3c73f61593
23 changed files with 470 additions and 23 deletions
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9
doc/CHANGELOG.md
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@ -23,8 +23,17 @@ software or firmware builds or that the documentation is consistent.
The full set of tests is only run for tagged releases.
### Summary
- add m9312 boot prom emulation
### New features
- new components
- ibd_m9312: new boot prom emulation
- new verification codes
- test_m9312_all.tcl: tbench for m9312
### Changes
- renamed kw11p tbench from w11a_kw11p to kw11p
### Bug Fixes
### Known issues

10
rtl/ibus/ibd_m9312.vbom Normal file
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@ -0,0 +1,10 @@
# libs
../vlib/slvtypes.vhd
../vlib/memlib/memlib.vhd
iblib.vhd
# components
[sim]../vlib/memlib/ram_1swsr_wfirst_gen.vbom
[xst]../vlib/memlib/ram_1swsr_wfirst_gen_unisim.vbom
[vsyn]../vlib/memlib/ram_1swsr_wfirst_gen.vbom
# design
ibd_m9312.vhd

181
rtl/ibus/ibd_m9312.vhd Normal file
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@ -0,0 +1,181 @@
-- $Id: ibd_m9312.vhd 1145 2019-05-04 10:07:32Z mueller $
--
-- Copyright 2019- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 3, or (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: ibd_m9312 - syn
-- Description: ibus dev: M9312
--
-- Dependencies: memlib/ram_1swsr_wfirst_gen
-- Test bench: -
-- Target Devices: generic
-- Tool versions: ise 14.7; viv 2017.2; ghdl 0.35
--
-- Revision History:
-- Date Rev Version Comment
-- 2019-04-28 1142 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.memlib.all;
use work.iblib.all;
-- ----------------------------------------------------------------------------
entity ibd_m9312 is -- ibus dev: M9312
-- fixed address: 165***,173***
port (
CLK : in slbit; -- clock
RESET : in slbit; -- system reset
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type -- ibus response
);
end ibd_m9312;
architecture syn of ibd_m9312 is
-- 1 111 110 000 000 000
-- 5 432 109 876 543 210
-- Note: LO-ROM addr is 165xxx: 1 110 101 xxx xxx xx0
-- HI-ROM addr is 173xxx: 1 111 011 xxx xxx xx0
-- --> addr(12) is 0 for LO and 1 for HI
constant ibaddr_m9312_lo : slv16 := slv(to_unsigned(8#165000#,16));
constant ibaddr_m9312_hi : slv16 := slv(to_unsigned(8#173000#,16));
constant csr_ibf_locwe : integer := 7;
constant csr_ibf_enahi : integer := 1;
constant csr_ibf_enalo : integer := 0;
type regs_type is record -- state registers
ibselcsr : slbit; -- ibus select csr: LO-ROM(0)
ibselmem : slbit; -- ibus select mem: LO-ROM or HI-ROM
locwe : slbit; -- write enable for loc access
enahi : slbit; -- HI-ROM loc visible
enalo : slbit; -- LO-ROM loc visible
end record regs_type;
constant regs_init : regs_type := (
'0','0', -- ibselcsr,ibselmem
'0', -- locwe
'0','0' -- enahi,enalo
);
signal R_REGS : regs_type := regs_init;
signal N_REGS : regs_type := regs_init;
signal BRAM_WE : slbit := '0';
signal BRAM_DO : slv16 := (others=>'0');
signal BRAM_ADDR : slv9 := (others=>'0');
begin
BRAM : ram_1swsr_wfirst_gen
generic map (
AWIDTH => 9,
DWIDTH => 16)
port map (
CLK => CLK,
EN => '1',
WE => BRAM_WE,
ADDR => BRAM_ADDR,
DI => IB_MREQ.din,
DO => BRAM_DO
);
BRAM_ADDR <= IB_MREQ.addr(12) & IB_MREQ.addr(8 downto 1);
proc_regs: process (CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
R_REGS <= regs_init;
else
R_REGS <= N_REGS;
end if;
end if;
end process proc_regs;
proc_next : process (R_REGS, IB_MREQ, BRAM_DO)
variable r : regs_type := regs_init;
variable n : regs_type := regs_init;
variable idout : slv16 := (others=>'0');
variable ibreq : slbit := '0';
variable iback : slbit := '0';
variable imemwe : slbit := '0';
begin
r := R_REGS;
n := R_REGS;
idout := (others=>'0');
ibreq := IB_MREQ.re or IB_MREQ.we;
iback := '0';
imemwe := '0';
-- ibus address decoder
n.ibselcsr := '0';
n.ibselmem := '0';
if IB_MREQ.aval='1' then
if IB_MREQ.addr(12 downto 1)=ibaddr_m9312_lo(12 downto 1) then
n.ibselcsr := '1';
end if;
if IB_MREQ.addr(12 downto 9)=ibaddr_m9312_lo(12 downto 9) or
IB_MREQ.addr(12 downto 9)=ibaddr_m9312_hi(12 downto 9) then
n.ibselmem := '1';
end if;
end if;
-- ibus transactions
if IB_MREQ.racc = '1' then -- rem side --------------------------
if r.ibselcsr = '1' then -- csr access
idout(csr_ibf_locwe) := r.locwe;
idout(csr_ibf_enahi) := r.enahi;
idout(csr_ibf_enalo) := r.enalo;
if IB_MREQ.we = '1' then
n.locwe := IB_MREQ.din(csr_ibf_locwe);
n.enahi := IB_MREQ.din(csr_ibf_enahi);
n.enalo := IB_MREQ.din(csr_ibf_enalo);
end if;
iback := ibreq;
end if;
else -- loc side --------------------------
if r.ibselmem = '1' then -- mem access
idout := BRAM_DO;
if IB_MREQ.re = '1' then -- read request
if IB_MREQ.addr(12) = '0' then -- LO-ROM
iback := r.enalo; -- ack if enabled
else -- HI-ROM
iback := r.enahi; -- ack if enabled
end if;
elsif IB_MREQ.we = '1' then -- write request
iback := r.locwe;
imemwe := r.locwe;
end if;
end if;
end if; -- IB_MREQ.racc
N_REGS <= n;
BRAM_WE <= imemwe;
IB_SRES.dout <= idout;
IB_SRES.ack <= iback;
IB_SRES.busy <= '0';
end process proc_next;
end syn;

13
rtl/ibus/ibdlib.vhd
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@ -1,4 +1,4 @@
-- $Id: ibdlib.vhd 1139 2019-04-27 14:00:38Z mueller $
-- $Id: ibdlib.vhd 1142 2019-04-28 19:27:57Z mueller $
--
-- Copyright 2008-2019 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@ -19,6 +19,7 @@
-- Tool versions: ise 8.2-14.7; viv 2014.4-2018.3; ghdl 0.18-0.35
-- Revision History:
-- Date Rev Version Comment
-- 2019-04-28 1142 1.3.8 add ibd_m9312
-- 2019-04-26 1139 1.3.7 add ibdr_dl11_buf
-- 2019-04-14 1131 1.3.6 RLIM_CEV now slv8
-- 2019-04-07 1129 1.3.5 add ibdr_pc11_buf
@ -326,6 +327,16 @@ component ibdr_lp11_buf is -- ibus dev(rem): LP11 (buffered)
);
end component;
component ibd_m9312 is -- ibus dev: M9312
-- fixed address: 165***,173***
port (
CLK : in slbit; -- clock
RESET : in slbit; -- system reset
IB_MREQ : in ib_mreq_type; -- ibus request
IB_SRES : out ib_sres_type -- ibus response
);
end component;
component ibdr_sdreg is -- ibus dev(rem): Switch/Display regs
-- fixed address: 177570
port (

6
rtl/ibus/ibdr_dl11_buf.vhd
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@ -1,4 +1,4 @@
-- $Id: ibdr_dl11_buf.vhd 1140 2019-04-28 10:21:21Z mueller $
-- $Id: ibdr_dl11_buf.vhd 1144 2019-05-01 18:39:26Z mueller $
--
-- Copyright 2019- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@ -229,7 +229,7 @@ begin
variable ixbufwe : slbit := '0';
variable ixbufrst : slbit := '0';
variable ixrlimsta : slbit := '0';
begin
begin
r := R_REGS;
n := R_REGS;
@ -320,7 +320,7 @@ begin
else -- write to full fifo
iback := '0'; -- signal nak
end if;
end if;
end if;
end if;
when ibaddr_xcsr => -- XCSR -- transmit control status ---

1
rtl/ibus/ibdr_maxisys.vbom
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@ -19,6 +19,7 @@ ibdr_pc11.vbom
ibdr_pc11_buf.vbom
ibdr_lp11.vbom
ibdr_lp11_buf.vbom
ibd_m9312.vbom
ibdr_sdreg.vbom
ib_sres_or_4.vbom
ib_sres_or_3.vbom

20
rtl/ibus/ibdr_maxisys.vhd
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@ -1,4 +1,4 @@
-- $Id: ibdr_maxisys.vhd 1139 2019-04-27 14:00:38Z mueller $
-- $Id: ibdr_maxisys.vhd 1142 2019-04-28 19:27:57Z mueller $
--
-- Copyright 2009-2019 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@ -30,6 +30,7 @@
-- ibdr_pc11_buf
-- ibdr_lp11
-- ibdr_lp11_buf
-- ibd_m9312
-- ibdr_sdreg
-- ib_sres_or_4
-- ib_sres_or_3
@ -192,6 +193,7 @@ architecture syn of ibdr_maxisys is
signal IB_SRES_DL11_1 : ib_sres_type := ib_sres_init;
signal IB_SRES_PC11 : ib_sres_type := ib_sres_init;
signal IB_SRES_LP11 : ib_sres_type := ib_sres_init;
signal IB_SRES_M9312 : ib_sres_type := ib_sres_init;
signal IB_SRES_SDREG : ib_sres_type := ib_sres_init;
signal IB_SRES_1 : ib_sres_type := ib_sres_init;
@ -532,6 +534,17 @@ begin
);
end generate LP11BUF;
M9312: if sys_conf_ibd_m9312 generate
begin
ROM : ibd_m9312
port map (
CLK => CLK,
RESET => RESET,
IB_MREQ => IB_MREQ,
IB_SRES => IB_SRES_M9312
);
end generate M9312;
SDREG : ibdr_sdreg
port map (
CLK => CLK,
@ -567,11 +580,12 @@ begin
IB_SRES_OR => IB_SRES_3
);
SRES_OR_4 : ib_sres_or_3
SRES_OR_4 : ib_sres_or_4
port map (
IB_SRES_1 => IB_SRES_PC11,
IB_SRES_2 => IB_SRES_LP11,
IB_SRES_3 => IB_SRES_SDREG,
IB_SRES_3 => IB_SRES_M9312,
IB_SRES_4 => IB_SRES_SDREG,
IB_SRES_OR => IB_SRES_4
);

24
tools/src/librw11/Rw11Cpu.cpp
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@ -1,4 +1,4 @@
// $Id: Rw11Cpu.cpp 1133 2019-04-19 18:43:00Z mueller $
// $Id: Rw11Cpu.cpp 1143 2019-05-01 13:25:51Z mueller $
//
// Copyright 2013-2019 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
//
@ -13,6 +13,7 @@
//
// Revision History:
// Date Rev Version Comment
// 2019-04-30 1143 1.2.19 add m9312 setup and HasM9312()
// 2019-04-19 1133 1.2.18 add ExecWibr(),ExecRibr(); LoadAbs(): better trace
// 2019-04-13 1131 1.2.17 add defs for w11 cpu component addresses; add
// MemSize(),MemWriteByte(); LoadAbs(): return start,
@ -207,6 +208,7 @@ const uint16_t Rw11Cpu::kIMLOLIM;
const uint16_t Rw11Cpu::kIMADDR;
const uint16_t Rw11Cpu::kIMDATA;
const uint16_t Rw11Cpu::kM9BASE;
const uint16_t Rw11Cpu::kKWLBASE;
const uint16_t Rw11Cpu::kKWPBASE;
const uint16_t Rw11Cpu::kKWPCSR;
@ -232,6 +234,7 @@ Rw11Cpu::Rw11Cpu(const std::string& type)
fHasHbpt(0),
fHasIbmon(false),
fHasIbtst(false),
fHasM9312(false),
fHasKw11l(false),
fHasKw11p(false),
fHasIist(false),
@ -977,6 +980,7 @@ void Rw11Cpu::Dump(std::ostream& os, int ind, const char* text,
os << bl << " fHasHbpt: " << fHasHbpt << endl;
os << bl << " fHasIbmon: " << RosPrintf(fHasIbmon) << endl;
os << bl << " fHasIbtst: " << RosPrintf(fHasIbtst) << endl;
os << bl << " fHasM9312: " << RosPrintf(fHasM9312) << endl;
os << bl << " fHasKw11l: " << RosPrintf(fHasKw11l) << endl;
os << bl << " fHasKw11p: " << RosPrintf(fHasKw11p) << endl;
os << bl << " fHasIist: " << RosPrintf(fHasIist) << endl;
@ -1070,13 +1074,13 @@ void Rw11Cpu::SetupOpt()
// probe
// - memory size: read losize register
// - optional cpu components: dmscnt, dmcmon, dmhbpt and ibmon, ibtst
// - optional devices: Kw11-L, KW11-P, IIST
// - optional devices: KW11-L, KW11-P, M9312, IIST
RlinkCommandList clist;
int ims = AddRibr(clist, kMEMLOSIZE); // read losize
int isc = clist.AddRreg(Base()+kSCBASE+kSCCNTL);
clist.SetLastExpectStatus(0,0); // disable stat check
clist.SetLastExpectStatus(0,0);
int icm = clist.AddRreg(Base()+kCMBASE+kCMCNTL);
clist.SetLastExpectStatus(0,0);
@ -1094,14 +1098,17 @@ void Rw11Cpu::SetupOpt()
clist.SetLastExpectStatus(0,0);
int ipc = clist.AddRreg(Base()+kPCBASE+kPCCNTL);
clist.SetLastExpectStatus(0,0); // disable stat check
clist.SetLastExpectStatus(0,0);
// probe auxilliary cpu components: m9312, kw11-l, kw11-p, iist
int im9= AddRibr(clist, kM9BASE); // m9312 probe rem
clist.SetLastExpectStatus(0,0);
// probe auxilliary cpu components: kw11-l, kw11-p, iist
int ikwl= AddRibr(clist, kKWLBASE); // kw11-l probe rem
clist.SetLastExpectStatus(0,0);
int ikwp= AddRibr(clist, kKWPBASE + kKWPCSR); // kw11-p probe rem
clist.SetLastExpectStatus(0,0);
clist.SetLastExpectStatus(0,0);
int iii = AddRibr(clist, kIISTBASE + kIISTACR); // iist probe rem
clist.SetLastExpectStatus(0,0);
@ -1179,6 +1186,11 @@ void Rw11Cpu::SetupOpt()
AllIAddrMapInsert("kwl.csr", kKWLBASE);
}
fHasM9312 = (clist[im9].Status() & statmsk) == 0;
if (fHasM9312) {
AllIAddrMapInsert("m9.csr", kM9BASE);
}
fHasKw11p = (clist[ikwp].Status() & statmsk) == 0;
if (fHasKw11p) {
AllIAddrMapInsert("kwp.csr", kKWPBASE + kKWPCSR);

6
tools/src/librw11/Rw11Cpu.hpp
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@ -1,4 +1,4 @@
// $Id: Rw11Cpu.hpp 1133 2019-04-19 18:43:00Z mueller $
// $Id: Rw11Cpu.hpp 1143 2019-05-01 13:25:51Z mueller $
//
// Copyright 2013-2019 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
//
@ -13,6 +13,7 @@
//
// Revision History:
// Date Rev Version Comment
// 2019-04-30 1143 1.2.19 add HasM9312()
// 2019-04-19 1133 1.2.18 add ExecWibr(),ExecRibr()
// 2019-04-13 1131 1.2.17 add defs for w11 cpu component addresses; add
// MemSize(),MemWriteByte(); LoadAbs() returns start
@ -98,6 +99,7 @@ namespace Retro {
uint16_t HasHbpt() const;
bool HasIbmon() const;
bool HasIbtst() const;
bool HasM9312() const;
bool HasKw11l() const;
bool HasKw11p() const;
bool HasIist() const;
@ -318,6 +320,7 @@ namespace Retro {
static const uint16_t kITFIFO = 0x0006; //!< IT.FIFO reg offset
// defs for optional w11 aux components
static const uint16_t kM9BASE = 0165000; //!< M9312 ibus address
static const uint16_t kKWLBASE = 0177546; //!< KW11-L ibus address
static const uint16_t kKWPBASE = 0172540; //!< KW11-P ibus address
static const uint16_t kKWPCSR = 0x0000; //!< KWP.CSR reg offset
@ -347,6 +350,7 @@ namespace Retro {
uint16_t fHasHbpt; //!< has dmhbpt (hardware breakpoint)
bool fHasIbmon; //!< has ibmon (ibus monitor)
bool fHasIbtst; //!< has ibtst (ibus tester)
bool fHasM9312; //!< has m9312 (boot rom)
bool fHasKw11l; //!< has kw11-l (line clock)
bool fHasKw11p; //!< has kw11-p (prog clock)
bool fHasIist; //!< has iist (smp comm)

11
tools/src/librw11/Rw11Cpu.ipp
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@ -1,4 +1,4 @@
// $Id: Rw11Cpu.ipp 1131 2019-04-14 13:24:25Z mueller $
// $Id: Rw11Cpu.ipp 1143 2019-05-01 13:25:51Z mueller $
//
// Copyright 2013-2019 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
//
@ -13,6 +13,7 @@
//
// Revision History:
// Date Rev Version Comment
// 2019-04-30 1143 1.2.6 add HasM9312()
// 2019-04-13 1131 1.2.5 add MemSize()
// 2019-02-15 1112 1.2.4 add HasIbtst()
// 2018-09-23 1050 1.2.3 add HasPcnt()
@ -155,6 +156,14 @@ inline bool Rw11Cpu::HasIbtst() const
//------------------------------------------+-----------------------------------
//! FIXME_docs
inline bool Rw11Cpu::HasM9312() const
{
return fHasM9312;
}
//------------------------------------------+-----------------------------------
//! FIXME_docs
inline bool Rw11Cpu::HasKw11l() const
{
return fHasKw11l;

4
tools/src/librwxxtpp/RtclRw11Cpu.cpp
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@ -1,4 +1,4 @@
// $Id: RtclRw11Cpu.cpp 1131 2019-04-14 13:24:25Z mueller $
// $Id: RtclRw11Cpu.cpp 1143 2019-05-01 13:25:51Z mueller $
//
// Copyright 2013-2019 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
//
@ -13,6 +13,7 @@
//
// Revision History:
// Date Rev Version Comment
// 2019-04-30 1143 1.2.31 add HasM9312() getter
// 2019-04-12 1131 1.2.30 BUGFIX: M_wtcpu(): check cpu attn in no-server case
// add MemSize() getter; loadabs: add -trace and start
// 2019-03-10 1121 1.2.28 M_cp(): tranfer BlockDone values after rblk
@ -1551,6 +1552,7 @@ void RtclRw11Cpu::SetupGetSet()
fGets.Add<uint16_t> ("hashbpt", bind(&Rw11Cpu::HasHbpt, pobj));
fGets.Add<bool> ("hasibmon", bind(&Rw11Cpu::HasIbmon, pobj));
fGets.Add<bool> ("hasibtst", bind(&Rw11Cpu::HasIbtst, pobj));
fGets.Add<bool> ("hasm9312", bind(&Rw11Cpu::HasM9312, pobj));
fGets.Add<bool> ("haskw11l", bind(&Rw11Cpu::HasKw11l, pobj));
fGets.Add<bool> ("haskw11p", bind(&Rw11Cpu::HasKw11p, pobj));
fGets.Add<bool> ("hasiist", bind(&Rw11Cpu::HasIist, pobj));

5
tools/tbench/README.md
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@ -4,6 +4,10 @@ This directory tree contains the **w11 test bench** and is organized in
| --------- | ------- |
| [cp](cp) | test of CPU control port |
| [deuna](deuna) | test of `deuna` ibus device |
| [pc11](dl11) | test of `dl11` ibus device |
| [kw11p](kw11p) | test of `kw11p` ibus device |
| [pc11](lp11) | test of `lp11` ibus device |
| [pc11](m9312) | test of `m9312` ibus device |
| [pc11](pc11) | test of `pc11` ibus device |
| [rhrp](rhrp) | test of `rhrp` ibus device |
| [tm11](tm11) | test of `tm11` ibus device |
@ -12,5 +16,4 @@ This directory tree contains the **w11 test bench** and is organized in
| [w11a_hbpt](w11a_hbpt) | test of CPU `hbpt` unit (hardware breakpoint) |
| [w11a_ibmon](w11a_ibmon) | test of `ibd_ibmon` (ibus monitor) |
| [w11a_ibtst](w11a_ibtst) | test of `ibd_ibtst` (ibus test device) |
| [w11a_kw11p](w11a_kw11p) | test of `kw11p` ibus device (programmable clock) |
| [w11a_pcnt](w11a_pcnt) | test of CPU `pcnt` unit (performance counters) |

3
tools/tbench/cpu_all.dat
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@ -1,4 +1,4 @@
# $Id: cpu_all.dat 1115 2019-02-24 12:53:04Z mueller $
# $Id: cpu_all.dat 1143 2019-05-01 13:25:51Z mueller $
#
## steering file for all cpu tests
#
@ -11,6 +11,5 @@
#
@w11a_cmon/w11a_cmon_all.dat
@w11a_hbpt/w11a_hbpt_all.dat
@w11a_kw11p/w11a_kw11p_all.dat
@w11a_pcnt/w11a_pcnt_all.dat
#

5
tools/tbench/dev_all.dat
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@ -1,7 +1,10 @@
# $Id: dev_all.dat 1139 2019-04-27 14:00:38Z mueller $
# $Id: dev_all.dat 1143 2019-05-01 13:25:51Z mueller $
#
## steering file for all devices tests
#
@kw11p/kw11p_all.dat
@m9312/m9312_all.dat
#
@dl11/dl11_all.dat
@lp11/lp11_all.dat
@pc11/pc11_all.dat

2
tools/tbench/w11a_kw11p/w11a_kw11p_all.dat → tools/tbench/kw11p/kw11p_all.dat
View File

@ -1,4 +1,4 @@
# $Id: w11a_kw11p_all.dat 1045 2018-09-15 15:20:57Z mueller $
# $Id: kw11p_all.dat 1143 2019-05-01 13:25:51Z mueller $
#
## steering file for all w11a_kw11p tests
#

0
tools/tbench/w11a_kw11p/test_kw11p_ctr.tcl → tools/tbench/kw11p/test_kw11p_ctr.tcl
View File

0
tools/tbench/w11a_kw11p/test_kw11p_int.tcl → tools/tbench/kw11p/test_kw11p_int.tcl
View File

0
tools/tbench/w11a_kw11p/test_kw11p_regs.tcl → tools/tbench/kw11p/test_kw11p_regs.tcl
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5
tools/tbench/m9312/m9312_all.dat Normal file
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# $Id: m9312_all.dat 1143 2019-05-01 13:25:51Z mueller $
#
## steering file for all m9312 tests
#
test_m9312_all.tcl

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tools/tbench/m9312/test_m9312_all.tcl Normal file
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# $Id: test_m9312_all.tcl 1143 2019-05-01 13:25:51Z mueller $
#
# Copyright 2019- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
# License disclaimer see License.txt in $RETROBASE directory
#
# Revision History:
# Date Rev Version Comment
# 2019-04-30 1143 1.0 Initial version
#
# Test register response
# ----------------------------------------------------------------------------
rlc log "test_m9312_all: test m9312 response ---------------------------------"
if {[$cpu get hasm9312] == 0} {
rlc log " test_m9312_regs-W: no m9312 unit found, test aborted"
return
}
package require ibd_m9312
# -- Section A ---------------------------------------------------------------
rlc log " A1: test csr response (rem) -------------------------------"
# test csr bits
$cpu cp \
-wibr m9.csr [regbld ibd_m9312::RCSR locwe] \
-ribr m9.csr -edata [regbld ibd_m9312::RCSR locwe] \
-wibr m9.csr [regbld ibd_m9312::RCSR enahi] \
-ribr m9.csr -edata [regbld ibd_m9312::RCSR enahi] \
-wibr m9.csr [regbld ibd_m9312::RCSR enalo] \
-ribr m9.csr -edata [regbld ibd_m9312::RCSR enalo]
# test that only csr is rem accessible, and not rest of LO-ROM and HI-ROM
$cpu cp \
-ribr [expr $ibd_m9312::A_LOROM + 0002] -estaterr \
-ribr [expr $ibd_m9312::A_LOROM + 0776] -estaterr \
-ribr [expr $ibd_m9312::A_HIROM ] -estaterr \
-ribr [expr $ibd_m9312::A_HIROM + 0776] -estaterr
rlc log " A2: csr.locwe=1: loc write ROM ----------------------------"
$cpu cp \
-wibr m9.csr [regbld ibd_m9312::RCSR locwe] \
-wma [expr $ibd_m9312::A_LOROM + 0000] 0100000 \
-wma [expr $ibd_m9312::A_LOROM + 0200] 0100222 \
-wma [expr $ibd_m9312::A_LOROM + 0400] 0100444 \
-wma [expr $ibd_m9312::A_LOROM + 0600] 0100666 \
-wma [expr $ibd_m9312::A_LOROM + 0776] 0100777 \
-wma [expr $ibd_m9312::A_HIROM + 0000] 0101000 \
-wma [expr $ibd_m9312::A_HIROM + 0200] 0101222 \
-wma [expr $ibd_m9312::A_HIROM + 0400] 0101444 \
-wma [expr $ibd_m9312::A_HIROM + 0600] 0101666 \
-wma [expr $ibd_m9312::A_HIROM + 0776] 0101777
rlc log " A3: csr.locwe=0: loc write ROM fails ----------------------"
$cpu cp \
-wibr m9.csr [regbld ibd_m9312::RCSR enahi enalo] \
-wma [expr $ibd_m9312::A_LOROM + 0000] 0xdead -estaterr \
-wma [expr $ibd_m9312::A_LOROM + 0776] 0xbeaf -estaterr \
-wma [expr $ibd_m9312::A_HIROM + 0000] 0xdead -estaterr \
-wma [expr $ibd_m9312::A_HIROM + 0776] 0xbeaf -estaterr
rlc log " A4: csr.enalo=1,enahi=1: all ROM readable -----------------"
$cpu cp \
-wibr m9.csr [regbld ibd_m9312::RCSR enahi enalo] \
-ribr m9.csr -edata [regbld ibd_m9312::RCSR enahi enalo] \
-rma [expr $ibd_m9312::A_LOROM + 0000] -edata 0100000 \
-rma [expr $ibd_m9312::A_LOROM + 0200] -edata 0100222 \
-rma [expr $ibd_m9312::A_LOROM + 0400] -edata 0100444 \
-rma [expr $ibd_m9312::A_LOROM + 0600] -edata 0100666 \
-rma [expr $ibd_m9312::A_LOROM + 0776] -edata 0100777 \
-rma [expr $ibd_m9312::A_HIROM + 0000] -edata 0101000 \
-rma [expr $ibd_m9312::A_HIROM + 0200] -edata 0101222 \
-rma [expr $ibd_m9312::A_HIROM + 0400] -edata 0101444 \
-rma [expr $ibd_m9312::A_HIROM + 0600] -edata 0101666 \
-rma [expr $ibd_m9312::A_HIROM + 0776] -edata 0101777
rlc log " A4: csr.enalo=1,enahi=0: only LO-ROM visible --------------"
$cpu cp \
-wibr m9.csr [regbld ibd_m9312::RCSR enalo] \
-rma [expr $ibd_m9312::A_LOROM + 0000] -edata 0100000 \
-rma [expr $ibd_m9312::A_LOROM + 0776] -edata 0100777 \
-rma [expr $ibd_m9312::A_HIROM + 0000] -estaterr \
-rma [expr $ibd_m9312::A_HIROM + 0776] -estaterr
rlc log " A4: csr.enalo=0,enahi=1: only HI-ROM visible --------------"
$cpu cp \
-wibr m9.csr [regbld ibd_m9312::RCSR enahi] \
-rma [expr $ibd_m9312::A_LOROM + 0000] -estaterr \
-rma [expr $ibd_m9312::A_LOROM + 0776] -estaterr \
-rma [expr $ibd_m9312::A_HIROM + 0000] -edata 0101000 \
-rma [expr $ibd_m9312::A_HIROM + 0776] -edata 0101777
rlc log " A4: csr.enalo=0,enahi=0: no ROM visible -------------------"
$cpu cp \
-wibr m9.csr [regbld ibd_m9312::RCSR] \
-rma [expr $ibd_m9312::A_LOROM + 0000] -estaterr \
-rma [expr $ibd_m9312::A_LOROM + 0776] -estaterr \
-rma [expr $ibd_m9312::A_HIROM + 0000] -estaterr \
-rma [expr $ibd_m9312::A_HIROM + 0776] -estaterr

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# $Id: util.tcl 1143 2019-05-01 13:25:51Z mueller $
#
# Copyright 2019- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
#
# This program is free software; you may redistribute and/or modify it under
# the terms of the GNU General Public License as published by the Free
# Software Foundation, either version 3, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful, but
# WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
# or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
# for complete details.
#
# Revision History:
# Date Rev Version Comment
# 2019-05-01 1143 1.0 Initial version
#
package provide ibd_m9312 1.0
package require rlink
package require rw11util
package require rw11
namespace eval ibd_m9312 {
#
# setup register descriptions for ibd_m9312 --------------------------------
#
set A_LOROM 0165000
set A_HIROM 0173000
regdsc RCSR {locwe 7} {enahi 1} {enalo 0}
rw11util::regmap_add ibd_m9312 m9.csr {r? RCSR}
#
# boot: load m9312 from mac source and start -------------------------------
#
proc boot {{cpu "cpu0"} {fnam ""}} {
$cpu cp -stapc [load $cpu $fnam]
return;
}
#
# load: load m9312 from mac source -----------------------------------------
#
proc load {{cpu "cpu0"} {fnam ""}} {
if {$fnam eq ""} {
set fnam "$::env(RETROBASE)/tools/mcode/m9312/bootw11.mac"
}
if {! [file readable $fnam]} {
error "m9312::load-E: file '$fnam' not found"
}
$cpu cp -wibr m9.csr [regbld ibd_m9312::RCSR locwe]
if { [catch {loadfile $cpu $fnam} start] } {
$cpu cp -wibr m9.csr 0x0
error $start
}
$cpu cp -wibr m9.csr [regbld ibd_m9312::RCSR enalo enahi]
return $start;
}
#
# loadfile: helper to perform the actual file load -------------------------
#
proc loadfile {cpu fnam} {
set start 1;
if {[string match "*.mac" $fnam]} {
$cpu ldasm -file $fnam -sym ldasm_sym
if {[info exists ldasm_sym(...end)]} { set start $ldasm_sym(...end) }
} else {
$cpu ldabs $fnam start
}
if {($start < $ibd_m9312::A_LOROM ||
$start > [expr {$ibd_m9312::A_LOROM + 0776}]) &&
($start < $ibd_m9312::A_HIROM ||
$start > [expr {$ibd_m9312::A_HIROM + 0776}])} {
error "m9312::load-E: start address not specified or not in ROM"
}
return $start
}
}

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tools/tcl/rw11util/regmap.tcl
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@ -1,4 +1,4 @@
# $Id: regmap.tcl 1118 2019-03-05 19:26:39Z mueller $
# $Id: regmap.tcl 1143 2019-05-01 13:25:51Z mueller $
#
# Copyright 2015-2019 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
#
@ -13,6 +13,7 @@
#
# Revision History:
# Date Rev Version Comment
# 2019-04-30 1143 1.0.3 add ibd_m9312
# 2019-03-03 1118 1.0.2 add ibd_ibtst
# 2017-03-04 858 1.0.1 add ibd_deuna
# 2015-12-28 720 1.0 Initial version
@ -88,6 +89,7 @@ namespace eval rw11util {
package require ibd_ibmon
package require ibd_ibtst
package require ibd_lp11
package require ibd_m9312
package require ibd_pc11
package require ibd_rhrp
package require ibd_rk11

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tools/tcl/setup_packages
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@ -1,5 +1,5 @@
#! /usr/bin/env tclshcpp
# $Id: setup_packages 1118 2019-03-05 19:26:39Z mueller $
# $Id: setup_packages 1143 2019-05-01 13:25:51Z mueller $
#
# pkg_mkIndex uses tclLog to write, which by default writes to stderr
# this is 'make -s' unfriendly, so redefined tclLog to use plain puts
@ -32,6 +32,7 @@ pkg_mkIndex -verbose ibd_dl11 *.tcl
pkg_mkIndex -verbose ibd_ibmon *.tcl
pkg_mkIndex -verbose ibd_ibtst *.tcl
pkg_mkIndex -verbose ibd_lp11 *.tcl
pkg_mkIndex -verbose ibd_m9312 *.tcl
pkg_mkIndex -verbose ibd_pc11 *.tcl
pkg_mkIndex -verbose ibd_rhrp *.tcl
pkg_mkIndex -verbose ibd_rk11 *.tcl