mirror of
https://github.com/wfjm/w11.git
synced 2026-01-12 00:43:01 +00:00
wfjm
parent
b3f9a8be30
commit
4001ddd695
@ -4,7 +4,6 @@
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[](https://scan.coverity.com/projects/wfjm-w11)
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[](https://github.com/wfjm/w11/releases)
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### Overview
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The project contains the VHDL code for a **complete DEC PDP-11 system**:
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a
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@ -51,12 +50,12 @@ For more information look into:
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A short description of the directory layout
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[is provided separately](https://wfjm.github.io/home/w11/impl/dirlayout.html),
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the top level directories are
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the top-level directories are
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| Directory | Content |
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| --------- | ------- |
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| [doc](doc) | documentation |
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| [rtl](rtl) | HDL sources (mostly vhdl) |
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| [rtl](rtl) | HDL sources (mostly VHDL) |
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| [tools](tools) | many tools |
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### Note on freecores/w11
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@ -15,7 +15,7 @@
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and [w11a_V0.57](#user-content-w11a_V0.57))
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- added LP11,PC11 support
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(in [w11a_V0.58](#user-content-w11a_V0.58))
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- reference system now ISE 14.7 and Ubuntu 12.04 64 bit, ghdl 0.31
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- reference system now ISE 14.7 and Ubuntu 12.04 64 bit, GHDL 0.31
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- many code cleanups; use `numeric_std`
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- many documentation improvements
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- development status upgraded to beta (from alpha)
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@ -66,7 +66,7 @@
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### Summary
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- new reference system
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- switched from ISE 13.3 to 14.7.
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- map/par behaviour changed, unfortunately unfavorably for w11a.
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- map/par behavior changed, unfortunately unfavorably for w11a.
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On Nexys3 no timing closure anymore for 80 MHz, only 72 MHz can
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be achieved now.
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- new man pages (in `doc/man/man1/`)
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@ -77,7 +77,7 @@
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- new modules
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- rtl/vlib/xlib
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- s6_cmt_sfs_unisim - Spartan-6 CMT for simple frequency synthesis
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- s6_cmt_sfs_gsim - dito, simple ghdl simulation model
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- s6_cmt_sfs_gsim - dito, simple GHDL simulation model
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- tools/src/librutiltpp
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- RtclSignalAction - Tcl signal handler
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- RtclSystem - Tcl Unix system interface
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@ -113,7 +113,7 @@
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### Other updates
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- INSTALL_ghdl.txt - text reflects current situation on ghdl packages
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- INSTALL_ghdl.txt - text reflects current situation on GHDL packages
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<!-- --------------------------------------------------------------------- -->
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---
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@ -165,7 +165,7 @@
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### New features
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- new modules
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- rtl/bplib/fx2rlink - new vhdl lib with rlink over fx2 modules
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- rtl/bplib/fx2rlink - new VHDL lib with rlink over fx2 modules
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- ioleds_sp1c_fx2 - io activity leds for rlink_sp1c_fx2
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- rlink_sp1c_fx2 - rlink over serport + fx2 combo
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- tools/src/librw11
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@ -199,7 +199,7 @@
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Can be used stand-alone to generate 'absolute loader' format files,
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but also integrates tightly into the Tcl environment and is used as
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building block in the creation of CPU test benches.
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- use now doxygen 1.8.3.1, generate c++, tcl, and vhdl source docs
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- use now doxygen 1.8.3.1, generate c++, tcl, and VHDL source docs
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See section 9. in INSTALL.txt for details.
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### New features
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@ -216,14 +216,14 @@
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- asm-11 - simple, Macro-11 syntax subset compatible, assembler
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- asm-11_expect - expect checker for asm-11 test bench
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- tools/dox
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- *.Doxyfile - new descriptors c++,tcl,vhdl docs
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- make_dox - driver script to generate c++,tcl,vhdl doxygen docs
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- *.Doxyfile - new descriptors C++,Tcl,VHDL docs
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- make_dox - driver script to generate C++,Tcl,VHDL doxygen docs
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### Changes
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- vhdl module renames:
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- VHDL module renames:
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vlib/serport -> vlib/serportlib
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- vhdl module splits:
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- VHDL module splits:
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bplib/bpgen/bpgenlib -> bpgenlib + bpgenrbuslib
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- C++ class splits
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librtcltools/RtclProxyBase -> RtclCmdBase + RtclProxyBase
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@ -297,13 +297,13 @@ The version of several key tools and libraries changed:
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- rtl/sys_gen/tst_fx2loop/nexys2/ic3/sys_tst_fx2loop_ic3_n2
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- rtl/sys_gen/tst_rlink_cuff/nexys2/ic/sys_tst_rlink_cuff_ic_n2
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- tools/bin
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- xilinx_sdf_ghdl_filter: tool to patch ISE sdf files for usage with ghdl
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- xilinx_sdf_ghdl_filter: tool to patch ISE sdf files for usage with GHDL
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### Changes
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- documentation
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- added a 'system requirements' section in INSTALL.txt
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- added INSTALL_ghdl.txt and INSTALL_urjtag.txt covering ghdl and urjtag
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- added INSTALL_ghdl.txt and INSTALL_urjtag.txt covering GHDL and urjtag
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- added README_USB-VID-PID.txt
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- organizational changes
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- added TCLINC,RETRO_FX2_VID,RETRO_FX2_PID environment variables
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@ -385,7 +385,7 @@ The version of several key tools and libraries changed:
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- functional changes
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- use now 'a6' polynomial of Koopman et al for crc8 in rlink
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- with one exception all vhdl sources use now numeric_std
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- with one exception all VHDL sources use now numeric_std
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- module renames:
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vlib/xlib/dcm_sp_sfs_gsim -> vlib/xlib/dcm_sfs_gsim
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vlib/xlib/dcm_sp_sfs_unisim -> vlib/xlib/dcm_sfs_unisim_s3e
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@ -17,7 +17,7 @@
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(in [w11a_V0.65](#user-content-w11a_V0.65))
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- add TM11/TY10 tape support
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(in [w11a_V0.66](#user-content-w11a_V0.66))
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- reference system now ISE 14.7, Vivado 2014.4; Ubuntu 14.04 64 bit, ghdl 0.31
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- reference system now ISE 14.7, Vivado 2014.4; Ubuntu 14.04 64 bit, GHDL 0.31
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### Table of contents
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- Release [w11a_V0.70](#user-content-w11a_V0.70)
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@ -331,12 +331,12 @@
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- rtl/bplib/nexys4 - support for Digilent Nexys4 board
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- rtl/make_viv - make includes for Vivado
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- new files
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- tools/bin/xviv_ghdl_unisim - ghdl compile Vivado UNISIM & UNIMACRO libs
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- tools/bin/xviv_ghdl_unisim - GHDL compile Vivado UNISIM & UNIMACRO libs
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- new modules
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- rtl/ibus/ibdr_rl11 - ibus controller for RL11
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- rtl/vlib/rlink/ioleds_sp1c - io activity leds for rlink+serport_1clk
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- rtl/vlib/xlib
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- s7_cmt_sfs_gsim - Series-7 CMT: simple vhdl model
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- s7_cmt_sfs_gsim - Series-7 CMT: simple VHDL model
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- s7_cmt_sfs_unisim - Series-7 CMT: wrapper for UNISIM
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- rtl/w11a
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- pdp11_bram_memctl - simple BRAM based memctl
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@ -420,13 +420,13 @@
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### Known issues
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- resolved issues: _none_
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- new issues:
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- **V0.64-7**: ghdl simulated OS boots via ti_w11 (-n4 ect options) fail due to
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- **V0.64-7**: GHDL simulated OS boots via ti_w11 (-n4 ect options) fail due to
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a flow control issue (likely since V0.63).
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- **V0.64-6**: IO delays still unconstraint in vivado. All critical IOs use
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explicitly IOB flops, thus timing well defined.
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- **V0.64-5**: w11a_tb_guide.txt covers only ISE based tests
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(see also V0.64-4).
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- **V0.64-4**: No support for the Vivado simulator (xsim) yet. With ghdl only
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- **V0.64-4**: No support for the Vivado simulator (xsim) yet. With GHDL only
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functional simulations, post synthesis (_ssim) fails to compile.
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- **V0.64-3**: Highest baud rate with basys3 and nexys4 is 10 MBaud. 10 MBaud
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is not supported according to FTDI, but works. 12 MBaud in next release.
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@ -453,7 +453,7 @@
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### Remarks on reference system
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- still using tcl 8.5 (even though 8.6 is now default in Ubuntu 14.04)
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- don't use doxygen 1.8.8 and 1.8.9, it fails to generate vhdl docs
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- don't use doxygen 1.8.8 and 1.8.9, it fails to generate VHDL docs
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### New features
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@ -530,7 +530,7 @@ Notes:
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1. still using tcl 8.5 (even though 8.6 is now default in Ub 14.04)
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2. sdcc 3.x is not source compatible with sdcc 2.9. The Makefile
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allows to use both, see tools/fx2/src/README.txt .
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3. don't use doxygen 1.8.8, it fails to generate vhdl docs
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3. don't use doxygen 1.8.8, it fails to generate VHDL docs
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### New features
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@ -38,10 +38,10 @@
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results in a bit faster cache line load times. The overall performance
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of a w11a design is measurably, but marginally better.
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- many unit tests still used a ISE environment. All board independent
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tests were converted now to a vivado environment, only tests which
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really depend a FPGA not supported by vivado stay with ISE.
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tests were converted now to a Vivado environment, only tests which
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really depend an FPGA not supported by Vivado stay with ISE.
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- a total of 82 unit or system tests are currently available. Many of them
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can be executed by different simulation engines, ghdl or the ISE/vivado
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can be executed by different simulation engines, GHDL or the ISE/Vivado
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build-in simulators, and for different stages of the implementation flow,
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from initial behavioral simulation over post-synthesis functional to final
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post-routing timing simulation. This results in a large number of possible
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@ -76,7 +76,7 @@
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bench configuration is done in the first ns of the simulation and has
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thus completed well before all other activities.
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- finally a caveat: post-synthesis simulations work fine with ISE, but
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currently not with vivado, even in case of almost identical designs,
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currently not with Vivado, even in case of almost identical designs,
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like `sys_tst_rlink_n3` vs `sys_tst_rlink_n4`. Is under investigation.
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### Summary
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@ -143,7 +143,7 @@
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- generic_ghdl.mk - ghdl_clean: remove also gcov files
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- rtl/make_viv
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- generic_ghdl.mk - ghdl_clean: remove also gcov files
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- generic_vivado.mk - viv_clean: rm only vivado logs
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- generic_vivado.mk - viv_clean: rm only Vivado logs
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- generic_xsim.mk - xsim work dir now xsim.<mode>.<stem>
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- rtl/sys_gen/tst_serloop
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- */tb/tb_tst_serloop*.vhd - remove CLK_STOP logic
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@ -185,46 +185,46 @@
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---
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## <a id="w11a_V0.73">2016-06-26: w11a_V0.73 - svn rev 36(oc) 779(wfjm)</a>
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### Preface
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- the 'basic vivado support' added with V0.64 was a minimal effort port of
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the code base used under ISE, leading to sub-optimal results under vivado.
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- the FSM inference under vivado is quirky and has several issues. The
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- the 'basic Vivado support' added with V0.64 was a minimal effort port of
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the code base used under ISE, leading to sub-optimal results under Vivado.
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- the FSM inference under Vivado is quirky and has several issues. The
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most essential one prevented re-coding with 'one_hot' encoding, which
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lead to high logic depth and low clock rates. Proper work-arounds were
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applied to almost all FSMs, now vivado infers all (but one) properly
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applied to almost all FSMs, now Vivado infers all (but one) properly
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and re-codes them as 'one_hot'. That is especially important for the
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pdp11_sequencer, which has 113 states. The sys_w11a_n4 system can now
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run with up to 90 MHz (was 75-80 MHz before).
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- due to a remaining synthesis issue the dmscnt and dmcmon debug units
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are currently disabled for Artix based systems (see issue V0.73-3).
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- memory inference is now used for all distributed and block rams under
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vivado. The memory generators in memlib are still used under ISE
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Vivado. The memory generators in memlib are still used under ISE
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Note: they were initially setup to work around ISE synthesis issues.
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- vivado synthesis and implementation use now 'explore' type flows for
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- Vivado synthesis and implementation use now 'explore' type flows for
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optimal timing performance.
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- the two clock dram based fifo was re-written (as `fifo_2c_dram2`) to allow
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proper usage of vivado constraints (e.g. scoped xdc).
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- vivado is now the prime platform for all further development
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proper usage of Vivado constraints (e.g. scoped xdc).
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- Vivado is now the prime platform for all further development
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- the component test benches run now by default under Vivado with an
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Artix-7 as default target. The makefiles for ISE with a Spartan-6 target
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are available as `Makefile.ise` and via the `makeise` command.
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- a message filter (`xviv_msg_filter`) has been developed which lists only
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the unexpected message of a synthesis or implementation run. Filter
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rule sets (`.vmfset` files) are available for all designs.
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- full support for the vivado simuator `xsim` has been added, there are
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- full support for the Vivado simuator `xsim` has been added, there are
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make targets to build a behavioral simulation as well as post-synthesis,
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post-optimize, and post-routing functional and timing models. All these
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models are now created in separate sub-directories and can now co-exist.
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However see issues V0.73-1 and V0.73-2 for severe caveats on xsim.
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- vivado write_vhdl generates code which violates a vhdl language rule.
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- Vivado write_vhdl generates code which violates a VHDL language rule.
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Attributes of port signals are declared in the wrong place. xsim and
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other simulators accept this, but ghdl doesn't. As a work-around the
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other simulators accept this, but GHDL doesn't. As a work-around the
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generated code is cleaned up by a filter (see xviv_sim_vhdl_cleanup).
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- additional rlink devices
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- the XADC block, available on all 7Series FPGAs, is now accessible via
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rlink on all Arty, Basys3 and Nexys4 designs. Especially useful on the
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Arty board because on this board also the currents are monitored.
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- the USR_ACCESS register, available on all 7Series FPGAs, is now readable
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via rlink on all Arty, Basys3 and Nexys4 designs. The vivado build flow
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via rlink on all Arty, Basys3 and Nexys4 designs. The Vivado build flow
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initializes this register with the build timestamp. This allows to
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verify the build time of a design at run time.
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- the cache used by the w11a (`pdp11_cache`) was initialy developed with the
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@ -250,7 +250,7 @@
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### Summary
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- new reference system: switched to Vivado 2016.2 (from 2015.4)
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- code base cleaned-up for vivado, fsm now inferred
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- code base cleaned-up for Vivado, fsm now inferred
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- xsim support complete (but many issues to be resolved yet)
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- added configurable w11a cache
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- removed some never documented and now strategically obsolete designs:
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@ -268,7 +268,7 @@
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- cdc_vector_s0.vhd - cdc for a vector, 1 stage
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- rtl/vlib/memlib
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- fifo_2c_dram2.vhd - re-write of fifo_2c_dram to allow
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proper usage of vivado constraints
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proper usage of Vivado constraints
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- rtl/vlib/rbus
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- rb_sres_or_6.vhd - rbus result or, 6 input
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- rbd_usracc.vhd - return usr_access register
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@ -281,9 +281,9 @@
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- new files
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- tools/bin
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- xise_msg_summary - list all filtered ISE messages
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- xviv_msg_filter - message filter for vivado
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- xviv_msg_summary - list all filtered vivado messages
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- xviv_sim_vhdl_cleanup - cleanup vivado generated vhdl for ghdl
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- xviv_msg_filter - message filter for Vivado
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- xviv_msg_summary - list all filtered Vivado messages
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- xviv_sim_vhdl_cleanup - cleanup Vivado generated VHDL for GHDL
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- makeise - wrapper for make -f Makefile.ise
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- tools/tcl/rbtest
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- test_flow.tcl - test back pressure and flow control
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@ -294,10 +294,10 @@
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- rtl/bplib/*/tb/tb_*.vbom - use -UUT attribute
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- rtl/sys_gen/*/*/tb/tb_*.vbom - use -UUT attribute
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- rtl/make_ise
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- generic_ghdl.mk - use ghdl.?sim as workdir for ghdl
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- generic_ghdl.mk - use ghdl.?sim as workdir for GHDL
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- generic_xflow.mk - use .imfset for ISE message rules
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- rtl/make_viv
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- generic_ghdl.mk - use ghdl.?sim as workdir for ghdl
|
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- generic_ghdl.mk - use ghdl.?sim as workdir for GHDL
|
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- generic_vivado.mk - add [sorep]sim.v and %.vivado targets
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- vmfset support, use xviv_sim_vhdl_cleanup
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- generic_xsim.mk - [rep]sim models; use xsim.?sim as workdir
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@ -322,8 +322,8 @@
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- rtl/w11a
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- pdp11_bram_memctl.vhd - use memory inference now
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- pdp11_cache.vhd - now configurable size (8,16,32,64,128 kB)
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- pdp11_sequencer.vhd - proc_snum conditional (vivado fsm fix)
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- rtl/*/*.vbom - use memory inference for vivado
|
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- pdp11_sequencer.vhd - proc_snum conditional (Vivado fsm fix)
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- rtl/*/*.vbom - use memory inference for Vivado
|
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- rtl/*/*.vhd - workarounds and fixes to many FSMs
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- tools/bin
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- tbrun_tbw - use _bsim.log for behavioral sim log
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@ -365,24 +365,24 @@
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### Known issues
|
||||
- all issues: see README_known_issues.txt
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||||
- resolved issues:
|
||||
- **V0.72-1**: since vivado 2016.1 xelab builds models which use DPI in a
|
||||
mixed vhdl-verilog language environment.
|
||||
- **V0.72-1**: since Vivado 2016.1 xelab builds models which use DPI in a
|
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mixed VHDL-Verilog language environment.
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- **V0.72-2**: now full support to build behavioral as well as functional and
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timing simulations with xsim. See V.073-1 and 0.73-2 for caveats.
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||||
- **V0.64-7**: flow control issues with simulation models resolved
|
||||
- **V0.64-3**: basys3, nexys4 and arty designs support now 12 MBaud.
|
||||
- new issues:
|
||||
- **V0.73-1**: as of vivado 2016.2 `xelab` shows sometimes extremely long
|
||||
build times, especially for generated post-synthesis vhdl models. But also
|
||||
- **V0.73-1**: as of Vivado 2016.2 `xelab` shows sometimes extremely long
|
||||
build times, especially for generated post-synthesis VHDL models. But also
|
||||
building a behavioral simulation for a w11a design can take 25 min.
|
||||
Even though post-synthesis or post-routing models are now generated
|
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in verilog working with xsim is cumbersome and time consuming.
|
||||
in Verilog working with xsim is cumbersome and time consuming.
|
||||
- **V0.73-2**: Many post-synthesis functional and especially post-routing
|
||||
timing simulations currently fail due to startup and initialization
|
||||
problems. Cause is MMCM/PLL startup, which is not properly reflected
|
||||
in the test bench. Will be resolved in an upcoming release.
|
||||
- **V0.73-3**: The 'state number generator' code in `pdp11_sequencer` causes
|
||||
in vivado 2016.1 (and .2) that the main FSM isn't re-coded anymore, which
|
||||
in Vivado 2016.1 (and .2) that the main FSM isn't re-coded anymore, which
|
||||
has high impact on achievable clock rate. The two optional debug units
|
||||
depending on the state number, `dmscnt` and `dmcmon`, are therefore
|
||||
currently deactivated in all Artix based systems (but are available on
|
||||
@ -412,10 +412,10 @@
|
||||
- re-factored tbcore_rlink to support DPI and VHPI
|
||||
- Vivado supports with DPI (from SystemVerilog) a mechanism to call
|
||||
external C code. The rlink test bench code so far relies on VHPI, which
|
||||
is supported by ghdl, but not by ISE ISim or Vivado xsim. The code was
|
||||
restructured and can use now DPI or VHPI to support both ghdl and
|
||||
is supported by GHDL, but not by ISE ISim or Vivado xsim. The code was
|
||||
restructured and can use now DPI or VHPI to support both GHDL and
|
||||
Vivado. Unfortunately has Vivado 2015.4 a bug, DPI doesn't work in a
|
||||
mixed vhdl-verilog language environment (see Known issues), so the
|
||||
mixed VHDL-Verilog language environment (see Known issues), so the
|
||||
code base is there, but utilization will habe to wait.
|
||||
- Vivado synthesis by default keeps hierarchy. This leads to doubly defined
|
||||
modules if a component is used in both test bench and unit under test.
|
||||
@ -457,7 +457,7 @@
|
||||
- */tb/Makefile - Vivado now default, keep Makefile.ise
|
||||
- rtl/bplib/*/tb/tb_*.vhd - use s7_cmt_sfs_tb and serport_master_tb
|
||||
- rtl/vlib/comlib
|
||||
- comlib.vhd - add work-around for vivado 2015.4 issue
|
||||
- comlib.vhd - add work-around for Vivado 2015.4 issue
|
||||
- rtl/vlib/rbus
|
||||
- rb_sres_or_mon - supports 6 inputs now
|
||||
- rtl/vlib/serport
|
||||
@ -470,13 +470,13 @@
|
||||
- sys_w11a_b3 - hardwire XON=1, support XADC; 72 MHz now
|
||||
- sys_w11a_n4 - support XADC
|
||||
- tools/bin
|
||||
- tbrun_tbw - add vivado xsim and Makefile.ise support
|
||||
- tbrun_tbw - add Vivado xsim and Makefile.ise support
|
||||
- tbrun_tbwrri - use --sxon and --hxon instead of --xon
|
||||
- tbw - add XSim support
|
||||
- ti_w11 - add arty support, add -fx
|
||||
- vbomconv - add [ise,viv]; add @uut tag handling;
|
||||
add preliminary --(vsyn|vsim)_export;
|
||||
add vivado xsim support;
|
||||
add Vivado xsim support;
|
||||
- xtwi,xtwv - add BARE_PATH to provide clean environment
|
||||
|
||||
### Bug fixes
|
||||
@ -492,7 +492,7 @@
|
||||
|
||||
- new issues:
|
||||
- **V0.72-1**: Vivado 2015.4 xelab crashes when DPI is used in a mxied
|
||||
vhdl-verilog language environment. This prevents currently to
|
||||
VHDL-Verilog language environment. This prevents currently to
|
||||
build a xsim simulation model for rlink based test benches.
|
||||
- **V0.72-2**: xsim simulations with timing annotation not yet available.
|
||||
|
||||
|
||||
@ -27,7 +27,7 @@ The full set of tests is only run for tagged releases.
|
||||
### Summary
|
||||
- drop Travis (now defunct)
|
||||
- add preliminary GitHub Actions support
|
||||
- use vivado 2020.1 as default
|
||||
- use Vivado 2020.1 as default
|
||||
- use std=c++17 (requires gcc 7.3 or later)
|
||||
- automate oskit download and container file setup
|
||||
- automate testing of oskits
|
||||
@ -50,7 +50,7 @@ The full set of tests is only run for tagged releases.
|
||||
- tst_mig/nexys4d/sys_tst_mig_n4d: use 100 MHz MIG SYS_CLK; add clock monitor
|
||||
- tst_sram/nexys4d/sys_tst_sram_n4d: use 100 MHz MIG SYS_CLK
|
||||
- w11a/nexys4d/sys_w11a_n4d: use 100 MHz MIG SYS_CLK
|
||||
- */*.vhd: fixes for ghdl V0.36 -Whide warnings
|
||||
- */*.vhd: fixes for GHDL V0.36 -Whide warnings
|
||||
|
||||
### Bug Fixes
|
||||
- nexys4d/mig_a.prj: BUGFIX: SysResetPolarity ACTIVE HIGH
|
||||
@ -59,7 +59,7 @@ The full set of tests is only run for tagged releases.
|
||||
---
|
||||
## <a id="w11a_V0.79">2019-07-27: [w11a_V0.79](https://github.com/wfjm/w11/releases/tag/w11a_V0.79) - rev 1197(wfjm)</a>
|
||||
### Summary
|
||||
- use vivado 2019.1 as default
|
||||
- use Vivado 2019.1 as default
|
||||
- finalize coverity fixups, now defect free ([see blog](https://wfjm.github.io/blogs/w11/2019-06-14-coverity-fixes-done.html))
|
||||
- use SPDX license tags, remove boilerplate license disclaimers ([see blog](https://wfjm.github.io/blogs/w11/2019-07-21-spdx.html))
|
||||
- TM11: support odd record length, close [issue #8](https://github.com/wfjm/w11/issues/8)
|
||||
@ -87,7 +87,7 @@ The full set of tests is only run for tagged releases.
|
||||
- tap2file: add -v option
|
||||
- firmware changes
|
||||
- sys_w11a_arty: down-rate to 72 MHz, viv 2019.1 fails with 75 MHz
|
||||
- sys_w11a_*.vmfset: add new rule for vivado 2019.1
|
||||
- sys_w11a_*.vmfset: add new rule for Vivado 2019.1
|
||||
- pdp11_vmbox: support membe for em cacc access
|
||||
|
||||
### Bug Fixes
|
||||
@ -319,7 +319,7 @@ The full set of tests is only run for tagged releases.
|
||||
a `.travis.yml`.
|
||||
- use static source code analysis [Coverity Scan](https://scan.coverity.com),
|
||||
add [project wfjm/w11](https://scan.coverity.com/projects/wfjm-w11).
|
||||
The scans are manually uploaded, not automated via Travis (w11 is a `vhdl`
|
||||
The scans are manually uploaded, not automated via Travis (w11 is a `VHDL`
|
||||
project after all, so C++ backend code doesn't change so often). Coverity
|
||||
found a modest number of defects, most uncritical, but some real bugs.
|
||||
- the Coverity results triggered a general backend code review
|
||||
@ -330,7 +330,7 @@ The full set of tests is only run for tagged releases.
|
||||
- add KW11-P (programmable clock) to all w11 systems. It is usefull in test
|
||||
benches (fast interrupt source) and enables on the long run to port the
|
||||
2.10BSD kernel profiling code to 2.11BSD.
|
||||
- stay with vivado 2017.2 as default tool, 2017.2 to 2018.2 exhibit much
|
||||
- stay with Vivado 2017.2 as default tool, 2017.2 to 2018.2 exhibit much
|
||||
longer build times for w11 designs (see [w11 blog posting](https://wfjm.github.io/blogs/w11/2018-09-01-vivado-2018.2-much-slower.html))
|
||||
- the first Artix-7 designs for the nexys4 board where done in 2013 with
|
||||
ISE 14.5, later with 14.7, simply because the early Vivado versions were
|
||||
@ -341,7 +341,7 @@ The full set of tests is only run for tagged releases.
|
||||
### New features
|
||||
- travis support via `.travis.yml`
|
||||
- compiles the C++ backend
|
||||
- download the `ghdl` based test benches (can't be build under Travis)
|
||||
- download the `GHDL` based test benches (can't be build under Travis)
|
||||
- execute the test benches with `tbrun`
|
||||
- add KW11-P support, enable it in all w11a systems
|
||||
- add performance counters
|
||||
@ -358,7 +358,7 @@ The full set of tests is only run for tagged releases.
|
||||
- remove ISE 14.x build support for 7Series (mostly nexys4 designs)
|
||||
- Makefile: `make all_tcl` now quiet, use setup_packages_filt
|
||||
- tools changes
|
||||
- vbomconv: now allows to inject Tcl scripts into the vivado project setup
|
||||
- vbomconv: now allows to inject Tcl scripts into the Vivado project setup
|
||||
sequence via the `@tcl` directive.
|
||||
- xviv_msg_filter
|
||||
- display INFO Common 17-14 'further message disabled'
|
||||
@ -456,9 +456,9 @@ The full set of tests is only run for tagged releases.
|
||||
Spartan vs Artix performance a w11a port to the Arty S7 board was added.
|
||||
The design runs with 80 MHz, same clock rate as achieved with Artix-7 FPGAs.
|
||||
_Note_: the design is only simulation tested, was _not FPGA tested_ !!
|
||||
- use vivado 2017.2 as default (needed for Spartan-7 support). All vivado
|
||||
- use Vivado 2017.2 as default (needed for Spartan-7 support). All Vivado
|
||||
versions from 2017.3 to 2018.2 were tested. All designs build properly under
|
||||
vivado 2018.2, but the CPU time for a build increased very substantially,
|
||||
Vivado 2018.2, but the CPU time for a build increased very substantially,
|
||||
so they are currently not used as default build tool.
|
||||
|
||||
### New features
|
||||
@ -470,8 +470,8 @@ The full set of tests is only run for tagged releases.
|
||||
### Changes
|
||||
- xviv_msg_filter: allow {yyyy.x} tags (in addition to ranges)
|
||||
- xviv_msg_summary: check also for .bit and .dcp files
|
||||
- get vivado 2017.2 ready (needed for Spartan-7 support)
|
||||
- test vivado 2017.3 - 2018.2 ready
|
||||
- get Vivado 2017.2 ready (needed for Spartan-7 support)
|
||||
- test Vivado 2017.3 - 2018.2 ready
|
||||
- *.vmfset: update rules to cover 2017.4-2018.2
|
||||
- all designs build under 2017.2 and 2018.2
|
||||
|
||||
@ -484,7 +484,7 @@ The full set of tests is only run for tagged releases.
|
||||
They are now consistent with the License.txt file, which refers to GPL V3.
|
||||
- Add Digilent Cmod A7 (35 die size) support
|
||||
- Add [INSTALL_quickstart](INSTALL_quickstart.md)
|
||||
- get vivado 2017.1 ready
|
||||
- get Vivado 2017.1 ready
|
||||
- Added Unix 7th Edition oskit; rename 5th Edition kit
|
||||
- u5ed_rk: renamed from unix-v5_rk
|
||||
- u7ed_rp: added, very preliminary, boots on Cmod A7, further testing needed
|
||||
@ -512,7 +512,7 @@ The full set of tests is only run for tagged releases.
|
||||
- 17bit support for tst_sram
|
||||
- tst_sram.vhd: allow AWIDTH=17; sstat_rbf_awidth instead of _wide
|
||||
- tcl/tst_sram/*.tcl: 17bit support; use sstat(awidth); add isnarrow
|
||||
- get vivado 2017.1 ready
|
||||
- get Vivado 2017.1 ready
|
||||
- xviv_msg_filter: add version-range tag support
|
||||
- *.vmfset:
|
||||
- drop the nonsense 'Synth 8-6014' messages
|
||||
@ -542,7 +542,7 @@ The full set of tests is only run for tagged releases.
|
||||
- move to Ubuntu 16.04 as development platform
|
||||
- document urjtag build (jtag in Ubuntu 16.04 is broken)
|
||||
- add environment sanity wrappers for acroread,awk,firefox to ensure
|
||||
proper operation of vivado under Ubuntu 16.04
|
||||
proper operation of Vivado under Ubuntu 16.04
|
||||
- use -std=c++11 (gcc 4.7 or later)
|
||||
- for all FTDI USB-UART it is essential to set them to `low latency` mode.
|
||||
That was default for Linux kernels 2.6.32 to 4.4.52. Since about March
|
||||
@ -550,7 +550,7 @@ The full set of tests is only run for tagged releases.
|
||||
[kernel patch 9589541](https://patchwork.kernel.org/patch/9589541/).
|
||||
**For newer systems it is essential to install a udev rule** which
|
||||
automatically sets low latency, see [documentation](../tools/sys/README.md).
|
||||
- the cpu monitor dmcmon was not available in vivado systems due to synthesis
|
||||
- the cpu monitor dmcmon was not available in Vivado systems due to synthesis
|
||||
issues caused by dmscnt. Is resolved, dmcmon now part of sys_w11a_n4.
|
||||
- many improvements to the w11 shell in ti_w11: rbmon integrated, usage
|
||||
of ibmon and dmcmon streamlined.
|
||||
@ -613,7 +613,7 @@ The full set of tests is only run for tagged releases.
|
||||
- does not depend on full state number generation anymore
|
||||
- missed WAIT instructions so far, has been fixed
|
||||
- dmcmon included in sys_w11a_n4 again
|
||||
- full snum generation code gives bad synthesis under vivado (fine in ISE)
|
||||
- full snum generation code gives bad synthesis under Vivado (fine in ISE)
|
||||
- the updated dmcmon can life with a simple, category based, snum
|
||||
- move hook_*.tcl files to tools/oskiit/hook directory
|
||||
- w11 shell .bs now support ibus register names and ranges
|
||||
@ -711,7 +711,7 @@ The full set of tests is only run for tagged releases.
|
||||
## <a id="w11a_V0.742">2017-01-07: [w11a_V0.742](https://github.com/wfjm/w11/releases/tag/w11a_V0.742) - rev 841(wfjm)</a>
|
||||
|
||||
### Summary
|
||||
- fixes for Vivado 2016.4; all designs build under vivado 2016.4
|
||||
- fixes for Vivado 2016.4; all designs build under Vivado 2016.4
|
||||
- added **preliminary** support for Nexys4 DDR board (thanks to [Michael Lyle](https://github.com/mlyle) for testing!)
|
||||
- [w11 shell](../tools/tcl/rw11/shell.tcl) re-organized and expanded,
|
||||
now default in [ti_w11](../tools/bin/ti_w11)
|
||||
|
||||
@ -6,7 +6,7 @@
|
||||
|
||||
### Symptom summary
|
||||
- the `cpuerr` register is not cleared by a `$cpu cp -creset` command
|
||||
- the `cpuerr` status can affect cpu behaviour, e.g. yellow stack traps are
|
||||
- the `cpuerr` status can affect cpu behavior, e.g. yellow stack traps are
|
||||
only taken when the corresponding `cpuerr` flag is not set
|
||||
- this makes tbench test execution on FPGA potentially depending on pre-history
|
||||
|
||||
|
||||
@ -5,7 +5,7 @@
|
||||
- [Download](#user-content-download)
|
||||
- [System requirements](#user-content-sysreq)
|
||||
- [Setup environment variables](#user-content-envvar)
|
||||
- [Compile UNISIM/UNIMACRO/SIMPRIM libraries for ghdl](#user-content-ghdl-lib)
|
||||
- [Compile UNISIM/UNIMACRO/SIMPRIM libraries for GHDL](#user-content-ghdl-lib)
|
||||
- [Compile and install the support software](#user-content-build-tools)
|
||||
- [Compile sharable libraries](#user-content-build-cpp)
|
||||
- [Setup Tcl packages](#user-content-build-tcl)
|
||||
@ -40,7 +40,7 @@ working directory with the name represented as `<install-dir>`
|
||||
git checkout tags/<tag>
|
||||
|
||||
The GitHub repository contains the full version history since 2010.
|
||||
Prior to October 2016 the project was maintained on OpenCores, access
|
||||
Prior to October 2016, the project was maintained on OpenCores, access
|
||||
to the legacy svn repository is described in
|
||||
[INSTALL_from_opencores.md](INSTALL_from_opencores.md).
|
||||
|
||||
@ -49,7 +49,7 @@ to the legacy svn repository is described in
|
||||
This project contains not only VHDL code but also support software. Therefore
|
||||
quite a few software packages are expected to be installed. The following
|
||||
list gives the Ubuntu/Debian package names, but mapping this to other
|
||||
distributions should be straight forward.
|
||||
distributions should be straightforward.
|
||||
|
||||
- building the FPGA bit files requires the Xilinx design tools
|
||||
- Vivado WebPACK (for Series-7 based designs)
|
||||
@ -64,9 +64,9 @@ distributions should be straight forward.
|
||||
-> package: `tcl` `tcl-dev` `tcllib` `tclreadline`
|
||||
|
||||
- for VHDL simulations one needs
|
||||
- ghdl
|
||||
- GHDL
|
||||
-> see [INSTALL_ghdl.md](INSTALL_ghdl.md) for the unfortunately gory details
|
||||
- gtkwave
|
||||
- GTKWave
|
||||
-> package: `gtkwave`
|
||||
|
||||
- additional requirements for using Cypress FX (on Nexys2/3) see
|
||||
@ -78,9 +78,9 @@ distributions should be straight forward.
|
||||
|
||||
### <a id="envvar">Setup environment variables</a>
|
||||
|
||||
The make flows for building test benches (ghdl, Vivado xsim or ISE ISim based)
|
||||
and FPGA bit files (with Vivado or ISE) as well as the support software
|
||||
(mainly the rlink backend server) requires the definition of the environment
|
||||
The `make` flows for building test benches (GHDL, Vivado xsim or ISE ISim based)
|
||||
and FPGA bit files (with Vivado or ISE), as well as the support software
|
||||
(mainly the rlink backend server), requires the definition of the environment
|
||||
variables:
|
||||
|
||||
| Variable | Comment |
|
||||
@ -105,7 +105,7 @@ For bash and alike use
|
||||
export LD_LIBRARY_PATH=$LD_LIBRARY_PATH:$RETROBASE/tools/lib
|
||||
export MANPATH=$MANPATH:$RETROBASE/tools/man
|
||||
|
||||
Boost was essential in the pre-c++11 times, but has been completely replaced
|
||||
Boost was essential in the pre-c++11 times but has been completely replaced
|
||||
by std:: classes provided by c++11. In most cases the Tcl version coming with
|
||||
the distribution will work, in those cases simply use
|
||||
|
||||
@ -116,15 +116,15 @@ and don't setup `BOOSTINC` and `BOOSTLIB`.
|
||||
|
||||
After that building functional model based test benches will work. If you
|
||||
want to also build post-synthesis or post-place&route test benches
|
||||
read next section.
|
||||
read the next section.
|
||||
|
||||
For Cypress FX2 (on Nexys2/3) related setup see
|
||||
[INSTALL_fx2_support.md](INSTALL_fx2_support.md).
|
||||
|
||||
### <a id="ghdl-lib">Compile UNISIM/UNIMACRO/SIMPRIM libraries for ghdl</a>
|
||||
### <a id="ghdl-lib">Compile UNISIM/UNIMACRO/SIMPRIM libraries for GHDL</a>
|
||||
|
||||
The build system for test benches also supports test benches run against the
|
||||
gate level models derived after synthesis or place&route. In this case ghdl
|
||||
gate level models derived after synthesis or place&route. In this case GHDL
|
||||
has to link against a compiled a `UNISIM`, `UNIMACRO` or `SIMPRIM` library.
|
||||
The details are described in
|
||||
- [README_buildsystem_Vivado.md](README_buildsystem_Vivado.md#user-content-ghdllibs)
|
||||
@ -134,7 +134,7 @@ The details are described in
|
||||
|
||||
#### <a id="build-cpp">Compile sharable libraries</a>
|
||||
|
||||
The backend code base uses now many `c++11` langauge features, e.g.
|
||||
The backend codebase uses now many `c++11` language features, e.g.
|
||||
`nullptr`, `auto`, lambda functions, list initialization, range-based `for`,
|
||||
to name the most prominent.
|
||||
A C++ compiler with full `c++11` support is therefore needed, so either
|
||||
@ -158,7 +158,7 @@ To build all sharable libraries
|
||||
make -j 4
|
||||
|
||||
Default is to compile with `-O2` and without `-g`. These options can be
|
||||
overwritten with the `CXXOPTFLAGS` enviromnent variable (or make opion).
|
||||
overwritten with the `CXXOPTFLAGS` environment variable (or make option).
|
||||
To build with `-O3` optimize use
|
||||
|
||||
make -j 4 CXXOPTFLAGS=-O3
|
||||
@ -187,7 +187,7 @@ To use these packages it is convenient to make them available via the
|
||||
lappend auto_path [file join $env(RETROBASE) tools tcl]
|
||||
lappend auto_path [file join $env(RETROBASE) tools lib]
|
||||
|
||||
The w11 project contains two ready to use `.tclshrc` or `.wishrc`
|
||||
The w11 project contains two ready-to-use `.tclshrc` or `.wishrc`
|
||||
files which
|
||||
- include the auto_path statements above
|
||||
- activate `tclreadline` (and thus in `tclshrc` an event loop)
|
||||
@ -249,7 +249,7 @@ with in most cases
|
||||
|
||||
### <a id="bitkits">Available bitkits with bit and log files</a>
|
||||
|
||||
Tarballs with ready to use bit files and all logfiles from the tool
|
||||
Tarballs with ready-to-use bit files and all logfiles from the tool
|
||||
chain can be downloaded from
|
||||
http://www.retro11.de/data/oc_w11/bitkits/ .
|
||||
|
||||
|
||||
@ -1,50 +1,28 @@
|
||||
# Installation of ghdl
|
||||
# Installation of GHDL
|
||||
|
||||
The w11 project uses the open source VHDL simulator **ghdl**.
|
||||
The w11 project uses the open source VHDL simulator **GHDL**.
|
||||
|
||||
It used to be part of most distributions. Unfortunately the Debian maintainer
|
||||
for ghdl refused at some point to integrate ghdl into Debian Etch. Therefore
|
||||
ghdl was part of Debian 5 "Lenny", and again of Debian 6 "Squeeze", and is
|
||||
missing again in Debian 7 "Wheezy" (the current 'stable').
|
||||
for GHDL refused at some point to integrate GHDL into Debian 4 "Etch".
|
||||
GHDL was part of Debian 5 "Lenny", and again of Debian 6 "Squeeze", and was
|
||||
missing again in Debian 7 "Wheezy", Debian 8 "Jessy", and Debian 9 "Stretch".
|
||||
It was finally re-integrated in Debian 10 "Buster" (with V0.35) and
|
||||
Debian 11 "Bullseye" (with V1.0.0).
|
||||
|
||||
The glitch at Debian unfortunately lead to the removal of ghdl from Ubuntu,
|
||||
The glitch at Debian unfortunately lead to the removal of GHDL from Ubuntu,
|
||||
which is based on Debian. Ubuntu 10.04 "Lucid" up to 11.10 "Oneiric" included
|
||||
ghdl, the currently maintained versions 12.04 LTS "Precise", 14.04 LTS "Trusty"
|
||||
and 14.10 "Utopic" unfortunately don't.
|
||||
GHDL, while 12.04 LTS "Precise", 14.04 LTS "Trusty", 16.04 LTS "Xenial",
|
||||
and 18.04 "Bionic" didn't. It was finally re-integrated in Ubuntu in
|
||||
20.04 LTS "Focal" (with V0.37) and 22.04 LTS "Jammy" (with V1.0.0).
|
||||
|
||||
To install ghdl on an up-to-date Debian or Ubuntu systems you have the
|
||||
following options _(as of early February 2015)_:
|
||||
However, the recent Debian packages do not include the `VITAL` libraries anymore,
|
||||
see [issue 1939910](https://bugs.launchpad.net/ubuntu/+source/ghdl/+bug/1939910)
|
||||
and [comment 899552686](https://github.com/ghdl/ghdl/pull/1841#issuecomment-899552686)
|
||||
The response was that they were removed due to license issues, see
|
||||
[comment 899576418](https://github.com/ghdl/ghdl/pull/1841#issuecomment-899576418). The recent Ubuntu packages also do not include the `VITAL` libraries.
|
||||
|
||||
- Ubuntu Precise and Trusty
|
||||
The Debian/Ubuntu packages are therefore useless for w11 verification.
|
||||
|
||||
Thanks to Peter Gavin Ubuntu packages for GHDL are available from his PPA
|
||||
'Personal Package Archives', see
|
||||
|
||||
https://launchpad.net/~pgavin/+archive/ghdl
|
||||
|
||||
So to install ghdl under Ubuntu use
|
||||
|
||||
sudo add-apt-repository ppa:pgavin/ghdl
|
||||
sudo apt-get update
|
||||
sudo apt-get install ghdl
|
||||
|
||||
- Debian Wheezy
|
||||
|
||||
Thanks to Joris van Rantwijk Debian packages for GHDL are available
|
||||
from the web site
|
||||
|
||||
http://jorisvr.nl/ghdl_debian.html
|
||||
|
||||
There are also Ubuntu packages, but Joris focus is clearly on Debian.
|
||||
|
||||
Only Debian and Ubuntu are actively used by the w11a developer. The situation
|
||||
for other Linux distributions is therefore just taken from the respective web
|
||||
sites _(status October 2013)_:
|
||||
|
||||
- **Suse**
|
||||
For Suse 12.2 and 12.3 un-official ghdl packages are available, but they
|
||||
seem to be based on the long obsolete ghdl version 0.27.
|
||||
- **Redhat/Fedora**
|
||||
For Fedora 18,19, and 20 packages are available based on ghdl 0.29
|
||||
- **Gentoo**
|
||||
Packages, marked 'unstable', are available based on ghdl 0.29 and 0.27
|
||||
The only solution is to install GHDL from sources.
|
||||
That had been a bit quirky at times, but since V0.37 it works without
|
||||
any problems.
|
||||
|
||||
@ -73,7 +73,7 @@ with the currently supported combinations
|
||||
nexys4 n4 3840 kB Digilent Nexys4 board (cellular RAM)
|
||||
nexys4d n4d 3840 kB Digilent Nexys A7-100 board (DDR2)
|
||||
|
||||
The FPGA is configured via the vivado hardware server with
|
||||
The FPGA is configured via the Vivado hardware server with
|
||||
|
||||
make sys_w11a_<btype>.vconfig
|
||||
|
||||
@ -81,7 +81,7 @@ The FPGA is configured via the vivado hardware server with
|
||||
|
||||
A variety of _oskits_ is provided under [tools/oskit](../tools/oskit).
|
||||
The quick start guide describes only how to boot plain 2.11BSD. The
|
||||
full featured [211bsd_rp](../tools/oskit/211bsd_rp/README.md) can be
|
||||
full-featured [211bsd_rp](../tools/oskit/211bsd_rp/README.md) can be
|
||||
used when more than 1024 kB memory is available, for systems with 512 to
|
||||
1024 kB memory use the pruned down
|
||||
[211bsd_rpmin](../tools/oskit/211bsd_rpmin/README.md).
|
||||
|
||||
@ -5,9 +5,9 @@
|
||||
- [Concept](#user-content-concept)
|
||||
- [Setup system environment](#user-content-sysenv)
|
||||
- [Setup environment variables](#user-content-envvar)
|
||||
- [Compile UNISIM/UNIMACRO/SIMPRIM libraries for ghdl](#user-content-ghdllibs)
|
||||
- [Compile UNISIM/UNIMACRO/SIMPRIM libraries for GHDL](#user-content-ghdllibs)
|
||||
- [Building test benches](#user-content-buildtb)
|
||||
- [With ghdl](#user-content-buildtb-ghdl)
|
||||
- [With GHDL](#user-content-buildtb-ghdl)
|
||||
- [With ISE ISim](#user-content-buildtb-isim)
|
||||
- [Building FPGA bit files](#user-content-buildfpga)
|
||||
- [Configuring FPGAs (via make flow)](#user-content-config-make)
|
||||
@ -16,9 +16,9 @@
|
||||
|
||||
### <a id="concept">Concept</a>
|
||||
|
||||
This projects uses GNU make to
|
||||
This project uses GNU make to
|
||||
- generate bit files (synthesis with xst and place&route with par)
|
||||
- generate test benches (with ghdl or Xilinx ISim)
|
||||
- generate test benches (with GHDL or Xilinx ISim)
|
||||
- configure the FPGA (with Xilinx Impact or Linux jtag)
|
||||
|
||||
The Makefile's in general contain only a few definitions, all the make logic
|
||||
@ -32,18 +32,18 @@ The build system employed in this project is based on manifest files called
|
||||
|
||||
'vbom' or "VHDL bill of material" files
|
||||
|
||||
which list for each vhdl source file the libraries and sources for the
|
||||
instantiated components, the later via their vbom, and last but not least
|
||||
the name of the vhdl source file.
|
||||
which list for each VHDL source file the libraries and sources for the
|
||||
instantiated components, the latter via their vbom, and last but not least
|
||||
the name of the VHDL source file.
|
||||
|
||||
All file name are relative to the current directory. A recursive traversal
|
||||
All file names are relative to the current directory. A recursive traversal
|
||||
through all vbom's gives for each vhld module all sources needed to compile
|
||||
it. The vbomconv script in tools/bin does this, and generates depending on
|
||||
it. The vbomconv script in tools/bin does this and generates depending on
|
||||
options
|
||||
- make dependency files
|
||||
- ISE xst project files (synthesis)
|
||||
- ISE ISim project files (simulation)
|
||||
- ghdl commands for analysis, inspection and make step
|
||||
- GHDL commands for analysis, inspection and make step
|
||||
|
||||
The master make files contain pattern rules like
|
||||
|
||||
@ -52,7 +52,7 @@ The master make files contain pattern rules like
|
||||
|
||||
which encapsulate all the vbomconv magic
|
||||
|
||||
A full w11a system is build from about 100 source files, test benches
|
||||
A full w11a system is built from about 100 source files, test benches
|
||||
from even more. Using the vbom's a large number of designs can be easily
|
||||
maintained.
|
||||
|
||||
@ -73,15 +73,15 @@ For details on `RETRO_FX2_VID` and `RETRO_FX2_PID` see
|
||||
|
||||
Notes:
|
||||
- The build system uses a small wrapper script called `xtwi` to encapsulate
|
||||
the Xilinx environment. It uses `XTWI_PATH` to setup the ISE environment on
|
||||
the Xilinx environment. It uses `XTWI_PATH` to set up the ISE environment on
|
||||
the fly. For details consult 'man xtwi'.
|
||||
- don't run the ISE setup scripts ..../settings(32|64).sh in your working
|
||||
shell. Setup only `XTWI_PATH` !
|
||||
|
||||
#### <a id="ghdllibs">Compile UNISIM/UNIMACRO/SIMPRIM libraries for ghdl</a>
|
||||
#### <a id="ghdllibs">Compile UNISIM/UNIMACRO/SIMPRIM libraries for GHDL</a>
|
||||
|
||||
A few entities use `UNISIM` or `UNIMACRO` primitives, and models derived after
|
||||
the par step require also `SIMPRIM` primitives. In these cases ghdl has to
|
||||
the par step require also `SIMPRIM` primitives. In these cases, GHDL has to
|
||||
link against a compiled `UNISIM`, `UNIMACRO` or `SIMPRIM` libraries.
|
||||
|
||||
To make handling of the parallel installation of several ISE versions
|
||||
@ -102,17 +102,17 @@ Run these scripts for each ISE version which is installed.
|
||||
### <a id="buildtb">Building test benches</a>
|
||||
|
||||
The build flows support two simulators
|
||||
- ghdl -> open source, with VHPI support, doesn't accept sdf files
|
||||
- GHDL -> open source, with VHPI support, doesn't accept sdf files
|
||||
- ISE ISim -> limited to 50k lines in WebPack, no VHPI support
|
||||
|
||||
#### <a id="buildtb-ghdl">With ghdl</a>
|
||||
#### <a id="buildtb-ghdl">With GHDL</a>
|
||||
|
||||
To compile a ghdl based test bench named `<tbench>` all is needed is
|
||||
To compile a GHDL based test bench named `<tbench>` all is needed is
|
||||
|
||||
make <tbench>
|
||||
|
||||
The make file will use `<tbench>.vbom`, create all make dependency files,
|
||||
and generate the needed ghdl commands.
|
||||
and generate the needed GHDL commands.
|
||||
|
||||
In many cases the test benches can also be compiled against the gate
|
||||
level models derived after the `xst`, `map` or `par` step. To compile them
|
||||
@ -128,12 +128,12 @@ Individual working directories are used for the different models
|
||||
ghdl.fsim for post-map
|
||||
ghdl.tsim for post-par
|
||||
|
||||
and can co-exist. The `make ghdl_tmp_clean` can be used to flush the ghdl
|
||||
and can co-exist. The `make ghdl_tmp_clean` can be used to flush the GHDL
|
||||
work areas, but in general this is not needed (since V0.73).
|
||||
|
||||
Notes:
|
||||
- the post-xst simulation (_ssim targets) proved to be a valuable tool.
|
||||
- ghdl fails to read sdf files generated by Xilinx tools, and thus does
|
||||
- GHDL fails to read sdf files generated by Xilinx tools, and thus does
|
||||
not support a post-par simulation with full timing.
|
||||
- post-par simulations without timing annotation often fail, most likely
|
||||
due to clocking and delta cycle issues due to inserted clock buffers.
|
||||
@ -163,7 +163,7 @@ Notes:
|
||||
simulation engine throttles to snails speed.
|
||||
- ISim does not support VHPI (interfacing of external C routines to VHDL).
|
||||
Since VHPI is used in the rlink simulation all system test benches with
|
||||
an rlink interface, thus most, will only run with ghdl and not with ISim.
|
||||
an rlink interface, thus most, will only run with GHDL and not with ISim.
|
||||
|
||||
### <a id="buildfpga">Building FPGA bit files</a>
|
||||
|
||||
@ -235,7 +235,7 @@ the FPGA. For detailed documentation see the respective man pages.
|
||||
|
||||
### <a id="artix">Note on Artix-7 based designs</a>
|
||||
|
||||
The development for Nexys4 started with ISE, but has now fully moved to
|
||||
The development for Nexys4 started with ISE but has now fully moved to
|
||||
Vivado. The make files for the ISE build flows have been kept for comparison
|
||||
are have the name `Makefile.ise`. So for some Nexys4 designs and associated
|
||||
one can still start with a
|
||||
|
||||
@ -5,9 +5,9 @@
|
||||
- [Concept](#user-content-concept)
|
||||
- [Setup system environment](#user-content-sysenv)
|
||||
- [Setup environment variables](#user-content-envvar)
|
||||
- [Compile UNISIM/UNIMACRO libraries for ghdl](#user-content-ghdllibs)
|
||||
- [Compile UNISIM/UNIMACRO libraries for GHDL](#user-content-ghdllibs)
|
||||
- [Building test benches](#user-content-buildtb)
|
||||
- [With ghdl](#user-content-buildtb-ghdl)
|
||||
- [With GHDL](#user-content-buildtb-ghdl)
|
||||
- [With Vivado xsim](#user-content-buildtb-xsim)
|
||||
- [Building FPGA bit files](#user-content-buildfpga)
|
||||
- [Building vivado projects, creating models](#user-content-buildviv)
|
||||
@ -16,9 +16,9 @@
|
||||
|
||||
### <a id="concept">Concept</a>
|
||||
|
||||
This projects uses GNU `make` to
|
||||
This project uses GNU `make` to
|
||||
- generate bit files (with Vivado synthesis)
|
||||
- generate test benches (with ghdl or Vivado XSim)
|
||||
- generate test benches (with GHDL or Vivado XSim)
|
||||
- configure the FPGA (with Vivado hardware server)
|
||||
|
||||
The Makefile's in general contain only a few definitions. By far most of
|
||||
@ -34,18 +34,18 @@ The build system employed in this project is based on manifest files called
|
||||
|
||||
'vbom' or "VHDL bill of material" files
|
||||
|
||||
which list for each vhdl source file the libraries and sources for the
|
||||
instantiated components, the later via their vbom, and last but not least
|
||||
the name of the vhdl source file.
|
||||
which list for each VHDL source file the libraries and sources for the
|
||||
instantiated components, the latter via their vbom, and last but not least
|
||||
the name of the VHDL source file.
|
||||
|
||||
All file name are relative to the current directory. A recursive traversal
|
||||
All file names are relative to the current directory. A recursive traversal
|
||||
through all vbom's gives for each vhld module all sources needed to compile
|
||||
it. The `vbomconv` script in `tools/bin` does this, and generates depending on
|
||||
it. The `vbomconv` script in `tools/bin` does this and generates depending on
|
||||
options
|
||||
- make dependency files
|
||||
- Vivado synthesis setup files
|
||||
- Vivado simulation setup files
|
||||
- ghdl commands for analysis, inspection and make step
|
||||
- GHDL commands for analysis, inspection and make step
|
||||
|
||||
The master make files contain pattern rules like
|
||||
|
||||
@ -54,7 +54,7 @@ The master make files contain pattern rules like
|
||||
|
||||
which encapsulate all the `vbomconv` magic
|
||||
|
||||
A full w11a system is build from about 100 source files, test benches
|
||||
A full w11a system is built from about 100 source files, test benches
|
||||
from even more. Using the vbom's a large number of designs can be easily
|
||||
maintained.
|
||||
|
||||
@ -68,22 +68,22 @@ The build flows require the environment variables:
|
||||
- `RETROBASE`: must refer to the installation root directory
|
||||
- `XTWV_PATH`: install path of the Vivado version
|
||||
|
||||
For general instructions on environment see [INSTALL.md](INSTALL.md).
|
||||
For general instructions on the environment see [INSTALL.md](INSTALL.md).
|
||||
|
||||
Notes:
|
||||
- The build system uses a small wrapper script called xtwv to encapsulate
|
||||
the Xilinx environment. It uses `XTWV_PATH` to setup the Vivado environment
|
||||
the Xilinx environment. It uses `XTWV_PATH` to set up the Vivado environment
|
||||
on the fly. For details consult 'man xtwv'.
|
||||
- don't run the Vivado setup scripts ..../settings(32|64).sh in your working
|
||||
shell. Setup only XTWV_PATH !
|
||||
|
||||
#### <a id="ghdllibs">Compile UNISIM/UNIMACRO libraries for ghdl</a>
|
||||
#### <a id="ghdllibs">Compile UNISIM/UNIMACRO libraries for GHDL</a>
|
||||
|
||||
A few entities use `UNISIM` or `UNIMACRO` primitives, and post synthesis models
|
||||
require also `UNISIM` primitives. In these cases ghdl has to link against a
|
||||
A few entities use `UNISIM` or `UNIMACRO` primitives, and post-synthesis models
|
||||
require also `UNISIM` primitives. In these cases, GHDL has to link against a
|
||||
compiled `UNISIM` or `UNIMACRO` libraries.
|
||||
|
||||
To make handling of the parallel installation of several Vivado versions
|
||||
To make the handling of the parallel installation of several Vivado versions
|
||||
easy the compiled libraries are stored in sub-directories under `$XTWV_PATH`:
|
||||
|
||||
$XTWV_PATH/ghdl/unisim
|
||||
@ -94,33 +94,33 @@ A helper scripts will create these libraries:
|
||||
cd $RETROBASE
|
||||
xviv_ghdl_unisim # does UNISIM and UNIMACRO
|
||||
|
||||
Run these scripts for each Vivado version which is installed.
|
||||
Run these scripts for each Vivado version that is installed.
|
||||
|
||||
Notes:
|
||||
- Vivado supports `SIMPRIM` libraries only in Verilog form, there is no vhdl
|
||||
- Vivado supports `SIMPRIM` libraries only in Verilog form, there is no VHDL
|
||||
version anymore.
|
||||
- ghdl can therefore not be used to do timing simulations with Vivado.
|
||||
However: under ISE `SIMPRIM` was available in vhdl, but ghdl did never
|
||||
accept the sdf files, making ghdl timing simulations impossible under ISE too.
|
||||
- GHDL can therefore not be used to do timing simulations with Vivado.
|
||||
However: under ISE `SIMPRIM` was available in VHDL, but GHDL did never
|
||||
accept the sdf files, making GHDL timing simulations impossible under ISE too.
|
||||
|
||||
### <a id="buildtb">Building test benches</a>
|
||||
|
||||
The build flows currently supports ghdl and the vivado simulator xsim.
|
||||
The build flows currently supports GHDL and the Vivado simulator xsim.
|
||||
|
||||
#### <a id="buildtb-ghdl">With ghdl</a>
|
||||
#### <a id="buildtb-ghdl">With GHDL</a>
|
||||
|
||||
To compile a ghdl based test bench named `<tbench>` all is needed is
|
||||
To compile a GHDL based test bench named `<tbench>` all is needed is
|
||||
|
||||
make <tbench>
|
||||
|
||||
The make file will use `<tbench>.vbom`, create all make dependency files,
|
||||
and generate the needed ghdl commands.
|
||||
and generate the needed GHDL commands.
|
||||
|
||||
In some cases the test benches can also be compiled against the gate
|
||||
In some cases, the test benches can also be compiled against the gate
|
||||
level models derived after the synthesis or optimize step.
|
||||
Vivado only generated functional (`UNISIM` based) models in vhdl. Timing
|
||||
(`SIMPRIM` based) models are only available on verilog. The combination
|
||||
vivado + ghdl is therefore limited to functional model simulation.
|
||||
Vivado only generated functional (`UNISIM` based) models in VHDL. Timing
|
||||
(`SIMPRIM` based) models are only available on Verilog. The combination
|
||||
Vivado + GHDL is therefore limited to functional model simulation.
|
||||
|
||||
To compile them
|
||||
|
||||
@ -136,7 +136,7 @@ Individual working directories are used for the different models
|
||||
ghdl.osim for post optimize
|
||||
ghdl.rsim for post routing
|
||||
|
||||
and can co-exist. The `make ghdl_tmp_clean` can be used to flush the ghdl
|
||||
and can co-exist. The `make ghdl_tmp_clean` can be used to flush the GHDL
|
||||
work areas, but in general this is not needed (since V0.73).
|
||||
|
||||
Notes:
|
||||
@ -153,11 +153,11 @@ To compile a Vivado xsim based test bench named <tbench> all is needed is
|
||||
The make file will use `<tbench>.vbom`, create all make dependency files,
|
||||
and generate the needed Vivado xsim project files and commands.
|
||||
|
||||
In many cases the test benches can also be compiled against the gate
|
||||
In many cases, the test benches can also be compiled against the gate
|
||||
level models derived after the synthesis, optimize or routing step.
|
||||
Vivado supports functional (`UNISIM` based) models in vhdl and in verilog,
|
||||
and timing (`SIMPRIM` based) models only in verilog. Since practice showed
|
||||
that verilog models compile and execute faster, verilog is used for both
|
||||
Vivado supports functional (`UNISIM` based) models in VHDL and in Verilog,
|
||||
and timing (`SIMPRIM` based) models only in Verilog. Since practice showed
|
||||
that Verilog models compile and execute faster, Verilog is used for both
|
||||
functional and timing models.
|
||||
|
||||
make <tbench>_XSim_ssim # for post-synthesis functional
|
||||
@ -169,8 +169,8 @@ functional and timing models.
|
||||
make <tbench>_XSim_tsim # for post-routing timing
|
||||
|
||||
Notes:
|
||||
- as of vivado 2016.2 `xelab` shows sometimes extremely long build times,
|
||||
especially for generated post-synthesis vhdl models
|
||||
- as of Vivado 2016.2 `xelab` shows sometimes extremely long build times,
|
||||
especially for generated post-synthesis VHDL models
|
||||
(see [issue #9](https://github.com/wfjm/w11/issues/9)).
|
||||
- Many post-synthesis functional and especially post-routing timing
|
||||
simulations currently fail due to startup and initialization problems
|
||||
@ -218,10 +218,10 @@ If only the post synthesis, optimize or route design checkpoints are wanted
|
||||
make <sys>_opt.dcp
|
||||
make <sys>_rou.dcp
|
||||
|
||||
### <a id="buildviv">Building vivado projects, creating gate level models</a>
|
||||
### <a id="buildviv">Building Vivado projects, creating gate level models</a>
|
||||
|
||||
Vivado is used in 'project mode', whenever one of the targets mentioned
|
||||
above is build a vivado project is freshly created in the directory
|
||||
above is build a Vivado project is freshly created in the directory
|
||||
|
||||
project_mflow
|
||||
|
||||
@ -231,27 +231,27 @@ with the project file
|
||||
|
||||
There are many make targets which
|
||||
- just create the project
|
||||
- start vivado in gui mode to inspect the most recent project
|
||||
- start Vivado in gui mode to inspect the most recent project
|
||||
- create gate level models
|
||||
|
||||
Specifically
|
||||
|
||||
make <sys>.vivado # create vivado project from <sys>.vbom
|
||||
make <sys>.vivado # create Vivado project from <sys>.vbom
|
||||
make vivado # open project in project_mflow
|
||||
|
||||
make <sys>_ssim.vhd # post-synthesis functional model (vhdl)
|
||||
make <sys>_osim.vhd # post-optimize functional model (vhdl)
|
||||
make <sys>_rsim.vhd # post-routing functional model (vhdl)
|
||||
make <sys>_ssim.vhd # post-synthesis functional model (VHDL)
|
||||
make <sys>_osim.vhd # post-optimize functional model (VHDL)
|
||||
make <sys>_rsim.vhd # post-routing functional model (VHDL)
|
||||
|
||||
make <sys>_ssim.v # post-synthesis functional model (verilog)
|
||||
make <sys>_osim.v # post-optimize functional model (verilog)
|
||||
make <sys>_rsim.v # post-routing functional model (verilog)
|
||||
make <sys>_ssim.v # post-synthesis functional model (Verilog)
|
||||
make <sys>_osim.v # post-optimize functional model (Verilog)
|
||||
make <sys>_rsim.v # post-routing functional model (Verilog)
|
||||
|
||||
make <sys>_esim.v # post-synthesis timing model (verilog)
|
||||
make <sys>_psim.v # post-optimize timing model (verilog)
|
||||
make <sys>_tsim.v # post-routing timing model (verilog)
|
||||
make <sys>_esim.v # post-synthesis timing model (Verilog)
|
||||
make <sys>_psim.v # post-optimize timing model (Verilog)
|
||||
make <sys>_tsim.v # post-routing timing model (Verilog)
|
||||
|
||||
For timing model verilog file an associated sdf file is also generated.
|
||||
For timing model Verilog file an associated sdf file is also generated.
|
||||
|
||||
### <a id="config-fpga">Configuring FPGAs</a>
|
||||
|
||||
@ -265,7 +265,7 @@ only one board must connected.
|
||||
|
||||
### <a id="ise">Note on ISE</a>
|
||||
|
||||
The development for Nexys4 started with ISE, but has now fully moved to
|
||||
The development for Nexys4 started with ISE but has now fully moved to
|
||||
Vivado. The make files for the ISE build flows have been kept for comparison
|
||||
are have the name `Makefile.ise`. So for some Nexys4 designs and associated
|
||||
one can still start with a
|
||||
|
||||
@ -2,6 +2,11 @@
|
||||
|
||||
The case id indicates the release when the issue was first recognized.
|
||||
|
||||
### V0.79 {[issue #29](https://github.com/wfjm/w11/issues/29)} -- migrate from Travis to GitHub actions
|
||||
|
||||
Travis is now defunct and has been removed in [6b8c063](https://github.com/wfjm/w11/commit/6b8c063).
|
||||
So it's time to migrate CI/CD to GitHub actions.
|
||||
|
||||
### V0.50-2 {[issue #28](https://github.com/wfjm/w11/issues/28)} -- RK11: write protect action too slow
|
||||
|
||||
Some simple RK11 drivers, especially in test codes, don't poll for completion
|
||||
@ -154,17 +159,6 @@ that 2018.3 is less tolerant to the sub-optimal w11a design.
|
||||
This will be fixed in a future release, either by setting up an appropriate
|
||||
false_path constraint, or by changing the data path structure.
|
||||
|
||||
### V0.76-2 {[issue #17](https://github.com/wfjm/w11/issues/17)} -- Help wanted: Testing with Arty S7 appreciated
|
||||
The w11a design for Arty S7 (50 die size), see rtl/sys_gen/w11a/artys7,
|
||||
was provided to support also an up-to-date Spartan-7 based board. Turned
|
||||
out that speed is equivalent to Artix-7. It is so far only simulation tested.
|
||||
|
||||
Testing done with a real Arty S7, would be highly appreciated. Please double
|
||||
check the pin assignments (see _mig_a.prj and artys7*.xdc_) with the
|
||||
documentation of your board to avoid potential damage.
|
||||
|
||||
Looking forward to receive test reports.
|
||||
|
||||
### V0.73-2 {[issue #10](https://github.com/wfjm/w11/issues/10)} -- Many post-synthesis simulations fail
|
||||
Many post-synthesis functional and especially post-routing timing
|
||||
simulations currently fail due to startup and initialization problems.
|
||||
@ -172,10 +166,10 @@ Cause is MMCM/PLL startup, which is not properly reflected in the test
|
||||
bench. Will be resolved in an upcoming release.
|
||||
|
||||
### V0.73-1 {[issue #9](https://github.com/wfjm/w11/issues/9)} -- Vivado xelab sometimes extremely slow
|
||||
as of vivado 2016.2 `xelab` shows sometimes extremely long build times,
|
||||
especially for generated post-synthesis vhdl models. But also building a
|
||||
as of Vivado 2016.2 `xelab` shows sometimes extremely long build times,
|
||||
especially for generated post-synthesis VHDL models. But also building a
|
||||
behavioral simulation for a w11a design can take 25 min. Even though
|
||||
post-synthesis or post-routing models are now generated in verilog working
|
||||
post-synthesis or post-routing models are now generated in Verilog working
|
||||
with `xsim` is cumbersome and time consuming.
|
||||
|
||||
### V0.65-2 {[issue #7](https://github.com/wfjm/w11/issues/7)} -- Some exotic RH70/RP/RM features not implemented
|
||||
@ -341,7 +335,7 @@ Fixed with commit [6024dce](https://github.com/wfjm/w11/commit/6024dce).
|
||||
|
||||
### V0.73-3 {[issue #11](https://github.com/wfjm/w11/issues/11)} -- dmscnt and dmcmon disabled in Vivado based flows
|
||||
#### Original Issue
|
||||
The 'state number generator' code in `pdp11_sequencer` causes in vivado
|
||||
The 'state number generator' code in `pdp11_sequencer` causes in Vivado
|
||||
2016.1 (and .2) that the main FSM isn't re-coded anymore, which has high
|
||||
impact on achievable clock rate. The two optional debug units depending on
|
||||
the state number, `dmscnt` and `dmcmon`, are therefore currently deactivated in
|
||||
@ -350,4 +344,23 @@ all Artix based systems (but are available on all Spartan based systems).
|
||||
At least mitigated with [d14626c](https://github.com/wfjm/w11/commit/d14626c)
|
||||
which allows to use `dmcmon` without the full state number generation logic
|
||||
in `pdp11_sequencer`. Reintroduced `dmcmon` in `sys_w11a_n4` again. `dmscnt` is
|
||||
still deconfigured for vivado designs, but this has much less practical impact.
|
||||
still deconfigured for Vivado designs, but this has much less practical impact.
|
||||
|
||||
## Closed issues
|
||||
|
||||
### V0.76-2 {[issue #17](https://github.com/wfjm/w11/issues/17)} -- Help wanted: Testing with Arty S7 appreciated
|
||||
#### Original Issue
|
||||
The w11a design for Arty S7 (50 die size), see rtl/sys_gen/w11a/artys7,
|
||||
was provided to support also an up-to-date Spartan-7 based board. Turned
|
||||
out that speed is equivalent to Artix-7. It is so far only simulation tested.
|
||||
|
||||
Testing done with a real Arty S7, would be highly appreciated. Please double
|
||||
check the pin assignments (see _mig_a.prj and artys7*.xdc_) with the
|
||||
documentation of your board to avoid potential damage.
|
||||
|
||||
Looking forward to receive test reports.
|
||||
|
||||
#### Reason for closure
|
||||
Apparently nobody invested into an Arty S7.
|
||||
The sys_w11a_as7 will be marked untested, removed from the default build
|
||||
and test flows, but kept in the repository.
|
||||
|
||||
@ -1,6 +1,6 @@
|
||||
# Summary of known differences and limitations for w11a CPU and systems
|
||||
|
||||
This file descibes differences and limitations of the w11 CPU and systems.
|
||||
This file describes the differences and limitations of the w11 CPU and systems.
|
||||
The issues of the w11 CPU and systems are listed in a separate document
|
||||
[README_known_issues.md](README_known_issues.md).
|
||||
|
||||
@ -22,11 +22,11 @@ The issues of the w11 CPU and systems are listed in a separate document
|
||||
- https://minnie.tuhs.org/pipermail/tuhs/2006-October/002695.html
|
||||
- https://minnie.tuhs.org/pipermail/tuhs/2006-October/002702.html
|
||||
|
||||
In the w11a the `SPL` has 11/70 semantics in kernel mode, thus next no
|
||||
In the w11a the `SPL` has 11/70 semantics in kernel mode, thus no
|
||||
traps or interrupts, but in supervisor and user mode `SPL` really acts as
|
||||
`NOOP`, so traps and interrupts are taken as for all other instructions.
|
||||
**--> The w11a isn't bug compatible with the 11/70.**
|
||||
- A 'red stack violation' looses PSW, a 0 is pushed in stack.
|
||||
- A 'red stack violation' loses PSW, a 0 is pushed onto the stack.
|
||||
- The 'instruction complete flag' in `SSR0` is not implemented, it is
|
||||
permanently '0', `SSR2` will not record vector addresses in case of a
|
||||
vector fetch fault. Recovery of vector fetch faults is therefore not
|
||||
@ -36,9 +36,9 @@ The issues of the w11 CPU and systems are listed in a separate document
|
||||
the 22bit extended mode address space. With UNIBUS mapping enabled, this
|
||||
allowed to access via 17000000:17757777 the memory exactly as a UNIBUS
|
||||
device would see it. The w11a doesn't implement this remapping, an access
|
||||
in the range 17000000:17757777 causes a NXM fault.
|
||||
in the range 17000000:17757777 causes an NXM fault.
|
||||
|
||||
All four points relate to very 11/70 specific behaviour, no operating system
|
||||
All four points relate to very 11/70 specific behavior, no operating system
|
||||
depends on them, therefore they are considered acceptable implementation
|
||||
differences.
|
||||
|
||||
@ -50,7 +50,7 @@ differences.
|
||||
**--> a 'CPU throttle mechanism' will be added in a future version to
|
||||
circumvent this for some old test codes.**
|
||||
- the emulated I/O can lead to apparently slow device reaction times,
|
||||
especially when the server runs as normal user process. This can lead
|
||||
to timeout, again mostly in test programs.
|
||||
especially when the server runs as a normal user process. This can lead
|
||||
to a timeout, again mostly in test programs.
|
||||
**--> a 'watch dog' mechanism will be added in a future version which
|
||||
suspends the CPU when the server doesn't respond fast enough.**
|
||||
|
||||
@ -14,19 +14,19 @@
|
||||
|
||||
All UNIBUS peripherals which exchange data (currently DL11, DZ11, LP11, PC11,
|
||||
DEUNA, RK11, RL11, RPRH, and TM11) are currently emulated via a backend
|
||||
process. The communication between FPGA board and backend server can be via
|
||||
process. The communication between the FPGA board and backend server can be via
|
||||
|
||||
- Serial port
|
||||
- via an integrated USB-UART bridge
|
||||
- on Arty A7, Basys3, Cmod A7 and Nexys4 and Nexys A7 with a `FT2232HQ`,
|
||||
- on Arty A7, Basys3, Cmod A7 and Nexys4, and Nexys A7 with a `FT2232HQ`,
|
||||
allows up to 12M Baud
|
||||
- on Nexys3 with a `FT232R`, allows up to 2M Baud
|
||||
- for all FTDI USB-UART it is essential to set them to `low latency` mode.
|
||||
That was default for Linux kernels 2.6.32 to 4.4.52. Since about March
|
||||
2017 one gets kernels with 16 ms default latency again, thanks to
|
||||
That was the default for Linux kernels 2.6.32 to 4.4.52. Since about March
|
||||
2017, one gets kernels with 16 ms default latency again, thanks to
|
||||
[kernel patch 9589541](https://patchwork.kernel.org/patch/9589541/).
|
||||
**For newer systems it is essential to install a udev rule** which
|
||||
automatically sets low latency, see
|
||||
**On newer systems, it is essential to install a udev rule** which
|
||||
automatically sets low latency, see the
|
||||
[documentation in tools/sys](../tools/sys/README.md).
|
||||
- via RS232 port, as on S3board and Nexys2
|
||||
- using a serial port (/dev/ttySx) is limited to 115 kBaud on most PCs.
|
||||
@ -35,7 +35,7 @@ process. The communication between FPGA board and backend server can be via
|
||||
- Direct USB connection using a Cypress FX2 USB controller
|
||||
- is supported on the Nexys2 and Nexys3 FPGA boards
|
||||
- much faster than serial port connections (see below)
|
||||
- also allows to configure the FPGA over the same USB connection
|
||||
- also allows configuring the FPGA over the same USB connection
|
||||
|
||||
- Notes:
|
||||
- A 12M Baud connection, like on a Nexys4, gives disk access rates and
|
||||
@ -45,7 +45,7 @@ process. The communication between FPGA board and backend server can be via
|
||||
is actually smaller than the bare numbers suggest.
|
||||
- A 460k Baud connection gives in practice a disk throughput of ~20 kB/s.
|
||||
This allows to test the system but is a bit slow for real usage.
|
||||
- USB-RS232 cables with a FTDI `FT232R` chip work fine, tests with Prolific
|
||||
- USB-RS232 cables with an FTDI `FT232R` chip work fine, tests with Prolific
|
||||
Technology `PL2303` based cable never gave reliable connections for higher
|
||||
Baud rates.
|
||||
|
||||
@ -70,22 +70,22 @@ Recommended setups
|
||||
- [Arty A7](https://wfjm.github.io/home/w11/inst/boards.html#digi_arty) or
|
||||
[Arty S7](https://wfjm.github.io/home/w11/inst/boards.html#digi_artys7)
|
||||
- connect USB cable to micro-USB connector labeled 'J10'
|
||||
- to configure via vivado hardware server `make <sys>.vconfig`
|
||||
- to configure via Vivado hardware server `make <sys>.vconfig`
|
||||
|
||||
- [Basys3](https://wfjm.github.io/home/w11/inst/boards.html#digi_basys3)
|
||||
- connect USB cable to micro-USB connector labeled 'PROG'
|
||||
- to configure via vivado hardware server `make <sys>.vconfig`
|
||||
- to configure via ivado hardware server `make <sys>.vconfig`
|
||||
|
||||
- [Cmod A7](https://wfjm.github.io/home/w11/inst/boards.html#digi_cmoda7)
|
||||
- connect USB cable to micro-USB connector
|
||||
- to configure via vivado hardware server `make <sys>.vconfig`
|
||||
- to configure via Vivado hardware server `make <sys>.vconfig`
|
||||
|
||||
- [Nexys4](https://wfjm.github.io/home/w11/inst/boards.html#digi_nexys4)
|
||||
and [Nexys A7](https://wfjm.github.io/home/w11/inst/boards.html#digi_nexysa7)
|
||||
(or
|
||||
[Nexys4 DDR](https://wfjm.github.io/home/w11/inst/boards.html#digi_nexys4d))
|
||||
- connect USB cable to micro-USB connector labeled 'PROG'
|
||||
- to configure via vivado hardware server `make <sys>.vconfig`
|
||||
- to configure via Vivado hardware server `make <sys>.vconfig`
|
||||
|
||||
- [Nexys3](https://wfjm.github.io/home/w11/inst/boards.html#digi_nexys3)
|
||||
- use Cypress FX for configure and and rlink communication
|
||||
@ -161,11 +161,11 @@ All examples below use the same basic setup
|
||||
Notes:
|
||||
- the letter after `-tu` is either the serial device number,
|
||||
denoted as `<dn>`, or the letter `D` for auto-detection of
|
||||
Digilent boards with a FT2232HQ based interface.
|
||||
Digilent boards with an FT2232HQ based interface.
|
||||
- for Arty A7, Basys3, Cmod A7, Nexys4, and Nexys A7 board simply use `D`
|
||||
- otherwise check with `ls /dev/ttyUSB*` to see what is available
|
||||
- `<dn>` is typically '1' if a single `FT2232HQ` based board is connected,
|
||||
like an Arty, Basys3, Cmod A7, or Nexys4. Initially two ttyUSB devices
|
||||
like an Arty, Basys3, Cmod A7, or Nexys4. Initially, two ttyUSB devices
|
||||
show up, the lower is for FPGA configuration and will disappear when
|
||||
the Vivado hardware server is used once. The upper provides the data
|
||||
connection.
|
||||
@ -198,12 +198,12 @@ All examples below use the same basic setup
|
||||
### <a id="simh">simh simulator setup</a>
|
||||
|
||||
Sometimes it is good to compare the w11a behavior with the PDP-11 software
|
||||
emulator from the simh project (see http://simh.trailing-edge.com/).
|
||||
emulator from the simh project (see https://github.com/simh/simh).
|
||||
|
||||
Under `$RETROBASE/tools/simh` two setup files are provided with configure
|
||||
Under `$RETROBASE/tools/simh` two setup files are provided which configure
|
||||
simh to reflect the w11a setup as close as possible:
|
||||
- `setup_w11a_min.scmd`
|
||||
Very close the current w11a state when it runs on an s3board
|
||||
Very close to the current w11a state when it runs on an s3board
|
||||
- processor: 11/70, no FPP, 1 Mbyte
|
||||
- periphery: 2 DL11, LP11, RK11, PC11
|
||||
- `setup_w11a_max.scmd`
|
||||
@ -216,9 +216,10 @@ configuration, so will show in the emulator what w11a can do when
|
||||
finished.
|
||||
|
||||
All examples below use the same basic setup
|
||||
- setup vt100 emulator window for 2nd DL11
|
||||
- setup vt100 emulator window for 1st and 2nd DL11
|
||||
|
||||
cd $RETROBASE/tools/oskit/<oskit-name>
|
||||
console_starter -s -d DL0 &
|
||||
console_starter -s -d DL1 &
|
||||
|
||||
**Note**: the -s ensures that the port numbers used by simh are taken!
|
||||
@ -267,9 +268,9 @@ For further details consult the `README.md` file in the oskit directory.
|
||||
|
||||
#### Legal and license issues
|
||||
|
||||
Unfortunately there is no general hobbyist license for DEC operating
|
||||
Unfortunately, there is no general hobbyist license for DEC operating
|
||||
systems for PDP-11 computers. The 'Mentec license' is commonly understood
|
||||
to cover the some older versions of DEC operating systems, for example
|
||||
to cover some older versions of DEC operating systems, for example
|
||||
|
||||
- RT-11 V5.3 or prior
|
||||
- RSX-11M V4.3 or prior
|
||||
|
||||
@ -11,27 +11,27 @@
|
||||
- [Available system test benches](#user-content-list-tb-sys)
|
||||
|
||||
### General Notes
|
||||
- Ghdl is used for all behavioral simulations
|
||||
- GHDL is used for all behavioral simulations
|
||||
- Optionally Vivado xsim can be used
|
||||
- For post synthesis or post implementation functionnal simulations
|
||||
either Ghdl or Vivado xsim can be used.
|
||||
- For timing simulations only Vivado xsim can be used.
|
||||
- For post-synthesis or post-implementation functional simulations
|
||||
either GHDL or Vivado xsim can be used.
|
||||
- For timing simulations, only Vivado xsim can be used.
|
||||
- ISE isim is also available, but considered legacy support
|
||||
|
||||
### <a id="env">Tests bench environment</a>
|
||||
|
||||
All test benches have the same simple structure:
|
||||
|
||||
- the test benches are 'self-checking'. For unit tests a stimulus process
|
||||
- the test benches are 'self-checking'. For unit tests, a stimulus process
|
||||
reads test patterns as well as the expected responses from a stimulus file
|
||||
|
||||
- the responses are checked in very simple cases by the stimulus process,
|
||||
in general by a monitoring process
|
||||
|
||||
- the test bench produces a comprehensive log file. For each checked
|
||||
response the line contains the word "CHECK" and either an "OK" or a
|
||||
"FAIL", in the later case in general with an indication of whats wrong.
|
||||
Other unexpected behaviour, like timeouts, will also result in a line
|
||||
response, the line contains the word "CHECK" and either an "OK" or a
|
||||
"FAIL", in the latter case in general with an indication of what's wrong.
|
||||
Other unexpected behavior, like timeouts, will also result in a line
|
||||
containing the word "FAIL".
|
||||
|
||||
- at the end a line with the word "DONE" is printed.
|
||||
@ -50,12 +50,12 @@ All test benches have the same simple structure:
|
||||
|
||||
Building the simulation models is handled by the build environment. See
|
||||
[README_buildsystem_Vivado.md](README_buildsystem_Vivado.md) for details
|
||||
of the vivado flow and
|
||||
of the Vivado flow and
|
||||
[README_buildsystem_ISE.md](README_buildsystem_ISE.md) for the ISE flow.
|
||||
|
||||
### <a id="tb-unit">Unit test benches</a>
|
||||
|
||||
All unit test are executed via `tbw` (test bench warpper) script.
|
||||
All unit test are executed via `tbw` (test bench wrapper) script.
|
||||
|
||||
- the test bench is run like
|
||||
|
||||
@ -65,47 +65,47 @@ All unit test are executed via `tbw` (test bench warpper) script.
|
||||
- tbw sets up the environment of the test bench and starts it.
|
||||
It generates required symbolic links, e.g. to the stimulus file,
|
||||
the defaults extracted from the file tbw.dat, if an optional file
|
||||
name is give this one will be used instead.
|
||||
name is given this one will be used instead.
|
||||
- tbfilt saves the full test bench output to a logfile and filters
|
||||
the output for PASS/FAIL criteria
|
||||
|
||||
- for convenience a wrapper script `tbrun_tbw` is used to generate the
|
||||
- for convenience, a wrapper script `tbrun_tbw` is used to generate the
|
||||
tbw|tbfilt pipe. This script also checks with `make` whether the
|
||||
test bench is up-to-date or must be (re)-compiled.
|
||||
|
||||
### <a id="tb-sys">System test benches</a>
|
||||
|
||||
The system tests allow to verify to verify a full system design.
|
||||
In this case vhdl test bench code contains
|
||||
The system tests allow verification of a full system design.
|
||||
In this case, VHDL test bench code contains
|
||||
- (simple) models of the memories used on the FPGA boards
|
||||
- drivers for the rlink connection (currently just serialport)
|
||||
- drivers for the rlink connection (currently just serial port)
|
||||
- code to interface the rlink data stream to a UNIX 'named pipe',
|
||||
implemented with a C routine which is called via VHPI from VHDL.
|
||||
|
||||
This way the whole ghdl simulation can be controlled via a di-directional
|
||||
This way the whole GHDL simulation can be controlled via a bi-directional
|
||||
byte stream.
|
||||
|
||||
The rlink backend process can connect either via a named pipe to a ghdl
|
||||
simulation, or via a serial port to a FPGA board. This way the same tests
|
||||
The rlink backend process can connect either via a named pipe to a GHDL
|
||||
simulation, or via a serial port to an FPGA board. This way the same tests
|
||||
can be executed in simulation and on real hardware.
|
||||
|
||||
In general the script `tbrun_tbwrri` is used to generate the quite lengthy
|
||||
command to properly setup the tbw|tbfilt pipe. This script also checks
|
||||
In general, the script `tbrun_tbwrri` is used to generate the quite lengthy
|
||||
command to properly set up the tbw|tbfilt pipe. This script also checks
|
||||
with `make` whether the test bench is up-to-date or must be (re)-compiled.
|
||||
|
||||
### <a id="tb-driver">Test bench driver</a>
|
||||
|
||||
All available tests (unit and system test benches) are described in a
|
||||
set of descriptor files, usually called `tbrun.yml`. The top level file
|
||||
set of descriptor files, usually called `tbrun.yml`. The top-level file
|
||||
in `$RETROBASE` includes other descriptor files located in the source
|
||||
directories of the tests.
|
||||
|
||||
The script `tbrun` reads these descriptor files, selects tests based
|
||||
on `--tag` and `--exclude` options, and executes the tests with the
|
||||
simulation engine and simulation type given by the `--mode` option.
|
||||
For full description of see `man tbrun`.
|
||||
For a full description see `man tbrun`.
|
||||
|
||||
The low level drivers `tbrun_tbw` and `tbrun_tbwrri` will automatically
|
||||
The low-level drivers `tbrun_tbw` and `tbrun_tbwrri` will automatically
|
||||
build the model if it is not available or outdated. This is very convenient
|
||||
when working with a single test bench during development.
|
||||
|
||||
@ -114,21 +114,21 @@ the model building (make phase) made model execution (run phase). Both
|
||||
the low level drivers as well as `tbrun` support this via the options
|
||||
`--nomake` and `--norun`.
|
||||
|
||||
The individial test benches are simplest started via tbrun and a proper
|
||||
The individual test benches are simplest started via tbrun and a proper
|
||||
selection via `--tag`. Very helpful is
|
||||
|
||||
cd $RETROBASE
|
||||
tbrun --dry --tag=.*
|
||||
|
||||
which gives a listing of all available test. The tag list as well as
|
||||
the shell commands to execute the test are shown.
|
||||
which gives a listing of all available tests. The tag list, as well as
|
||||
the shell commands to execute the test, are shown.
|
||||
|
||||
### <a id="tb-exec">Execute all available tests</a>
|
||||
|
||||
As stated above it is in general better to to separate the model building
|
||||
As stated above it is in general better to separate the model building
|
||||
(make phase) made model execution (run phase). The currently recommended
|
||||
way to execute all test benches is given below.
|
||||
The run time is measured on a 3 GHz dual core system.
|
||||
The run time is measured on a 3 GHz dual-core system.
|
||||
|
||||
cd $RETROBASE
|
||||
# build all behavioral models
|
||||
@ -136,7 +136,7 @@ The run time is measured on a 3 GHz dual core system.
|
||||
time nice tbrun -j 2 -norun -tag=ise -tee=tbrun_make_ise_bsim.log
|
||||
# --> real 3m41.732s user 6m3.381s sys 0m24.224s
|
||||
|
||||
# than all with vivado work flow
|
||||
# than all with Vivado work flow
|
||||
time nice tbrun -j 2 -norun -tag=viv -tee=tbrun_make_viv_bsim.log
|
||||
# --> real 3m36.532s user 5m58.319s sys 0m25.235s
|
||||
|
||||
|
||||
@ -1,7 +1,8 @@
|
||||
# $Id: tbrun.yml 1107 2019-01-27 12:54:48Z mueller $
|
||||
# $Id: tbrun.yml 1224 2022-04-20 10:25:52Z mueller $
|
||||
#
|
||||
# Revision History:
|
||||
# Date Rev Version Comment
|
||||
# 2022-04-20 1224 1.3 drop artys7(dram)
|
||||
# 2019-01-27 1107 1.2 add arty(dram),nexys4d(dram),artys7(dram)
|
||||
# 2018-08-11 1038 1.1 add artys7(bram)
|
||||
# 2017-06-25 914 1.1 add cmoda7
|
||||
@ -16,6 +17,4 @@
|
||||
- include: basys3/tb/tbrun.yml
|
||||
- include: arty/tb/tbrun.yml
|
||||
- include: arty_bram/tb/tbrun.yml
|
||||
- include: artys7/tb/tbrun.yml
|
||||
- include: artys7_bram/tb/tbrun.yml
|
||||
- include: cmoda7/tb/tbrun.yml
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user