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tbit trap overhaul; fix RESET wait

Browse Source 
- rtl/w11a:
  - pdp11.vhd: add cpustat_type treq_tbit and resetcnt; use op_rti rather op_rtt
  - pdp11_decode.vhd: use op_rti rather op_rtt
  - pdp11_sequencer.vhd: tbit logic overhaul; use treq_tbit; cleanups;
                         use resetcnt for 8 cycle RESET wait
- rtl/sys_gen/w11a/s3board/sys_conf.vhd: disable monitors for timing closure
- rtl/sys_gen/w11a/*/*.vmfset: drop removed signals
- tools
  - asm-11/lib/push_pop.mac: add push2
  - tbench/w11a/test_w11a_inst_quick.tcl: use creset option to clr pending traps
  - tcl/rw11/asm.tcl: asmrun: add creset option (active with ps option)
  - tcode/cpu_basics.mac: add F2.3 (reset settling time)
  - tcode/cpu_details.mac: add A4.* (PSW + tbit traps)
This commit is contained in:
wfjm
2022-12-07 15:48:48 +01:00
parent 93307c746d
commit 44c96ec4ab
27 changed files with 784 additions and 133 deletions
Download Patch File Download Diff File Expand all files Collapse all files

3
rtl/sys_gen/w11a/arty/sys_w11a_arty.vhd
View File

@@ -1,4 +1,4 @@
-- $Id: sys_w11a_arty.vhd 1247 2022-07-06 07:04:33Z mueller $
-- $Id: sys_w11a_arty.vhd 1325 2022-12-07 11:52:36Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2018-2022 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@@ -29,6 +29,7 @@
--
-- Synthesized:
-- Date Rev viv Target flop lutl lutm bram slic
-- 2022-12-06 1324 2022.1 xc7a35t-1l 6851 8991 872 17.5 3133
-- 2022-07-05 1247 2022.1 xc7a35t-1l 6842 9218 872 17.5 3210
-- 2019-05-19 1150 2017.2 xc7a35t-1l 6838 10574 923 17.5 3392 +dz11
-- 2019-04-27 1140 2017.2 xc7a35t-1l 6706 10249 898 17.0 3380 +*buf

4
rtl/sys_gen/w11a/arty/sys_w11a_arty.vmfset
View File

@@ -1,4 +1,4 @@
# $Id: sys_w11a_arty.vmfset 1242 2022-05-27 17:08:43Z mueller $
# $Id: sys_w11a_arty.vmfset 1325 2022-12-07 11:52:36Z mueller $
#
# Validated code/tool version combinations
# Date rev viv
@@ -47,7 +47,6 @@ i [Synth 8-3331] pdp11_psr .* DIN[(8|9|10)]
# --> not all moni fields used # OK 2018-12-28
i [Synth 8-3331] pdp11_mmu_ssr12 .* MONI[(idone|trace_prev)]
# --> not all CNTL fieds used; also 6 LSBs from vaddr # OK 2018-12-28
i [Synth 8-3331] pdp11_mmu .* CNTL[trap_done]
i [Synth 8-3331] pdp11_mmu .* VADDR[(0|1|2|3|4|5)]
# --> so far no usage of usec and msec pulse # OK 2018-12-28
i [Synth 8-3331] rlink_sp2c .* (CE_USEC|CE_MSEC)
@@ -78,7 +77,6 @@ i [Synth 8-7129] DIN[(8|9|10)] .* pdp11_psr
# --> not all moni fields used # OK 2022-05-26
i [Synth 8-7129] MONI[(idone|trace_prev)] .* pdp11_mmu_ssr12
# --> not all CNTL fieds used; also 6 LSBs from vaddr # OK 2022-05-26
i [Synth 8-7129] CNTL[trap_done] .* pdp11_mmu
i [Synth 8-7129] VADDR[(0|1|2|3|4|5)] .* pdp11_mmu
# --> so far no usage of usec and msec pulse # OK 2022-05-26
i [Synth 8-7129] (CE_USEC|CE_MSEC) .* rlink_sp2c

4
rtl/sys_gen/w11a/arty_bram/sys_w11a_br_arty.vmfset
View File

@@ -1,4 +1,4 @@
# $Id: sys_w11a_br_arty.vmfset 1242 2022-05-27 17:08:43Z mueller $
# $Id: sys_w11a_br_arty.vmfset 1325 2022-12-07 11:52:36Z mueller $
#
# Validated code/tool version combinations
# Date rev viv
@@ -46,7 +46,6 @@ i [Synth 8-3331] pdp11_psr .* DIN[(8|9|10)]
# --> not all moni fields used # OK 2018-11-18
i [Synth 8-3331] pdp11_mmu_ssr12 .* MONI[(idone|trace_prev)]
# --> not all CNTL fieds used; also 6 LSBs from vaddr # OK 2018-11-18
i [Synth 8-3331] pdp11_mmu .* CNTL[trap_done]
i [Synth 8-3331] pdp11_mmu .* VADDR[(0|1|2|3|4|5)]
# --> so far no usage of usec and msec pulse # OK 2018-11-18
i [Synth 8-3331] rlink_sp2c .* (CE_USEC|CE_MSEC)
@@ -77,7 +76,6 @@ i [Synth 8-7129] DIN[(8|9|10)] .* pdp11_psr
# --> not all moni fields used # OK 2022-05-26
i [Synth 8-7129] MONI[(idone|trace_prev)] .* pdp11_mmu_ssr12
# --> not all CNTL fieds used; also 6 LSBs from vaddr # OK 2022-05-26
i [Synth 8-7129] CNTL[trap_done] .* pdp11_mmu
i [Synth 8-7129] VADDR[(0|1|2|3|4|5)] .* pdp11_mmu
# --> so far no usage of usec and msec pulse # OK 2022-05-26
i [Synth 8-7129] (CE_USEC|CE_MSEC) .* rlink_sp2c

4
rtl/sys_gen/w11a/artys7/sys_w11a_as7.vmfset
View File

@@ -1,4 +1,4 @@
# $Id: sys_w11a_as7.vmfset 1242 2022-05-27 17:08:43Z mueller $
# $Id: sys_w11a_as7.vmfset 1325 2022-12-07 11:52:36Z mueller $
#
# Validated code/tool version combinations
# Date rev viv
@@ -44,7 +44,6 @@ i [Synth 8-3331] pdp11_psr .* DIN[(8|9|10)]
# --> not all moni fields used # OK 2019-01-12
i [Synth 8-3331] pdp11_mmu_ssr12 .* MONI[(idone|trace_prev)]
# --> not all CNTL fieds used; also 6 LSBs from vaddr # OK 2019-01-12
i [Synth 8-3331] pdp11_mmu .* CNTL[trap_done]
i [Synth 8-3331] pdp11_mmu .* VADDR[(0|1|2|3|4|5)]
# --> so far no usage of usec and msec pulse # OK 2019-01-12
i [Synth 8-3331] rlink_sp2c .* (CE_USEC|CE_MSEC)
@@ -77,7 +76,6 @@ i [Synth 8-7129] DIN[(8|9|10)] .* pdp11_psr
# --> not all moni fields used # OK 2022-05-26
i [Synth 8-7129] MONI[(idone|trace_prev)] .* pdp11_mmu_ssr12
# --> not all CNTL fieds used; also 6 LSBs from vaddr # OK 2022-05-26
i [Synth 8-7129] CNTL[trap_done] .* pdp11_mmu
i [Synth 8-7129] VADDR[(0|1|2|3|4|5)] .* pdp11_mmu
# --> pdp11_hio70_arty doesn't use MEM_ACT # OK 2022-05-26
i [Synth 8-7129] MEM_ACT_(R|W) .* pdp11_hio70_artys7

4
rtl/sys_gen/w11a/artys7_bram/sys_w11a_br_as7.vmfset
View File

@@ -1,4 +1,4 @@
# $Id: sys_w11a_br_as7.vmfset 1242 2022-05-27 17:08:43Z mueller $
# $Id: sys_w11a_br_as7.vmfset 1325 2022-12-07 11:52:36Z mueller $
#
# Validated code/tool version combinations
# Date rev viv
@@ -46,7 +46,6 @@ i [Synth 8-3331] pdp11_psr .* DIN[(8|9|10)]
# --> not all moni fields used # OK 2018-11-18
i [Synth 8-3331] pdp11_mmu_ssr12 .* MONI[(idone|trace_prev)]
# --> not all CNTL fieds used; also 6 LSBs from vaddr # OK 2018-11-18
i [Synth 8-3331] pdp11_mmu .* CNTL[trap_done]
i [Synth 8-3331] pdp11_mmu .* VADDR[(0|1|2|3|4|5)]
# --> so far no usage of usec and msec pulse # OK 2018-11-18
i [Synth 8-3331] rlink_sp2c .* (CE_USEC|CE_MSEC)
@@ -79,7 +78,6 @@ i [Synth 8-7129] DIN[(8|9|10)] .* pdp11_psr
# --> not all moni fields used # OK 2022-05-26
i [Synth 8-7129] MONI[(idone|trace_prev)] .* pdp11_mmu_ssr12
# --> not all CNTL fieds used; also 6 LSBs from vaddr # OK 2022-05-26
i [Synth 8-7129] CNTL[trap_done] .* pdp11_mmu
i [Synth 8-7129] VADDR[(0|1|2|3|4|5)] .* pdp11_mmu
# --> so far no usage of usec and msec pulse # OK 2022-05-26
i [Synth 8-7129] (CE_USEC|CE_MSEC) .* rlink_sp2c

3
rtl/sys_gen/w11a/basys3/sys_w11a_b3.vhd
View File

@@ -1,4 +1,4 @@
-- $Id: sys_w11a_b3.vhd 1247 2022-07-06 07:04:33Z mueller $
-- $Id: sys_w11a_b3.vhd 1325 2022-12-07 11:52:36Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2015-2022 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@@ -26,6 +26,7 @@
--
-- Synthesized:
-- Date Rev viv Target flop lutl lutm bram slic
-- 2022-12-06 1324 2022.1 xc7a35t-1 3050 5501 267 48.0 1829
-- 2022-07-05 1247 2022.1 xc7a35t-1 3011 5669 267 48.0 1906
-- 2019-05-19 1150 2017.2 xc7a35t-1 2968 6360 273 48.0 1963 +dz11
-- 2019-04-27 1140 2017.2 xc7a35t-1 2835 6032 248 47.5 1879 +*buf

4
rtl/sys_gen/w11a/basys3/sys_w11a_b3.vmfset
View File

@@ -1,4 +1,4 @@
# $Id: sys_w11a_b3.vmfset 1242 2022-05-27 17:08:43Z mueller $
# $Id: sys_w11a_b3.vmfset 1325 2022-12-07 11:52:36Z mueller $
#
# Validated code/tool version combinations
# Date rev viv
@@ -47,7 +47,6 @@ i [Synth 8-3331] pdp11_psr .* DIN[(8|9|10)]
# --> not all moni fields used # OK 2018-11-18
i [Synth 8-3331] pdp11_mmu_ssr12 .* MONI[(idone|trace_prev)]
# --> not all CNTL fieds used; also 6 LSBs from vaddr # OK 2018-11-18
i [Synth 8-3331] pdp11_mmu .* CNTL[trap_done]
i [Synth 8-3331] pdp11_mmu .* VADDR[(0|1|2|3|4|5)]
# --> so far no usage of usec and msec pulse # OK 2018-11-18
i [Synth 8-3331] rlink_sp2c .* (CE_USEC|CE_MSEC)
@@ -78,7 +77,6 @@ i [Synth 8-7129] DIN[(8|9|10)] .* pdp11_psr
# --> not all moni fields used # OK 2022-05-26
i [Synth 8-7129] MONI[(idone|trace_prev)] .* pdp11_mmu_ssr12
# --> not all CNTL fieds used; also 6 LSBs from vaddr # OK 2022-05-26
i [Synth 8-7129] CNTL[trap_done] .* pdp11_mmu
i [Synth 8-7129] VADDR[(0|1|2|3|4|5)] .* pdp11_mmu
# --> so far no usage of usec and msec pulse # OK 2022-05-26
i [Synth 8-7129] (CE_USEC|CE_MSEC) .* rlink_sp2c

3
rtl/sys_gen/w11a/cmoda7/sys_w11a_c7.vhd
View File

@@ -1,4 +1,4 @@
-- $Id: sys_w11a_c7.vhd 1247 2022-07-06 07:04:33Z mueller $
-- $Id: sys_w11a_c7.vhd 1325 2022-12-07 11:52:36Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2017-2022 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@@ -28,6 +28,7 @@
--
-- Synthesized:
-- Date Rev viv Target flop lutl lutm bram slic
-- 2022-12-06 1324 2022.1 xc7a35t-1 3447 5998 278 50.0 1992
-- 2022-07-05 1247 2022.1 xc7a35t-1 3411 6189 279 50.0 2021
-- 2019-05-19 1150 2017.2 xc7a35t-1 3369 6994 285 50.0 2099 +dz11
-- 2019-04-27 1140 2017.2 xc7a35t-1 3243 6618 260 50.0 2009 +ibtst

4
rtl/sys_gen/w11a/cmoda7/sys_w11a_c7.vmfset
View File

@@ -1,4 +1,4 @@
# $Id: sys_w11a_c7.vmfset 1242 2022-05-27 17:08:43Z mueller $
# $Id: sys_w11a_c7.vmfset 1325 2022-12-07 11:52:36Z mueller $
#
# Validated code/tool version combinations
# Date rev viv
@@ -55,7 +55,6 @@ i [Synth 8-3331] pdp11_psr .* DIN[(8|9|10)]
# --> not all moni fields used # OK 2018-11-18
i [Synth 8-3331] pdp11_mmu_ssr12 .* MONI[(idone|trace_prev)]
# --> not all CNTL fieds used; also 6 LSBs from vaddr # OK 2018-11-18
i [Synth 8-3331] pdp11_mmu .* CNTL[trap_done]
i [Synth 8-3331] pdp11_mmu .* VADDR[(0|1|2|3|4|5)]
# --> so far no usage of usec and msec pulse # OK 2018-11-18
i [Synth 8-3331] rlink_sp2c .* (CE_USEC|CE_MSEC)
@@ -88,7 +87,6 @@ i [Synth 8-7129] DIN[(8|9|10)] .* pdp11_psr
# --> not all moni fields used # OK 2022-05-26
i [Synth 8-7129] MONI[(idone|trace_prev)] .* pdp11_mmu_ssr12
# --> not all CNTL fieds used; also 6 LSBs from vaddr # OK 2022-05-26
i [Synth 8-7129] CNTL[trap_done] .* pdp11_mmu
i [Synth 8-7129] VADDR[(0|1|2|3|4|5)] .* pdp11_mmu
# --> so far no usage of usec and msec pulse # OK 2022-05-26
i [Synth 8-7129] (CE_USEC|CE_MSEC) .* rlink_sp2c

7
rtl/sys_gen/w11a/nexys2/sys_w11a_n2.vhd
View File

@@ -1,6 +1,6 @@
-- $Id: sys_w11a_n2.vhd 1181 2019-07-08 17:00:50Z mueller $
-- $Id: sys_w11a_n2.vhd 1325 2022-12-07 11:52:36Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2010-2019 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2010-2022 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
------------------------------------------------------------------------------
-- Module Name: sys_w11a_n2 - syn
@@ -21,10 +21,11 @@
-- Test bench: tb/tb_sys_w11a_n2
--
-- Target Devices: generic
-- Tool versions: xst 8.2-14.7; ghdl 0.26-0.35
-- Tool versions: xst 8.2-14.7; ghdl 0.26-2.0.0
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2022-12-06 1324 14.7 131013 xc3s1200e-4 3225 9040 638 5848 ok: 67%
-- 2019-05-19 1150 14.7 131013 xc3s1200e-4 3219 8981 638 5796 ok: +dz11 66%
-- 2019-04-27 1140 14.7 131013 xc3s1200e-4 3087 ???? 588 5515 ok: +*buf 63%
-- 2019-03-02 1116 14.7 131013 xc3s1200e-4 3024 8246 526 5322 ok: +ibtst 61%

7
rtl/sys_gen/w11a/nexys3/sys_w11a_n3.vhd
View File

@@ -1,6 +1,6 @@
-- $Id: sys_w11a_n3.vhd 1181 2019-07-08 17:00:50Z mueller $
-- $Id: sys_w11a_n3.vhd 1325 2022-12-07 11:52:36Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2011-2019 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2011-2022 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
------------------------------------------------------------------------------
-- Module Name: sys_w11a_n3 - syn
@@ -21,10 +21,11 @@
-- Test bench: tb/tb_sys_w11a_n3
--
-- Target Devices: generic
-- Tool versions: xst 13.1-14.7; ghdl 0.29-0.35
-- Tool versions: xst 13.1-14.7; ghdl 0.29-2.0.0
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2022-12-06 1324 14.7 131013 xc6slx16-2 3227 6368 254 2182 ok: 95%
-- 2019-05-19 1150 14.7 131013 xc6slx16-2 3167 6052 248 2130 ok: +dz11 93%
-- 2019-05-01 1143 14.7 131013 xc6slx16-2 3062 5761 232 2057 ok: +m9312 90%
-- 2019-04-27 1140 14.7 131013 xc6slx16-2 3053 5742 232 2050 ok: +dlbuf 89%

4
rtl/sys_gen/w11a/nexys4/sys_w11a_n4.vmfset
View File

@@ -1,4 +1,4 @@
# $Id: sys_w11a_n4.vmfset 1242 2022-05-27 17:08:43Z mueller $
# $Id: sys_w11a_n4.vmfset 1325 2022-12-07 11:52:36Z mueller $
#
# Validated code/tool version combinations
# Date rev viv
@@ -48,7 +48,6 @@ i [Synth 8-3331] pdp11_psr .* DIN[(8|9|10)]
# --> not all moni fields used # OK 2018-11-18
i [Synth 8-3331] pdp11_mmu_ssr12 .* MONI[(idone|trace_prev)]
# --> not all CNTL fieds used; also 6 LSBs from vaddr # OK 2018-11-18
i [Synth 8-3331] pdp11_mmu .* CNTL[trap_done]
i [Synth 8-3331] pdp11_mmu .* VADDR[(0|1|2|3|4|5)]
# --> so far no usage of usec and msec pulse # OK 2018-11-18
i [Synth 8-3331] rlink_sp2c .* (CE_USEC|CE_MSEC)
@@ -78,7 +77,6 @@ i [Synth 8-7129] DIN[(8|9|10)] .* pdp11_psr
# --> not all moni fields used # OK 2022-05-26
i [Synth 8-7129] MONI[(idone|trace_prev)] .* pdp11_mmu_ssr12
# --> not all CNTL fieds used; also 6 LSBs from vaddr # OK 2022-05-26
i [Synth 8-7129] CNTL[trap_done] .* pdp11_mmu
i [Synth 8-7129] VADDR[(0|1|2|3|4|5)] .* pdp11_mmu
# --> so far no usage of usec and msec pulse # OK 2022-05-26
i [Synth 8-7129] (CE_USEC|CE_MSEC) .* rlink_sp2c

3
rtl/sys_gen/w11a/nexys4d/sys_w11a_n4d.vhd
View File

@@ -1,4 +1,4 @@
-- $Id: sys_w11a_n4d.vhd 1247 2022-07-06 07:04:33Z mueller $
-- $Id: sys_w11a_n4d.vhd 1325 2022-12-07 11:52:36Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2019-2022 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@@ -28,6 +28,7 @@
--
-- Synthesized:
-- Date Rev viv Target flop lutl lutm bram slic MHz
-- 2022-12-06 1324 2022.1 xc7a100t-1 6852 8773 868 17.5 3240 80
-- 2022-07-05 1247 2022.1 xc7a100t-1 6805 8961 869 17.5 3282 80
-- 2019-08-10 1201 2019.1 xc7a100t-1 6850 10258 901 17.5 3563 80
-- 2019-05-19 1150 2017.2 xc7a100t-1 6811 10322 901 17.5 3496 80 +dz11

4
rtl/sys_gen/w11a/nexys4d/sys_w11a_n4d.vmfset
View File

@@ -1,4 +1,4 @@
# $Id: sys_w11a_n4d.vmfset 1242 2022-05-27 17:08:43Z mueller $
# $Id: sys_w11a_n4d.vmfset 1325 2022-12-07 11:52:36Z mueller $
#
# Validated code/tool version combinations
# Date rev viv
@@ -49,7 +49,6 @@ i [Synth 8-3331] pdp11_psr .* DIN[(8|9|10)]
# --> not all moni fields used # OK 2019-01-02
i [Synth 8-3331] pdp11_mmu_ssr12 .* MONI[(idone|trace_prev)]
# --> not all CNTL fieds used; also 6 LSBs from vaddr # OK 2019-01-02
i [Synth 8-3331] pdp11_mmu .* CNTL[trap_done]
i [Synth 8-3331] pdp11_mmu .* VADDR[(0|1|2|3|4|5)]
# --> so far no usage of usec and msec pulse # OK 2019-01-02
i [Synth 8-3331] rlink_sp2c .* (CE_USEC|CE_MSEC)
@@ -80,7 +79,6 @@ i [Synth 8-7129] DIN[(8|9|10)] .* pdp11_psr
# --> not all moni fields used # OK 2022-05-26
i [Synth 8-7129] MONI[(idone|trace_prev)] .* pdp11_mmu_ssr12
# --> not all CNTL fieds used; also 6 LSBs from vaddr # OK 2022-05-26
i [Synth 8-7129] CNTL[trap_done] .* pdp11_mmu
i [Synth 8-7129] VADDR[(0|1|2|3|4|5)] .* pdp11_mmu
# --> so far no usage of usec and msec pulse # OK 2022-05-26
i [Synth 8-7129] (CE_USEC|CE_MSEC) .* rlink_sp2c

4
rtl/sys_gen/w11a/nexys4d_bram/sys_w11a_br_n4d.vmfset
View File

@@ -1,4 +1,4 @@
# $Id: sys_w11a_br_n4d.vmfset 1242 2022-05-27 17:08:43Z mueller $
# $Id: sys_w11a_br_n4d.vmfset 1325 2022-12-07 11:52:36Z mueller $
#
# Validated code/tool version combinations
# Date rev viv
@@ -43,7 +43,6 @@ i [Synth 8-3331] pdp11_psr .* DIN[(8|9|10)]
# --> not all moni fields used # OK 2018-11-18
i [Synth 8-3331] pdp11_mmu_ssr12 .* MONI[(idone|trace_prev)]
# --> not all CNTL fieds used; also 6 LSBs from vaddr # OK 2018-11-18
i [Synth 8-3331] pdp11_mmu .* CNTL[trap_done]
i [Synth 8-3331] pdp11_mmu .* VADDR[(0|1|2|3|4|5)]
# --> so far no usage of usec and msec pulse # OK 2018-11-18
i [Synth 8-3331] rlink_sp2c .* (CE_USEC|CE_MSEC)
@@ -74,7 +73,6 @@ i [Synth 8-7129] DIN[(8|9|10)] .* pdp11_psr
# --> not all moni fields used # OK 2022-05-26
i [Synth 8-7129] MONI[(idone|trace_prev)] .* pdp11_mmu_ssr12
# --> not all CNTL fieds used; also 6 LSBs from vaddr # OK 2022-05-26
i [Synth 8-7129] CNTL[trap_done] .* pdp11_mmu
i [Synth 8-7129] VADDR[(0|1|2|3|4|5)] .* pdp11_mmu
# --> so far no usage of usec and msec pulse # OK 2022-05-26
i [Synth 8-7129] (CE_USEC|CE_MSEC) .* rlink_sp2c

17
rtl/sys_gen/w11a/s3board/sys_conf.vhd
View File

@@ -1,15 +1,16 @@
-- $Id: sys_conf.vhd 1181 2019-07-08 17:00:50Z mueller $
-- $Id: sys_conf.vhd 1325 2022-12-07 11:52:36Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2007-2019 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2007-2022 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for sys_w11a_s3 (for synthesis)
--
-- Dependencies: -
-- Tool versions: xst 8.1-14.7; ghdl 0.18-0.35
-- Tool versions: xst 8.1-14.7; ghdl 0.18-2022.1
-- Revision History:
-- Date Rev Version Comment
-- 2022-12-05 1324 1.4.2 disable dmhbpt,dmcmon,m9312 for timing closure
-- 2019-04-28 1142 1.4.1 add sys_conf_ibd_m9312
-- 2019-02-09 1110 1.4 use typ for DL,PC,LP; add dz11,ibtst
-- 2019-01-27 1108 1.3.7 drop iist
@@ -45,8 +46,8 @@ package sys_conf is
constant sys_conf_ibtst : boolean := true;
constant sys_conf_dmscnt : boolean := true;
constant sys_conf_dmpcnt : boolean := true;
constant sys_conf_dmhbpt_nunit : integer := 2; -- use 0 to disable
constant sys_conf_dmcmon_awidth : integer := 8; -- use 0 to disable
constant sys_conf_dmhbpt_nunit : integer := 0; -- use 0 to disable
constant sys_conf_dmcmon_awidth : integer := 0; -- use 0 to disable
-- configure w11 cpu core --------------------------------------------------
constant sys_conf_mem_losize : natural := 8#037777#; -- 1 MByte
@@ -62,7 +63,7 @@ package sys_conf is
constant sys_conf_ibd_dz11 : integer := 5; -- DZ11
constant sys_conf_ibd_pc11 : integer := 4; -- PC11
constant sys_conf_ibd_lp11 : integer := 5; -- LP11
constant sys_conf_ibd_deuna : boolean := true; -- DEUNA
constant sys_conf_ibd_deuna : boolean := false; -- DEUNA
-- configure mass storage devices
constant sys_conf_ibd_rk11 : boolean := true; -- RK11
@@ -72,7 +73,7 @@ package sys_conf is
-- configure other devices
constant sys_conf_ibd_iist : boolean := false; -- IIST
constant sys_conf_ibd_kw11p : boolean := true; -- KW11P
constant sys_conf_ibd_m9312 : boolean := true; -- M9312
constant sys_conf_ibd_kw11p : boolean := false; -- KW11P
constant sys_conf_ibd_m9312 : boolean := false; -- M9312
end package sys_conf;

9
rtl/sys_gen/w11a/s3board/sys_w11a_s3.vhd
View File

@@ -1,6 +1,6 @@
-- $Id: sys_w11a_s3.vhd 1181 2019-07-08 17:00:50Z mueller $
-- $Id: sys_w11a_s3.vhd 1325 2022-12-07 11:52:36Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2007-2019 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2007-2022 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
------------------------------------------------------------------------------
-- Module Name: sys_w11a_s3 - syn
@@ -20,10 +20,11 @@
-- Test bench: tb/tb_sys_w11a_s3
--
-- Target Devices: generic
-- Tool versions: xst 8.2-14.7; ghdl 0.18-0.35
-- Tool versions: xst 8.2-14.7; ghdl 0.18-2.0.0
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2022-12-06 1324 14.7 131013 xc3s1000-4 2620 7940 542 4929 OK: -dm,deu 64%
-- 2019-05-19 1150 14.7 131013 xc3s1000-4 3019 8764 574 5558 OK: +dz11 72%
-- 2019-04-27 1140 14.7 131013 xc3s1000-4 2890 8306 524 5252 OK: +*buf 68%
-- 2019-03-02 1116 14.7 131013 xc3s1000-4 2830 8045 462 5086 OK: +ibtst 66%
@@ -73,6 +74,8 @@
--
-- Revision History:
-- Date Rev Version Comment
-- 2022-12-06 1324 2.2.2 remove dmhbpt,dmcmon,deuna,kw11p,m9312 to mitigate
-- recurring timing closure problems
-- 2019-02-16 1112 2.2.1 set BTOWIDTH 7 (was 6, must > vmbox atowidth (6))
-- 2018-10-13 1055 2.2 use DM_STAT_EXP; IDEC to maxisys; setup PERFEXT
-- 2016-03-19 748 2.1.1 define rlink SYSID

12
rtl/w11a/pdp11.vhd
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@@ -1,4 +1,4 @@
-- $Id: pdp11.vhd 1323 2022-12-01 08:00:41Z mueller $
-- $Id: pdp11.vhd 1325 2022-12-07 11:52:36Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2006-2022 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@@ -11,6 +11,8 @@
--
-- Revision History:
-- Date Rev Version Comment
-- 2022-12-05 1324 1.5.19 add cpustat_type treq_tbit and resetcnt;
-- use op_rti rather op_rtt;
-- 2022-11-29 1323 1.5.18 rename cpuerr_type adderr->oddadr, mmu_mmr0_type
-- dspace->page_dspace; drop mmu_cntl_type.trap_done
-- 2022-11-24 1321 1.5.17 add cpustat_type intpend
@@ -266,7 +268,7 @@ package pdp11 is
is_rmwop : slbit; -- read-modify-write operation
is_bytop : slbit; -- byte operation
is_res : slbit; -- reserved operation code
op_rtt : slbit; -- RTT instruction
op_rti : slbit; -- RTI instruction
op_mov : slbit; -- MOV instruction
trap_vec : slv3; -- trap vector addr bits 4:2
force_srcsp : slbit; -- force src register to be sp
@@ -382,8 +384,10 @@ package pdp11 is
intack : slbit; -- INT_ACK pulse
intpend : slbit; -- interrupt pending
intvect : slv9_2; -- current interrupt vector
resetcnt : slv3; -- RESET wait timer counter
treq_mmu : slbit; -- mmu trap requested
treq_ysv : slbit; -- ysv trap requested
treq_tbit : slbit; -- tbit trap requested
prefdone : slbit; -- prefetch done
do_grwe : slbit; -- pending gr_we
in_vecser : slbit; -- in fatal stack error vector flow
@@ -398,8 +402,8 @@ package pdp11 is
"00000","000", -- cpfunc, cprnum
'0', -- waitsusp
'0','0','0','0','0', -- itimer,creset,breset,intack,intpend
(others=>'0'), -- intvect
'0','0','0', -- treq_(mmu|ysv), prefdone
(others=>'0'),"111", -- intvect,resetcnt
'0','0','0','0', -- treq_(mmu|ysv|tbit), prefdone
'0','0','0' -- do_grwe, in_vec(ser|ysv)
);

7
rtl/w11a/pdp11_decode.vhd
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@@ -1,4 +1,4 @@
-- $Id: pdp11_decode.vhd 1310 2022-10-27 16:15:50Z mueller $
-- $Id: pdp11_decode.vhd 1325 2022-12-07 11:52:36Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2006-2022 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@@ -12,6 +12,7 @@
-- Tool versions: ise 8.2-14.7; viv 2014.4-2022.1; ghdl 0.18-2.0.0
-- Revision History:
-- Date Rev Version Comment
-- 2022-12-02 1324 1.0.9 use op_rti rather op_rtt
-- 2022-10-25 1309 1.0.8 rename _gpr -> _gr
-- 2022-10-03 1301 1.0.7 add STAT.is_dstpcmode1
-- 2011-11-18 427 1.0.6 now numeric_std clean
@@ -93,7 +94,7 @@ begin
nstat.is_rmwop := '0';
nstat.is_bytop := '0';
nstat.is_res := '1';
nstat.op_rtt := '0';
nstat.op_rti := '0';
nstat.op_mov := '0';
nstat.trap_vec := "000";
nstat.force_srcsp := '0';
@@ -165,6 +166,7 @@ begin
nstat.do_fork_op := '1';
when "010" => -- RTI
nstat.op_rti := '1';
nstat.force_srcsp := '1';
nstat.fork_op := c_fork_op_rtti;
nstat.do_fork_op := '1';
@@ -184,7 +186,6 @@ begin
nstat.do_fork_op := '1';
when "110" => -- RTT
nstat.op_rtt := '1';
nstat.force_srcsp := '1';
nstat.fork_op := c_fork_op_rtti;
nstat.do_fork_op := '1';

147
rtl/w11a/pdp11_sequencer.vhd
View File

@@ -1,4 +1,4 @@
-- $Id: pdp11_sequencer.vhd 1323 2022-12-01 08:00:41Z mueller $
-- $Id: pdp11_sequencer.vhd 1325 2022-12-07 11:52:36Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2006-2022 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@@ -13,6 +13,8 @@
--
-- Revision History:
-- Date Rev Version Comment
-- 2022-12-05 1324 1.6.23 tbit logic overhaul; use treq_tbit; cleanups
-- use resetcnt for 8 cycle RESET wait
-- 2022-11-29 1323 1.6.22 rename adderr -> oddadr, don't set after err_mmu
-- 2022-11-28 1322 1.6.21 BUGFIX: correct mmu trap vs interrupt priority
-- 2022-11-24 1321 1.6.20 BUGFIX: correct mmu trap handing in s_idecode
@@ -407,13 +409,12 @@ begin
pbytop : in slbit := '0';
pmacc : in slbit := '0';
pispace : in slbit := '0';
kstack : in slbit := '0') is
pkstack : in slbit := '0') is
begin
pnvmcntl.dspace := not pispace;
-- bytop := R_IDSTAT.is_bytop and not is_addr;
pnvmcntl.bytop := pbytop;
pnvmcntl.macc := pmacc;
pnvmcntl.kstack := kstack;
pnvmcntl.kstack := pkstack;
pnvmcntl.req := '1';
pnstate := pwstate;
end procedure do_memread_d;
@@ -539,13 +540,14 @@ begin
pnstatus : inout cpustat_type;
pnmmumoni : inout mmu_moni_type) is
begin
pnmmumoni.idone := '1';
if R_STATUS.treq_mmu='1' or pnstatus.treq_mmu='1' or
R_STATUS.treq_ysv='1' or pnstatus.treq_ysv='1' or
PSW.tflag='1' then
pnmmumoni.idone := '1'; -- priority order
if pnstatus.treq_mmu='1' or -- mmu trap
pnstatus.treq_ysv='1' then -- ysv trap
pnstate := s_trap_disp;
elsif unsigned(INT_PRI) > unsigned(PSW.pri) then
elsif unsigned(INT_PRI) > unsigned(PSW.pri) then -- interrupts
pnstate := s_idle;
elsif pnstatus.treq_tbit='1' then -- tbit trap
pnstate := s_trap_disp;
elsif R_STATUS.cpugo='1' and -- running
R_STATUS.cpususp='0' and -- and not suspended
not R_STATUS.cmdbusy='1' then -- and no cmd pending
@@ -563,13 +565,14 @@ begin
begin
pndpcntl := pndpcntl; -- dummy to add driver (vivado)
pnvmcntl := pnvmcntl; -- "
pnmmumoni.idone := '1';
if R_STATUS.treq_mmu='1' or pnstatus.treq_mmu='1' or
R_STATUS.treq_ysv='1' or pnstatus.treq_ysv='1' or
PSW.tflag='1' then
pnmmumoni.idone := '1'; -- priority order
if pnstatus.treq_mmu='1' or -- mmu trap
pnstatus.treq_ysv='1' then -- ysv trap
pnstate := s_trap_disp;
elsif unsigned(INT_PRI) > unsigned(PSW.pri) then
elsif unsigned(INT_PRI) > unsigned(PSW.pri) then -- interrupts
pnstate := s_idle;
elsif pnstatus.treq_tbit='1' then -- tbit trap
pnstate := s_trap_disp;
elsif R_STATUS.cpugo='1' and -- running
R_STATUS.cpususp='0' and -- and not suspended
not R_STATUS.cmdbusy='1' then -- and no cmd pending
@@ -780,9 +783,12 @@ begin
if R_STATUS.cpugo = '1' then -- if already running
nstatus.cmderr := '1'; -- reject
else -- if not running
nstatus.creset := '1'; -- do cpu reset
nstatus.breset := '1'; -- and bus reset !
nstatus.suspint := '0'; -- clear suspend
nstatus.creset := '1'; -- do cpu reset
nstatus.breset := '1'; -- and bus reset !
nstatus.suspint := '0'; -- clear suspend
nstatus.treq_mmu := '0'; -- cancel trap requests
nstatus.treq_ysv := '0';
nstatus.treq_tbit := '0';
nstatus.cpurust := c_cpurust_init;
end if;
nstate := s_idle;
@@ -860,15 +866,20 @@ begin
nstate := s_op_wait; --waitsusp is cleared in s_op_wait
elsif R_STATUS.cpugo = '1' and -- running
R_STATUS.cpususp='0' then -- and not suspended
if int_pending = '1' then -- interrupt pending
nstatus.intack := '1'; -- acknowledle it
nstatus.intvect := INT_VECT; -- latch vector address
nstate := s_int_ext; -- and handle
R_STATUS.cpususp='0' then -- and not suspended
-- proceed in priority order
if R_STATUS.treq_mmu='1' and -- mmu trap
R_STATUS.treq_ysv='1' then -- ysv trap
nstate := s_trap_disp;
elsif R_STATUS.intpend = '1' then -- interrupts
nstatus.intack := '1'; -- acknowledle it
nstatus.intvect := INT_VECT; -- latch vector address
nstate := s_int_ext; -- and handle
elsif R_STATUS.treq_tbit = '1' then -- tbit trap
nstate := s_trap_disp;
else
nstate := s_ifetch; -- otherwise fetch intruction
nstate := s_ifetch; -- otherwise fetch intruction
end if;
end if;
when s_cp_regread => -- -----------------------------------
@@ -893,8 +904,6 @@ begin
ndpcntl.dres_sel := c_dpath_res_vmdout; -- DRES = VMDOUT
if (VM_STAT.ack or VM_STAT.err or VM_STAT.fail)='1' then
nstatus.cmdack := '1';
nstatus.treq_ysv := '0'; -- suppress traps on console
nstatus.treq_mmu := '0';
nstatus.cmdmerr := VM_STAT.err or VM_STAT.fail;
nstate := s_idle;
end if;
@@ -904,8 +913,6 @@ begin
nstate := s_cp_memw_w;
if (VM_STAT.ack or VM_STAT.err or VM_STAT.fail)='1' then
nstatus.cmdack := '1';
nstatus.treq_ysv := '0'; -- suppress traps on console
nstatus.treq_mmu := '0';
nstatus.cmdmerr := VM_STAT.err or VM_STAT.fail;
nstate := s_idle;
end if;
@@ -939,24 +946,29 @@ begin
nvmcntl.dspace := '0';
ndpcntl.vmaddr_sel := c_dpath_vmaddr_pc; -- VA = PC
-- The prefetch decision path can be critical (and was on s3).
-- It uses R_STATUS.intpend instead of int_pending, using the status
-- latched at the previous state is OK. It uses R_STATUS.treq_mmu
-- because no MMU trap can occur during this state (only in *_w states).
-- It does not check treq_ysv because pipelined instructions can't
-- trigger ysv traps, in contrast to MMU traps.
if ID_STAT.do_pref_dec='1' and -- prefetch possible
PSW.tflag='0' and -- no tbit traps
R_STATUS.intpend='0' and -- no interrupts
R_STATUS.treq_mmu='0' and -- no MMU trap request
R_STATUS.cpugo='1' and -- CPU on go
R_STATUS.cpususp='0' and -- CPU not suspended
not R_STATUS.cmdbusy='1' -- and no command pending
then -- then go for prefetch
nvmcntl.req := '1';
ndpcntl.gr_pcinc := '1'; -- (pc)++
nmmumoni.istart := '1';
nstatus.prefdone := '1';
nstatus.resetcnt := "111"; -- set RESET wait timer
if PSW.tflag='1' then -- if PSW tbit set
nstatus.treq_tbit := '1'; -- request tbit
else
-- The prefetch decision path can be critical (and was on s3). It uses
-- R_STATUS.intpend instead of int_pending, using the status latched
-- at the previous state is OK. It uses R_STATUS.treq_mmu because
-- no MMU trap can occur during this state (only in *_w states).
-- It does not check treq_ysv because pipelined instructions can't
-- trigger ysv traps, in contrast to MMU traps.
if ID_STAT.do_pref_dec='1' and -- prefetch possible
R_STATUS.intpend='0' and -- no interrupts
R_STATUS.treq_mmu='0' and -- no MMU trap request
R_STATUS.cpugo='1' and -- CPU on go
R_STATUS.cpususp='0' and -- CPU not suspended
not R_STATUS.cmdbusy='1' -- and no command pending
then -- then go for prefetch
nvmcntl.req := '1';
ndpcntl.gr_pcinc := '1'; -- (pc)++
nmmumoni.istart := '1';
nstatus.prefdone := '1';
end if;
end if;
if ID_STAT.do_fork_op = '1' then
@@ -1213,7 +1225,7 @@ begin
do_memread_d(nstate, nvmcntl, s_dstr_def_w,
pbytop=>R_IDSTAT.is_bytop, pmacc=>R_IDSTAT.is_rmwop,
pispace=>R_IDSTAT.is_dstpcmode1,
kstack=>is_kstackdst1246 and R_IDSTAT.is_rmwop);
pkstack=>is_kstackdst1246 and R_IDSTAT.is_rmwop);
when s_dstr_def_w => -- -----------------------------------
nstate := s_dstr_def_w;
@@ -1239,7 +1251,7 @@ begin
bytop := R_IDSTAT.is_bytop and not DSTDEF;
do_memread_d(nstate, nvmcntl, s_dstr_inc_w,
pbytop=>bytop, pmacc=>macc, pispace=>R_IDSTAT.is_dstpc,
kstack=>is_kstackdst1246 and R_IDSTAT.is_rmwop);
pkstack=>is_kstackdst1246 and R_IDSTAT.is_rmwop);
when s_dstr_inc_w => -- -----------------------------------
nstate := s_dstr_inc_w;
@@ -1275,7 +1287,7 @@ begin
bytop := R_IDSTAT.is_bytop and not DSTDEF;
do_memread_d(nstate, nvmcntl, s_dstr_inc_w,
pbytop=>bytop, pmacc=>macc,
kstack=>is_kstackdst1246 and R_IDSTAT.is_rmwop);
pkstack=>is_kstackdst1246 and R_IDSTAT.is_rmwop);
when s_dstr_ind => -- -----------------------------------
do_memread_i(nstate, ndpcntl, nvmcntl, s_dstr_ind1_w);
@@ -1302,7 +1314,7 @@ begin
bytop := R_IDSTAT.is_bytop and not DSTDEF;
do_memread_d(nstate, nvmcntl, s_dstr_ind2_w,
pbytop=>bytop, pmacc=>macc,
kstack=>is_kstackdst1246 and R_IDSTAT.is_rmwop);
pkstack=>is_kstackdst1246 and R_IDSTAT.is_rmwop);
when s_dstr_ind2_w => -- -----------------------------------
nstate := s_dstr_ind2_w;
@@ -1628,16 +1640,24 @@ begin
nstatus.itimer := '1'; -- itimer will stay 1 during a WAIT
end if;
when s_op_trap => -- traps -----------------------------
when s_op_trap => -- trap instructions (IOT,BPT,..) ----
idm_idone := '1'; -- instruction done
lvector := "0000" & R_IDSTAT.trap_vec; -- vector
do_start_vec(nstate, ndpcntl, lvector);
when s_op_reset => -- RESET -----------------------------
nstate := s_op_reset; -- default is spin till timer expire
nstatus.resetcnt := slv(unsigned(R_STATUS.resetcnt) - 1); -- dec timer
if is_kmode = '1' then -- if in kernel mode execute
nstatus.breset := '1'; -- issue bus reset
if R_STATUS.resetcnt = "111" then -- in first cycle
nstatus.breset := '1'; -- issue bus reset
end if;
if R_STATUS.resetcnt = "000" then -- in last cycle
nstate := s_idle; -- done, continue via s_idle
end if;
else -- if not in kernel mode
nstate := s_idle; -- nop, continue via s_idle
end if;
nstate := s_idle;
when s_op_rts => -- RTS -------------------------------
ndpcntl.ounit_asel := c_ounit_asel_ddst; -- OUNIT A=DDST
@@ -2183,8 +2203,9 @@ begin
else
lvector := "0000011"; -- trace trap: vector (14)
end if;
nstatus.treq_mmu := '0'; -- clear trap request flags
nstatus.treq_ysv := '0'; --
nstatus.treq_mmu := '0'; -- clear trap request flags
nstatus.treq_ysv := '0'; --
nstatus.treq_tbit := '0'; --
do_start_vec(nstate, ndpcntl, lvector);
when s_int_ext => -- -----------------------------------
@@ -2195,6 +2216,7 @@ begin
when s_vec_getpc => -- -----------------------------------
idm_vfetch := '1'; -- signal vfetch
nstatus.treq_tbit := '0'; -- cancel pending tbit request
nvmcntl.mode := c_psw_kmode; -- fetch PC from kernel D space
do_memread_srcinc(nstate, ndpcntl, nvmcntl, s_vec_getpc_w, nmmumoni);
@@ -2339,6 +2361,10 @@ begin
end if;
when s_rti_newpc => -- -----------------------------------
if R_IDSTAT.op_rti = '1' and -- if RTI instruction
PSW.tflag = '1' then -- and PSW tflag set now
nstatus.treq_tbit := '1'; -- request immediate tbit
end if;
ndpcntl.ounit_asel := c_ounit_asel_ddst; -- OUNIT A=DDST
ndpcntl.ounit_bsel := c_ounit_bsel_const; -- OUNIT B=const (0)
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
@@ -2346,11 +2372,7 @@ begin
ndpcntl.gr_we := '1'; -- load new PC
idm_pcload := '1'; -- signal flow change
idm_idone := '1'; -- instruction done
if R_IDSTAT.op_rtt = '1' then -- if RTT instruction
nstate := s_ifetch; -- force fetch
else -- otherwise RTI
do_fork_next(nstate, nstatus, nmmumoni);
end if;
do_fork_next(nstate, nstatus, nmmumoni);
-- exception abort states ---------------------------------------------------
@@ -2365,8 +2387,9 @@ begin
ndpcntl.gr_mode := c_psw_kmode; -- set kmode SP to 4
ndpcntl.gr_adst := c_gr_sp;
nstatus.treq_mmu := '0'; -- cancel mmu trap request
nstatus.treq_ysv := '0'; -- cancel ysv trap request
nstatus.treq_mmu := '0'; -- cancel mmu trap request
nstatus.treq_ysv := '0'; -- cancel ysv trap request
nstatus.treq_tbit := '0'; -- cancel tbit trap request
if R_VMSTAT.fail = '1' then -- vmbox failure
nstatus.cpugo := '0'; -- halt cpu