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minor edits; add cpu_mmu test
- tools/bin/tmuconv: change VFETCH text for MMU(250) and FPP(244) - tools/tcode/cpu_mmu.mac: add test C2.4: mmu abort vs nxm abort - doc/w11a_diff_70_mmu_nxm_prio.md: additional known w11 difference
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wfjm
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doc/w11a_diff_70_mmu_nxm_prio.md
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doc/w11a_diff_70_mmu_nxm_prio.md
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## Known differences between w11a and KB11-C (11/70)
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### MMU aborts have priority over NXM aborts
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Let's assume a case where two address errors are present:
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- the MMU rejects the access
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- the MMU translated physical address is located in non-existent memory
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Both checks run in parallel in hardware. The MMU logic uses the access control
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field and the page length field to check whether access is allowed.
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And the physical address is formed from the selected PAR and the resulting
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virtual address and compared with the memory size register.
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In the KB11-C processor, the NXM condition is handled before the MMU condition.
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This leads to the surprising situation that the access is aborted with a
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vector 4 flow rather than a vector 250 flow.
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The w11 logic inspects the MMU condition first and then the NXM condition.
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So a case like the one described above is terminated with a vector 250 flow.
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The `ekbee1` diagnostic tests this behavior in test 122. In fact, the code
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distinguishes between the KB11-B/C processor and the KB11-E processor
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that never made it to market.
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In the case of KB11-C, NXM takes precedence over MMU, and and in the case of
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KB11-E, MMU takes precedence over NXM.
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In case of an MMU plus NXM double error, the w11 therefore behaves like
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a KB11-E and not like a KB11-C.
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@@ -13,6 +13,7 @@ The issues of the w11 CPU and systems are listed in a separate document
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- [`jsr sp` pushes original `sp` value](w11a_diff_70_jsr_sp.md)
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- [18-bit UNIBUS address space not mapped](w11a_diff_70_unibus_mapping.md)
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- [MMU traps not suppressed when MMU register accessed](w11a_diff_70_mmu_trap_suppression.md)
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- [MMU aborts have priority over NXM aborts](w11a_diff_70_mmu_nxm_prio.md)
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All points relate to very 11/70 specific behavior, no operating system
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depends on them, therefore they are considered acceptable implementation
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@@ -1,10 +1,11 @@
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#!/usr/bin/perl -w
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# $Id: tmuconv 1316 2022-11-18 15:26:40Z mueller $
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# $Id: tmuconv 1324 2022-12-01 11:24:20Z mueller $
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# SPDX-License-Identifier: GPL-3.0-or-later
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# Copyright 2008-2022 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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#
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# Revision History:
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# Date Rev Version Comment
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# 2022-12-01 1324 1.1.11 change VFETCH text for MMU(250) and FPP(244)
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# 2022-11-18 1316 1.1.10 add -t_ru06 and -t_flow
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# 2022-10-25 1309 1.1.9 rename _gpr -> _gr
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# 2022-08-22 1283 1.1.8 print ru after em,ib, best for reg from mem cases
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@@ -773,8 +774,8 @@ sub do_file {
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$emtyp_str .= " 220 RK11" if ($emlast_addr == 0220);
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$emtyp_str .= " 224 TM11" if ($emlast_addr == 0224);
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$emtyp_str .= " 240 PIRQ" if ($emlast_addr == 0240);
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$emtyp_str .= " 244 FPP exp" if ($emlast_addr == 0244);
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$emtyp_str .= " 250 MMU trap" if ($emlast_addr == 0250);
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$emtyp_str .= " 244 FPE" if ($emlast_addr == 0244);
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$emtyp_str .= " 250 MMU" if ($emlast_addr == 0250);
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$emtyp_str .= " 254 RHRP" if ($emlast_addr == 0254);
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$emtyp_str .= " 260 IIST" if ($emlast_addr == 0260);
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$emtyp_str .= " 300 DL11-2-TTI" if ($emlast_addr == 0300);
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@@ -1,10 +1,10 @@
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; $Id: cpu_mmu.mac 1323 2022-12-01 08:00:41Z mueller $
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; $Id: cpu_mmu.mac 1324 2022-12-01 11:24:20Z mueller $
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; SPDX-License-Identifier: GPL-3.0-or-later
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; Copyright 2022- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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;
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; Revision History:
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; Date Rev Version Comment
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; 2022-11-29 1323 1.0 Initial version
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; 2022-12-01 1324 1.0 Initial version
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; 2022-07-24 1262 0.1 First draft
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;
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; Test CPU MMU: all aspects of the MMU
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@@ -1268,6 +1268,46 @@ tc0203: mov #vhmmua,v..mmu
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clr v..mmu+2
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9999$: iot ; end of test C2.3
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;
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; Test C2.4 -- mmu abort vs nxm abort ++++++++++++++++++++++++++++++++
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; On a KB11-C a NXM abort has priority over an MMU abort. An access via
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; an acf=7 (reserved) page mapped to non-existing memory is aborted as an
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; NXM error (vector 4) and not as an MMU error (vector 250). On a KB11-E
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; an MMU error is taken. This behavior is checked in test 122 of ekbee1.
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; The w11, and also SimH and e11, follow the KB11-E behavior which is the
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; natural and expected behavior.
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;
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tc0204: mov cp.los,kipar6 ; map begin of non-existent memory
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mov #<127.*md.plf>!md.arw,kipdr6 ; allow access
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mov #m3.e22,mmr3 ; enable 22-bit mode
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mov #m0.ena,mmr0 ; enable mmu with traps ;! MMU 22
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;
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; part1: MMU allows access to NXM memory --> NXM abort ---------------
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;
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clr cp.err ; clear CPUERR
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mov #1000$,v..iit ; set vector 4 handler for NXM abort
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clr @#p6p1p2 ; access
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halt
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1000$: mov #stack,sp ; vector 4 taken
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hcmpeq cp.err,#cp.nxm ; NXM error seen
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mov #v..iit+2,v..iit ; restore iit handler to catcher
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;
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; part2: MMU denies access to NXM memory --> MMU abort ---------------
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;
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mov #<127.*md.plf>!md.an7,kipdr6 ; deny access via acf=7
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clr cp.err ; clear CPUERR
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mov #2000$,v..mmu ; set vector 250 handler for MMU abort
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clr @#p6p1p2 ; access
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halt
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2000$: mov #stack,sp ; vector 250 taken
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htsteq cp.err ; check CPUERR (no NXM expected)
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mov #v..mmu+2,v..mmu ; restore mmu handler to catcher
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;
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reset ; mmu off ;! MMU off
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mov #001400,kipar6 ; reset kipar6
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mov #<127.*md.plf>!md.arw,kipdr6 ; reset kipdr6
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;
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9999$: iot ; end of test C2.4
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;
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; Section D: mmr2+mmr1+mmr0 register, abort recovery =========================
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;
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@@ -1922,7 +1962,7 @@ tf0102: mov #154345,@#p6base ; inititialize target
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;; END OF ALL TESTS - loop closure ============================================
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;
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mov tstno,r0 ; hack, for easy monitoring ...
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hcmpeq tstno,#22. ; all tests done ?
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hcmpeq tstno,#23. ; all tests done ?
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;
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jmp loop
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;
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