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- interim release w11a_V0.581 (untagged)

Browse Source 
- new reference system
  - switched from ISE 13.3 to 14.7.
  - map/par behaviour changed, unfortunately unfavorably for w11a. 
    On Nexys3 no timing closure anymore for 80 MHz, only 72 MHz can 
    be achieved now.
- new man pages (in doc/man/man1/)
- support for Spartan-6 CMTs in PLL and DCM mode
This commit is contained in:
Walter F.J. Mueller
2014-05-29 21:30:01 +00:00
parent 200ba69364
commit 4732555297
152 changed files with 4141 additions and 592 deletions
Download Patch File Download Diff File Expand all files Collapse all files

3
Makefile
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@@ -1,4 +1,4 @@
# $Id: Makefile 513 2013-05-01 14:02:06Z mueller $
# $Id: Makefile 538 2013-10-06 17:21:25Z mueller $
#
# 'Meta Makefile' for whole retro project
# allows to make all synthesis targets
@@ -6,6 +6,7 @@
#
# Revision History:
# Date Rev Version Comment
# 2013-09-28 535 1.0.7 add nexys4 port for sys_gen/tst_sram,w11a
# 2013-05-01 513 1.0.6 add clean_sim_tmp and clean_syn_tmp targets
# 2012-12-29 466 1.0.5 add tst_rlink_cuff
# 2011-12-26 445 1.0.4 add tst_fx2loop

49
doc/INSTALL_ghdl.txt
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@@ -1,4 +1,4 @@
# $Id: INSTALL_ghdl.txt 467 2013-01-02 19:49:05Z mueller $
# $Id: INSTALL_ghdl.txt 537 2013-10-06 09:06:23Z mueller $
The w11 project uses the open source VHDL simulator
@@ -6,22 +6,49 @@ The w11 project uses the open source VHDL simulator
It used to be part of most distributions. Unfortunately the Debian maintainer
for ghdl refused at some point to integrate ghdl into Debian Etch. Therefore
ghdl is part of Debian Lenny, and again of Debian Squeeze (the current
'stable'). So for an up-to-date Debian simply install the ghdl package.
ghdl was part of Debian Lenny, and again of Debian Squeeze, and is missing
again in Debian Wheezy (the current 'stable').
The glitch at Debian unfortunately lead to the removal of ghdl from Ubuntu,
which is based on Debian. Ubuntu Lucid (10.04) and up to Oneiric (11.10)
included ghdl, the currently maintained versions Precise (12.04 LTS) and
Quantal (12.10) don't.
alter don't.
Thanks to Peter Gavin Ubuntu packages for GHDL are available from his PPA
'Personal Package Archives', see
To install ghdl on an up-to-date Debian or Ubuntu systems you have the
following options {as of early October 2013}:
https://launchpad.net/~pgavin/+archive/ghdl
- Ubuntu Precise, Quantal, and Raring
So to install ghdl under Ubuntu use
Thanks to Peter Gavin Ubuntu packages for GHDL are available from his PPA
'Personal Package Archives', see
sudo add-apt-repository ppa:pgavin/ghdl
sudo apt-get update
sudo apt-get install ghdl
https://launchpad.net/~pgavin/+archive/ghdl
So to install ghdl under Ubuntu use
sudo add-apt-repository ppa:pgavin/ghdl
sudo apt-get update
sudo apt-get install ghdl
- Debian Wheezy
Thanks to Joris van Rantwijk Debian packages for GHDL are available
from the web site
http://jorisvr.nl/ghdl_debian.html
There are also Ubuntu packages, but Joris focus is clearly on Debian.
Only Debian and Ubuntu are actively used by the w11a developer. The
situation for other linux distributions is therefore just taken from
the respective web sites:
- Suse
For Suse 12.2 and 12.3 un-official ghdl packages are available, but they
seem to be based on the long obsolete ghdl version 0.27.
- Redhat/Fedora
For Fedora 18,19, and 20 packages are available based on ghdl 0.29
- Gentoo
Packages, marked 'unstable', are available based on ghdl 0.29 and 0.27

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doc/README.txt
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# $Id: README.txt 518 2013-05-12 16:45:02Z mueller $
# $Id: README.txt 556 2014-05-29 19:01:39Z mueller $
Release notes for w11a
@@ -82,7 +82,57 @@ Release notes for w11a
3. Change Log ----------------------------------------------------------------
- trunk (2013-05-12: svn rev 21(oc) 518(wfjm); untagged w11a_V0.58) +++++++++
- trunk (2014-05-29: svn rev 22(oc) 556(wfjm); untagged w11a_V0.581) ++++++++
- summary
- new reference system
- Switched from ISE 13.3 to 14.7.
- map/par behaviour changed, unfortunately unfavorably for w11a.
On Nexys3 no timing closure anymore for 80 MHz, only 72 MHz can
be achieved now.
- new man pages (in doc/man/man1/)
- support for Spartan-6 CMTs in PLL and DCM mode
- New features
- new modules
- rtl/vlib/xlib
- s6_cmt_sfs_unisim - Spartan-6 CMT for simple frequency synthesis
- s6_cmt_sfs_gsim - dito, simple ghdl simulation model
- tools/src/librutiltpp
- RtclSignalAction - Tcl signal handler
- RtclSystem - Tcl Unix system interface
- new files
- tools/bin/create_disk - creates a disk container file
- tools/bin/xtwi - Xilinx Tool Wrapper script for ISE
- tools/tcl/rw11/defs.tcl - w11a definitions
- Changes
- rtl/make
- imp_*.opt - use -fastpaths, -u, -tsi for trce
- imp_s6_speed.opt - adopt for ISE 14.x
- generic_xflow.mk - use xtwi; trce tsi file; use -C for cpp
- generic_isim.mk - use xtwi
- generic_xflow_cpld.mk - use xtwi
- rtl/sys_gen/*/nexys3
- .../sys_*.vhd - pll support, use clksys_vcodivide ect
- rtl/sys_gen/w11a/nexys3
- sys_conf.vhd - use 72 MHz, no closure in ISE 14.x for 80
- rtl/bplib/nexys(2|3)
- nexys(2|3)_time_fx2_ic.ucf - add VALID for hold time check
- tools/src/librwxxtpp
- RtclRw11Cpu - cp command options modified
- tools/bin
- vbomconv - add --viv_vhdl (for Vivado)
- tools/tcl/rw11
- util.tcl - move definitions to defs.tcl
- Bug fixes
- tools/src/librtools/RlogFile - fix date print (month was off by one)
- tools/tcl/rw11/asm.tcl - asmwait checks now pc if stop: defined
- Other updates
- INSTALL_ghdl.txt - text reflects current situation on ghdl packages
- trunk (2013-05-12: svn rev 21(oc) 518+(wfjm); untagged w11a_V0.58) ++++++++
- Summary
- C++ and Tcl based backend server now fully functional, supports with

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.\" -*- nroff -*-
.\" $Id: asm-11_expect.1 550 2014-02-03 08:16:57Z mueller $
.\"
.\" Copyright 2014- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
.\"
.\" ------------------------------------------------------------------
.
.TH ASM-11_EXPECT 1 2013-03-30 "Retro Project" "Retro Project Manual"
.\" ------------------------------------------------------------------
.SH NAME
asm-11_expect \- expect checker for asm-11 test bench
.\" ------------------------------------------------------------------
.SH SYNOPSIS
.
.SY asm-11_expect
.RI [ OPTION ]...
.I FILE...
.
.SY asm-11_expect
.B \-\-help
.YS
.
.\" ------------------------------------------------------------------
.SH DESCRIPTION
Reads one of more \fBasm-11\fP(1) listing files and checks for unexpected
assembly errors and tests for expected address and generated data values.
What is expected is specified by comments, described in section EXPECT COMMENTS,
which are added to the asm-11 source code.
asm-11 will copy these comments to the listing file and asm-11_expect extracts
them and checks whether the actual assembly results match the expected ones.
.PP
asm-11_expect produces at least a one line summary per file like
.PP
.EX
asm-11_expect: test_0010_alloc.lst OK
asm-11_expect: test_0020_expr.lst OK
.EE
.PP
where each file is marked either \fBOK\fR or \fBFAILED\fR.
In case of detected errors additional output follows which gives a description
of each error and the affected listing line, like
.PP
.EX
asm-11_expect: test_0110_op_gg.lst FAILED
FAIL: data 1 mismatch: found=177736, expect=177734
in: 1 27 001042 067700 177736 add @pa,r0 ;;!! 067700 177734
.EE
.PP
Main application for asm-11_expect is to build self-checking test benches
for \fBasm-11\fP(1).
.
.
.\" ------------------------------------------------------------------
.SH EXPECT COMMENTS
The special comments which describe what to expect for an assembly line
have the format
.PP
.EX
;;!! [\fIetags\fP] [\fIaddr\fP:] [\fIdata\fP]...
.EE
.PP
with
.PP
.PD 0
.IP "\fBetags\fP"
list of expected assembly error flags, given as sequence of uppercase letters
without white space between letters.
.IP "\fBaddr\fP"
expected location counter (value of '.'), given as 6 digit octal number.
Note that all 6 digits must be specified, even leading zeros.
.IP "\fBdata\fP"
expected generated assembly output data, given as blank separated list
of either 3 (for byte output) or 6 (for word output) digit octal numbers.
Again, all 3 or 6 digits must be specified, even leading zeros.
This is checked against the data section of the assembly listing.
.br
In general this is used to check data emitted into the binary output.
However, some assembler statements, e.g. assignments or directives like .end,
indicate some result value in data section, and this can of course be
checked as well.
.PD
.PP
All three components are optional. Error flags are always tested, if no
\fIetags\fP are specified it is checked that no assembly error flag has
been generated for the line. Address and data tests are only done in case
\fIaddr\fP or \fIdata\fP components have been given.
.PP
If a line starts with an expect comment it will be applied to the asm-11
statement in the following line. Or it is simply appended to a asm-11
statement.
.SS Comment examples
.IP "\fB;;\-\- DM\fR" 4
expect a D and a M error flag
.IP "\fB;;\-\- 001020:\fR"
expect that current location will be 001020, data not checked
.IP "\fB;;\-\- 074167 177762\fR"
expect that the listing data section shows two words, 074167 and 177762.
Address is not checked.
.IP "\fB;;\-\- 001004: 000207\fR"
expect that current location will be 001004 and that the listing data section
shows one word with value 000207.
.SS Some practical cases
.EX
.word 65537. ;;!! T
sob r4,s4 ;;!! A
stkbot: .blkw 400 ;;!! 001000:
.word 100+77 ;;!! 000177
.byte 2+<4*10> ;;!! 042
spl 5 ;;!! 000235
inc @1234(r4) ;;!! 005274 001234
add @p,@#a ;;!! 067737 177614 001000
jsr pc,sub ;;!! 001006: 004767 177772
cmp = 1234 ;;!! 001234
c2 = inc + 67 ;;!! 005267
.end ;;!! 000001
.EE
.\" ------------------------------------------------------------------
.SH OPTIONS
.
.\" ----------------------------------------------
.IP "\fB\-\-tline\fR"
Prints input lines from listing file as they are processed. Helpful to
debug expect comments, e.g. in conjunction with the \fB-\-tcheck\fR
option.
.
.\" ----------------------------------------------
.IP "\fB\-\-tcheck\fR"
Prints for each detected expect comment in the listing file a line reflecting
the content of the comment, like
.EX
...line generated by \-\-tcheck ... | original expect comment
exp: err=T | ;;!! T
exp: dot=001000 | ;;!! 001000:
exp: dat=060037 001000 | ;;!! 060037 001000
exp: dot=001006 dat=004767 | ;;!! 001006: 004767
.EE
.
.\" ----------------------------------------------
.IP "\fB\-help\fR"
print full help text and exit.
.
.\" ------------------------------------------------------------------
.SH EXAMPLES
.IP "\fBasm-11_expect *.lst\fR" 4
Will check all listing files in current directory and produce a listing with
at least one summary line per file as described in section DESCRIPTION.
.\" ------------------------------------------------------------------
.SH "SEE ALSO"
.BR asm-11 (1)
.\" ------------------------------------------------------------------
.SH AUTHOR
Walter F.J. Mueller <W.F.J.Mueller@gsi.de>

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.\" -*- nroff -*-
.\" $Id: config_wrapper.1 550 2014-02-03 08:16:57Z mueller $
.\"
.\" Copyright 2013- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
.\"
.\" ------------------------------------------------------------------
.
.TH CONFIG_WRAPPER 1 2013-01-02 "Retro Project" "Retro Project Manual"
.\" ------------------------------------------------------------------
.SH NAME
config_wrapper \- configure FPGA via ISE impact or Linux jtag
.\" ------------------------------------------------------------------
.SH SYNOPSIS
.
.SY config_wrapper
.OP \-\-board=\fIb\fP
.OP \-\-path=\fIp\fP
.I COMMAND
.I FILE
.
.SY config_wrapper
.B \-\-help
.YS
.
.\" ------------------------------------------------------------------
.SH DESCRIPTION
Wrapper script to handle the configuration of an FPGA board with either
a XILINX JTAG programming cable and the ISE \fBimpact\fP program or with
an onboard Cypress FX2 USB controller and the \fBjtag\fP(1) program.
The \fICOMMAND\fP argument controls the action:
.RS 3
.PD 0
.IP \fBiconfigf\fP 10
configure using \fBimpact\fP with \fI.bit\fP file \fIFILE\fP
.IP \fBjconfigf\fP
configure using \fBjtag\fP(1) with \fI.svf\fP file \fIFILE\fP
.IP \fBbit2svf\fP
create a \fI.svf\fP file from the \fI.bit\fP file \fIFILE\fP
.PD
.
.\" ------------------------------------------------------------------
.SH OPTIONS
.
.\" ----------------------------------------------
.IP \fB\-\-board=\fIb\fR
determines the type of board to be configured. The default is 's3board',
currently supported boards are:
.RS
.RS 3
.PD 0
.IP \fBs3board\fP 10
Digilent S3BOARD. Default path: xc3s1000
.IP \fBnexys2\fP
Digilent Nexys2. Default path: xc3s1200e
.IP \fBnexys3\fP
Digilent Nexys3. Default path: xc6slx16
.IP \fBatlys\fP
Digilent Atlys. Default path: xc6slx45
.IP \fBsp605\fP
Xilinx SP605. Default path: xc6slx45t
.RE
.RE
.PD
.
.\" ----------------------------------------------
.IP \fB\-\-path=\fIp\fR
determines the type of FPGA to be configured. It usually properly defaulted
based on the \fB\-\-board\fP option. Only in cases were a board is available
with several die sizes this option will be needed.
.
.\" ----------------------------------------------
.IP \fB\-\-help\fP
print help text and exit.
.
.\" ------------------------------------------------------------------
.SH COMMANDS
.
.\" ----------------------------------------------
.IP \fBbit2svf\fP
Convert a FPGA configuration file from \fI.bit\fP format (the native XILINX
format) to \fI.svf\fP format (the portable Serial Vector Format). The
XILINX ISE \fBimpact\fP program is used, the input \fIFILE\fP must be in
\fI.bit\fP format.
.
.\" ----------------------------------------------
.IP \fBiconfig\fP
Configure a FPGA with XILINX ISE \fBimpact\fP. The input \fIFILE\fP must be in
\fI.bit\fP format.
.
.\" ----------------------------------------------
.IP \fBjconfig\fP
Configure a FPGA with \fBjtag\fP(1). The input \fIFILE\fP must be in
\fI.svf\fP format. This sub command is usually used for boards with a
Cypress FX2 USB controller, like the Digilent Nexys2, Nexys3 or Atlys,
and a FX2 firmware which emulates an Altera USB-Blaster programming cable.
The USB device path is defined by the environment variables RETRO_FX2_VID
and RETRO_FX2_PID, or defaults to vid=16c0 and pid=03ef.
Use the \fBfx2load_wrapper\fP(1) command to ensure that the proper firmware
is loaded in the Cypress FX2 USB controller.
The \fBbit2svf\fP sub command can be used to create a \fI.svf\fP from
a \fI.bit\fP file.
.
.\" ------------------------------------------------------------------
.SH EXIT STATUS
In case of an error an exit status 1 is returned.
.
.\" ------------------------------------------------------------------
.SH ENVIRONMENT
.IP "\fBRETRO_FX2_VID, RETRO_FX2_PID\fR" 4
Used by the \fBjconfig\fP sub command to define the USB path of the
Cypress FX2 USB controller emulating an Altera USB-Blaster cable.
.IP \fBXILINX\fR
Path to current XILINX ISE installation. Required by all sub commands,
mainly to locate the \fI.bsdl\fP files which describe the JTAG commands
of all devices in the JTAG chain.
.
.\" ------------------------------------------------------------------
.SH EXAMPLES
.IP "\fBconfig_wrapper bit2svf test.bit\fR" 4
Creates \fItest.svf\fP from \fItest.bit\fP.
.
.IP "\fBconfig_wrapper --board=nexys2 iconfig test.bit\fR"
Configures a Nexys2 board with \fItest.bit\fP using ISE \fBimpact\fP.
.
.IP "\fBconfig_wrapper --board=nexys3 jconfig test.svf\fR"
Configures a Nexys3 board with \fItest.svf\fP using \fBjtag\fP(1).
.
.\" ------------------------------------------------------------------
.SH "SEE ALSO"
.BR jtag (1),
.BR fx2load_wrapper (1)
.\" ------------------------------------------------------------------
.SH AUTHOR
Walter F.J. Mueller <W.F.J.Mueller@gsi.de>

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.\" -*- nroff -*-
.\" $Id: create_disk.1 550 2014-02-03 08:16:57Z mueller $
.\"
.\" Copyright 2013- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
.\"
.\" ------------------------------------------------------------------
.
.TH CREATE_DISK 1 2013-05-20 "Retro Project" "Retro Project Manual"
.\" ------------------------------------------------------------------
.SH NAME
create_disk \- create disk container file for ti_w11
.\" ------------------------------------------------------------------
.SH SYNOPSIS
.
.SY create_disk
.BI \-\-typ "\fR=\fPtyp"
.OP \-\-ini=\fIpat\fP
.OP \-\-bad
.OP \-\-boot
.I FILE
.
.SY create_disk
.B \-\-help
.YS
.
.\" ------------------------------------------------------------------
.SH DESCRIPTION
Creates a disk container file \fIFILE\fP with the proper size for a disk of
type \fItyp\fP.
.
.\" ------------------------------------------------------------------
.SH OPTIONS
.
.\" ----------------------------------------------
.IP \fB\-\-typ=\fItyp\fR
determines disk type, must be specified.
The list of supported disk types can be obtained with the
.B \-\-help
option.
.
.\" ----------------------------------------------
.IP \fB\-\-ini=\fIpat\fR
determines whether the container file will be initialized with specific
data pattern. Note that the \fB\-\-bad\fP and \fB\-\-boot\fP options will
overwrite the last track or the first sector(s) respectively.
Allowed values for \fIpat\fP are
.RS
.IP \fBzero\fP
creates a disk with all sectors zero'ed. This is the default when no
\fB\-\-ini\fP option is given.
.IP \fBones\fP
creates a disk with all data bytes set to 0xff.
.IP \fBdead\fP
creates a disk with an alternating 0xdead 0xbeaf pattern. Can be helpful
to diagnose whether an operating system access previously in initialized
parts of a disk.
.IP \fBtest\fP
creates a disk with a unique test pattern in each sector. The whole disk
is initialized with groups of 8 16bit words (in PDP-11 little endian) with
.RS
.RS 3
.PD 0
.IP 0: 4
absolute disk byte address, lower word
.IP 1: 4
absolute disk byte address, upper word
.IP 2: 4
current cyclinder number (0 based)
.IP 3: 4
current track/head number (0 based)
.IP 4: 4
current sector number (0 based)
.IP 5: 4
number of cyclinders for disk type
.IP 6: 4
number of tracks/heads for disk type
.IP 7: 4
number of sectors for disk type
.RE
.PD
.PP
A \fBhexdump\fP(1) of a RP06 disk image initialized with
\fB\-\-ini\fP=\fItest\fP
will look like
.EX
0000000 0000 0000 0000 0000 0000 032f 0013 0016
0000010 0010 0000 0000 0000 0000 032f 0013 0016
...
00001f0 01f0 0000 0000 0000 0000 032f 0013 0016
0000200 0200 0000 0000 0000 0001 032f 0013 0016
...
a657be0 7be0 0a65 032e 0012 0015 032f 0013 0016
a657bf0 7bf0 0a65 032e 0012 0015 032f 0013 0016
.EE
.
.RE
.RE
.
.\" ----------------------------------------------
.IP \fB\-\-bad\fP
creates a DEC standard 044 compliant bad block table on the last track
of the disk container file.
.
.\" ----------------------------------------------
.IP \fB\-\-boot\fP
creates a PDP-11 dummy boot block. When such a disk is attached and booted
with \fBti_w11\fP(1) or a simh pdp11 a message like
.EX
++======================================++
|| This is not a hardware bootable disk ||
++======================================++
Disk image created with 'create_disk --typ=RK05':
number of cylinders: 203
tracks per cylinder: 2
sectors per track: 12
block size: 512
total number of sectors: 4872
capacity in kByte: 2436
CPU WILL HALT
.EE
will be printed on the system console and the CPU HALTed.
.
.\" ----------------------------------------------
.IP \fB\-\-help\fP
print full help, with list \fB\-\-typ\fP and \fB\-\-ini\fP options.
.
.\" ------------------------------------------------------------------
.SH EXIT STATUS
If the file
.I FILE
can not be created an exit status 1 is returned.
.\" ------------------------------------------------------------------
.SH EXAMPLES
.IP "\fBcreate_disk -typ=rk05 rk05.dsk\fR" 4
This will create a zero'ed disk contained sized for a RK05 disk. In most
cases it is sufficient to create such plain zero'ed disk images.
.
.IP "\fBcreate_disk -typ=rl02 -bad rl02.dsk\fR"
Creates a RL02 sized disk with a 'factory bad block table'. When using
RLxx, RPxx, or RMxx type disks, especially in conjunction with DEC
operating systems, it is advisable to create disks with \fB\-\-bad\fP.
.
.IP "\fBcreate_disk -typ=rk05 -ini=test rk05_test.dsk\fR"
Creates a RK05 sized disk with test pattern.
.
.\" ------------------------------------------------------------------
.SH "SEE ALSO"
.BR ti_w11 (1)
.\" ------------------------------------------------------------------
.SH AUTHOR
Walter F.J. Mueller <W.F.J.Mueller@gsi.de>

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.\" -*- nroff -*-
.\" $Id: fx2load_wrapper.1 550 2014-02-03 08:16:57Z mueller $
.\"
.\" Copyright 2013- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
.\"
.\" ------------------------------------------------------------------
.
.TH FX2LOAD_WRAPPER 1 2013-01-05 "Retro Project" "Retro Project Manual"
.\" ------------------------------------------------------------------
.SH NAME
fx2load_wrapper \- auto-load firmware into Cypress FX2 USB controller
.\" ------------------------------------------------------------------
.SH SYNOPSIS
.
.SY fx2load_wrapper
.OP \-\-board=\fIb\fP
.OP \-\-file=\fIf\fP
.OP \-\-ihx_path=\fIp\fP
.OP \-\-cycfx2prog
.OP \-\-force
.OP \-\-dry_run
.
.SY fx2load_wrapper
.B \-\-help
.YS
.
.\" ------------------------------------------------------------------
.SH DESCRIPTION
Checks firmware state of a Cypress FX2 USB controller and re-loads the
firmware in case of a mismatch of currently active and desired firmware.
The command locates a USB device with a USB path defined by the environment
variables RETRO_FX2_VID and RETRO_FX2_PID, or default vid=16c0 and pid=03ef.
It inquires with \fBlsusb\fP(1) the 'iProduct' attribute of the currently
active USB descriptor. If this attribute is defined and equals the basename
of the firmware image given with \fB-\-file\fP it is assumed the the proper
firmware is already active. Otherwise the firmware image is loaded with
either \fBfxload\fP(1) or \fBcycfx2prog\fP.
\fBNote:\fP after a firmware load the Cypress FX2 USB controller restarts.
This causes a USB re-numeratation, the USB device disconnects and reconnects
with a new device descriptor. It can take some time till the Linux USB stack
shows the new device descriptor. The command sleeps for 1.5 seconds, this is
usually enough to ensure that subsequent commands see the new state.
.
.\" ------------------------------------------------------------------
.SH OPTIONS
.
.\" ----------------------------------------------
.IP \fB\-\-board=\fIb\fR
determines the type of board to be configured. The default is 'nexys2',
currently supported boards are:
.RS
.PD 0
.IP \fBnexys2\fP
Digilent Nexys2. Default file: nexys2_jtag_2fifo_as.ihx
.IP \fBnexys3\fP
Digilent Nexys3. Default file: nexys3_jtag_2fifo_as.ihx
.IP \fBatlys\fP
Digilent Atlys. Default file: nexys3_jtag_2fifo_as.ihx
.RE
.PD
.
.\" ----------------------------------------------
.IP \fB\-\-file=\fIf\fR
specifies the firmware image to be loaded. Must be in \fI.ihx\fP format
and located in the path defined with the \fB\-\-ihx_path\fP option.
.
.\" ----------------------------------------------
.IP \fB\-\-ihx_path=\fIp\fR
specifies the directory were firmware image files are searched. The default
is \fI$RETROBASE/tools/fx2/bin\fP.
.
.\" ----------------------------------------------
.IP \fB\-\-cycfx2prog\fP
Use \fBcycfx2prog\fP instead of \fBfxload\fP(1) to load the firmware.
.
.\" ----------------------------------------------
.IP \fB\-\-force\fP
Unconditionally load the firmware, even when a 'iProduct' attribute match
is seen. Useful to reset the Cypress FX2 controller.
.
.\" ----------------------------------------------
.IP \fB\-\-dry_run\fP
Don't load the firmware, display only the command used to do so.
.
.\" ----------------------------------------------
.IP \fB\-\-help\fP
print help text and exit.
.
.\" ------------------------------------------------------------------
.SH EXIT STATUS
In case of an error an exit status 1 is returned.
.
.\" ------------------------------------------------------------------
.SH ENVIRONMENT
.IP "\fBRETRO_FX2_VID, RETRO_FX2_PID\fR" 4
Define the USB path of the Cypress FX2 USB controller. If not specified
the defaults vid=16c0 and pid=03ef are used.
.IP \fBRETROBASE\fR
Path to current Retro project root directory. Used for the default
firmware path in case no \fB\-\-ihx_path\fP option given.
.
.\" ------------------------------------------------------------------
.SH EXAMPLES
.IP "\fBfx2load_wrapper --board=nexys2 --file=nexys2_jtag_2fifo_ic.ihx\fR" 4
Checks whether the 'nexys2_jtag_2fifo_ic' version of the firmware is loaded
and in case not loads the firmware image.
.\" ------------------------------------------------------------------
.SH "SEE ALSO"
.BR fxload (1),
.BR config_wrapper (1)
.\" ------------------------------------------------------------------
.SH AUTHOR
Walter F.J. Mueller <W.F.J.Mueller@gsi.de>

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.\" -*- nroff -*-
.\" $Id: isemsg_filter.1 550 2014-02-03 08:16:57Z mueller $
.\"
.\" Copyright 2014- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
.\"
.\" ------------------------------------------------------------------
.TH ISEMSG_FILTER 1 2014-01-02 "Retro Project" "Retro Project Manual"
.\" ------------------------------------------------------------------
.SH NAME
isemsg_filter \- message filter for Xilinx ISE tool chain log files
.\" ------------------------------------------------------------------
.SH SYNOPSIS
.
.SY isemsg_filter
.OP \-\-pack
.I TYPE
.I MFSET
.I LOGFILE
.
.SY isemsg_filter
.B \-\-help
.YS
.
.\" ------------------------------------------------------------------
.SH DESCRIPTION
.\" ----------------------------------------------
Scans the log file \fILOGFILE\fP generated by Xilinx ISE tool specified
by \fITYPE\fP for informational, warning and error messages and compares
these messages against a set of message filter rules defined in the
\fIMFSET\fP file.
isemsg_filter will print all no-matching messages.
All filter rules which do not match a message are also listed, these
messages are considered missing.
Matched messages are considered accepted.
In normal operation they will not create output.
isemsg_filter is useful for example in \fBmake\fP(1) based flows to
create a short summary from the log files.
The accepted values for \fITYPE\fP are:
.RS 3
.PD 0
.IP \fBxst\fP 6
ISE xst
.IP \fBtra\fP
ISE ngdbuild (translate)
.IP \fBmap\fP
ISE map
.IP \fBpar\fP
ISE par
.IP \fBtwr\fP
ISE trce
.IP \fBbgn\fP
ISE bitgen
.PD
.RE
.
.\" ------------------------------------------------------------------
.SH OPTIONS
.\" ----------------------------------------------
.IP \fB\-\-pacc\fP
Print a summary of all accepted messages. The match count for each rule is
listed.
.
.\" ----------------------------------------------
.IP \fB\-\-help\fP
print full help.
.
.\" ------------------------------------------------------------------
.SH MESSAGE FILTER FILE FORMAT
.\" ----------------------------------------------
Simply a list of regular expression patters structured by section headers
of the form "[TYPE]".
Blank lines and lines starting with '#' will be ignored.
isemsg_filter will extract the patters of the section matching the
\fITYPE\fP argument.
.SS Example message filter file
.EX
# ---------
[xst]
INFO:.*The FF/Latch <.*> is equivalent to .* will be removed
Node <HIO/IOB_BTN/R_DI_[1-4]> of sequential type is unconnected
# ---------
[map]
INFO:.*The FF/Latch <.*>.*is equivalent to the following FF/Latch
.EE
.\" ------------------------------------------------------------------
.SH EXIT STATUS
If \fITYPE\fP is invalid or the \fIMFSET\fP or \fILOGFILE\fP files
can't be opend an exit status 1 is returned.
.\" ------------------------------------------------------------------
.SH EXAMPLES
.IP "\fBisemsg_filter xst proj.mfset proj_xst.log\fR" 4
Generate a short summary of a ISE xst log file.
.
.\" ------------------------------------------------------------------
.SH "BUGS"
The \fIMFSET\fP file is flat, no structuring possible, e.g. with includes.
It be great to have for example default rules for each target device.
Since ISE is 'end-of-life' no further work on isemsg_filter will be done.
.
.\" ------------------------------------------------------------------
.SH "SEE ALSO"
.
.\" ------------------------------------------------------------------
.SH AUTHOR
Walter F.J. Mueller <W.F.J.Mueller@gsi.de>

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@@ -1,11 +1,11 @@
.\" -*- nroff -*-
.\" $Id: set_ftdi_lat.1 321 2010-08-01 19:43:39Z mueller $
.\" $Id: set_ftdi_lat.1 547 2013-12-29 13:10:07Z mueller $
.\"
.\" Copyright 2010- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
.\" Copyright 2010-2013 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
.\"
.\" ------------------------------------------------------------------
.
.TH SET_FTDI_LAT 1 2010-07-24 "Retro Project" "Retro Project Manual"
.TH SET_FTDI_LAT 1 2013-12-26 "Retro Project" "Retro Project Manual"
.\" ------------------------------------------------------------------
.SH NAME
set_ftdi_lat \- set latency timer in FTDI USB UART or FIFO
@@ -19,51 +19,48 @@ set_ftdi_lat \- set latency timer in FTDI USB UART or FIFO
.
.\" ------------------------------------------------------------------
.SH DESCRIPTION
\fBNote:\fP command is obsolete when kernel 2.6.32 or newer is used.
See NOTES section.
.
.PP
FTDI USB UART or FIFO adapters of type FT232, FT245, and other similar
models have a latency timer which controls the maximal time between reception
of a byte by the UART or FIFO and the emission of a USB frame. The default
is 16 msec and can lead to unsatisfactory response times.
is 16 msec on kernels prior to 2.6.32 and can lead to unsatisfactory
response times.
The
.B set_ftdi_lat
script allows to set this latency timer via a node in the
.I /sys
script allows to set this latency timer via a node in the \fI/sys\fP
virtual file system, specifically
.IP "" 4
.I /sys/bus/usb-serial/devices/ttyUSBn/latency_timer
.
.PP
The first optional argument
.I dev
allows to specify the device name in the form
.I USBn
with the default
.IR USB0 .
The second optional argument
.I
time
allows to specify the new value of the latency timer, given in msec.
Default is 1 msec.
.
The first optional argument \fIdev\fP allows to specify the device name
in the form \fIUSBn\fP with the default \fIUSB0\fP. The second optional
argument \fItime\fP allows to specify the new value of the latency timer,
given in msec. Default is 1 msec.
.
.\" ------------------------------------------------------------------
.SH EXIT STATUS
If device
.RI tty dev
is not found or the entry in
.I /sys
is not writable an exit status 1 is returned.
If device tty\fIdev\fP is not found or the entry in \fI/sys\fP is not
writable an exit status 1 is returned.
.\" ------------------------------------------------------------------
.SH EXAMPLES
In general the command is given via
.BR sudo ,
like
In general the command is given via \fBsudo\fP(8) like
.EX
sudo set_ftdi_lat USB0 1
.EE
.\" ------------------------------------------------------------------
.SH "SEE ALSO"
.BR sudo (1)
.BR sudo (8)
.
.\" ------------------------------------------------------------------
.SH NOTES
For linux kernel 2.6.32 or newer the default is 1 ms already. On all
up-to-date systems therefore no need to use this command.
.
.\" ------------------------------------------------------------------
.SH AUTHOR

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.\" -*- nroff -*-
.\" $Id: svn_set_ignore.1 550 2014-02-03 08:16:57Z mueller $
.\"
.\" Copyright 2013- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
.\"
.\" ------------------------------------------------------------------
.
.TH SVN_SET_IGNORE 1 2010-04-26 "Retro Project" "Retro Project Manual"
.\" ------------------------------------------------------------------
.SH NAME
svn_set_ignore \- setup svn:ignore properties based on .cvsignore files
.\" ------------------------------------------------------------------
.SH SYNOPSIS
.
.SY svn_set_ignore
.OP \-\-dry-run
.YS
.
.\" ------------------------------------------------------------------
.SH DESCRIPTION
Creates or updates a \fIsvn:ignore\fP property for the current directory
and all sub-directories. The current directory must contain a
\fI.cvsignore\fP file which defines the default list of ignore patterns for the
whole project. If a local \fI.cvsignore\fP file is found in a sub directory
its content will be appended to the default list.
.
If no \fIsvn:ignore\fP property exists or the existing one differs from
the ignore pattern list determined from the top level and local
\f.cvsignore\fP file the property is set or updated.
.
.\" ------------------------------------------------------------------
.SH OPTIONS
.
.\" ----------------------------------------------
.IP \fB\-\-dry-run\fP
Shows \fIsvn:ignore\fP property changes, but doesn't store them in the
svn repository.
.
.\" ------------------------------------------------------------------
.SH EXIT STATUS
If no \fI.cvsignore\fP file is found or a \fBsvn\fP(1) command fails the
script dies with exit status 2.
.
.\" ------------------------------------------------------------------
.SH "SEE ALSO"
.BR svn (1)
.\" ------------------------------------------------------------------
.SH AUTHOR
Walter F.J. Mueller <W.F.J.Mueller@gsi.de>

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.\" -*- nroff -*-
.\" $Id: tbw.1 550 2014-02-03 08:16:57Z mueller $
.\"
.\" Copyright 2013- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
.\"
.\" ------------------------------------------------------------------
.
.TH TBW 1 2011-11-06 "Retro Project" "Retro Project Manual"
.\" ------------------------------------------------------------------
.SH NAME
tbw \- wrapper script to start ghdl based VHDL test benches
.\" ------------------------------------------------------------------
.SH SYNOPSIS
.
.SY tbw
.I TBPROG
.RI [ FILEDEF ]...
.RI [ GHDL-OPTIONS ]...
.
.SY tbw
.B \-\-help
.YS
.
.\" ------------------------------------------------------------------
.SH DESCRIPTION
Executes the \fBghdl\fP based test bench \fITBPROG\fP in an environment
defined by the descriptor file \fItbw.dat\fP and the \fIFILEDEF\fP
arguments. Any additional options \fIGHDL-OPTIONS\fP are passed on to the test
bench executable.
.SS Backgroud
The VHDL implementation in \fBghdl\fP has no direct support for passing
command line arguments to the VHDL code. All test benches in the Retro
project use therefore fixed build-in generic file names. By convention
they refer to symlinks (see \fBsymlink\fP(7)) which are setup by
\fBtbw\fP to point to a specific file prior to the execution of the
test bench.
.SS Default behaviour
In the simplest case \fBtbw\fP assumes a test bench with a single stimulus
file which is opened by convention as \'<TBPROG>_stim\'. The default
stimulus file is named \'<TBPROG>_stim.dat\'. \fBtbw\fP will simply
define \'<TBPROG>_stim\' as a symlink refering to \'<TBPROG>_stim.dat\',
or if defined to \fIFILEDEF\fP, and execute \fITBPROG\fP. In essence
.EX
ln -s -f <TBPROG>_stim.dat <TBPROG>_stim
<TBPROG> <GHDL-OPTIONS>
.EE
.
.SS Using a \fItbw.dat\fP configuration file
When the generic file name or the stimulus file name does not follow the
simple default pattern or more than one input file is required a
configuration file can be used to define the setup. It has the fixed
name \fItbw.dat\fP and is searched the current working directory. The
format is described in section FILES.
In this case the \fIFILEDEF\fP argument can be specified as 'tag=value'
pairs where tag refers to a generic name and value gives the concrete
file name. Useful when several input files are to be specified.
.
.SS Test benches controlled with \fBti_rri\fP
In this case the communication between test bench and the controlling
\fBti_rri\fP is done via two named pipes (see \fBfifo\fP(7)). The test
bench might open in addition a configuration file. This setup is also
defined via the \fItbw.dat\fP file, for details see section FILES.
.
.\" ------------------------------------------------------------------
.SH GHDL OPTIONS
All options are passed on to the test bench executable. The list of
available options for a \fBghdl\fP generated executable can be inquired
with the "\fB\-\-help\fR" option. Some especially useful options are:
.
.\" ----------------------------------------------
.IP "\fB\-\-wave=\fIfile\fR"
dump signal values into a wave file (use file type .ghw). Far superior
to the VCD format and allows to inspect all VHDL records and all data types
with \fBgtkwave\fP(1).
.
.\" ----------------------------------------------
.IP "\fB\-\-stack-max-size\fP=\fIn\fR"
set maximum stack size. Very helpful in case of very large models. A value
of \fIn\fP=16384 is in general enough for all generated models, which usually
have a large number of very simple processes.
.
.\" ----------------------------------------------
.IP "\fB\-\-stop-time\fI=t\fR"
stop the simulation at time \fIt\fP (in VHDL notation, e.g. 100ns).
.
.\" ----------------------------------------------
.IP "\fB\-\-disp-time\fR"
display time as simulation advances.
.
.\" ----------------------------------------------
.IP "\fB\-\-trace-processes\fR"
display process name before each cycle.
.
.\" ------------------------------------------------------------------
.SH FILES
.IP "\fI./tbw.dat\fR" 4
This configuration file is searched for in the current working directory
and holds associations between generic file names and concrete file names
for one or more test bench executables. It contains sections of the format
.EX
[\fITBPROG\fP]
<generic name 1> = <concrete file name 1>
<generic name 2> = <concrete file name 2>
...
.EE
.RS
.IP "\fBUsage with Stimulus file based test benches\fR" 4
\fBtbw\fP will create a \fBsymlink\fP(7) with the generic name which
refers to the given concrete file name. A typical example is
.EX
[tb_nx_cram_memctl_as]
tb_nx_cram_memctl_stim = tb_nx_cram_memctl_stim.dat
.EE
.IP "\fBUsage with test benches controlled with ti_rri\fR"
The special token \fI<fifo>\fP indicates that a named pipe is used
rather than a normal file. In this case \fBtbw\fP will create a
\fBfifo\fP(7) rather than a symlink. Another special token is
\fI<null>\fP, it simply translates to \fI/dev/null\fP and can be
used as default value for configuration files. Currently all
\fBrlink\fP based test benches use the same generic names and have
a setup like
.EX
[tb_w11a_n3]
rlink_cext_fifo_rx = <fifo>
rlink_cext_fifo_tx = <fifo>
rlink_cext_conf = <null>
.EE
.RE
.
.\" ------------------------------------------------------------------
.SH EXAMPLES
.SS Stimulus file based test benches
Test benches are usually self-checking and produce a comprehensive log file.
For each checked response the line contains the word \fICHECK\fP and either
an \fIOK\fP or a \fIFAIL\fP, in the later case in general with an indication
of whats wrong.
Other unexpected behaviour, like timeouts, will also result in a line
containing the word \fIFAIL\fP.
When the simulation stops a line with the word \fIDONE\fP is printed.
These test benches are usually run like
.EX
tbw <testbenchname> [stimfile] | tee <logfile> | egrep "(FAIL|DONE)"
.EE
where
.RS 2
.PD 0
.IP "\-" 2
\fBtbw\fP sets up the stimulus file and runs the test bench executable
.IP "\-"
\fBtee\fP ensures that the full log is saved
.IP "\-"
\fBegrep\fP filters \fIFAIL\fP and \fIDONE\fP lines, a successful run will
produce a single \fIDONE\fP line
.PD
.RE
.SS Test benches controlled with \fBti_rri\fP
In these cases the test bench is started via \fBti_rri\fP using the
\fB\-\-run\fP and \fB\-\-fifo\fP options. Also here Usually a pipe with
\fBtee\fP and \fBegrep\fP is used, a typical example is
.EX
ti_rri \-\-run="tbw tb_tst_rlink_n3" \-\-fifo \-\-logl=3 \-\- \\
"package require tst_rlink" \\
"tst_rlink::setup" "tst_rlink::test_all" |\\
tee tb_tst_rlink_n3_dsim.log |\\
egrep "(\-[EFW]:|FAIL|PEND|DONE)"
.EE
.
.\" ------------------------------------------------------------------
.SH "SEE ALSO"
.BR ti_rri (1),
.BR gtkwave (1),
.BR symlink (7),
.BR fifo (7)
.\" ------------------------------------------------------------------
.SH AUTHOR
Walter F.J. Mueller <W.F.J.Mueller@gsi.de>

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.\" -*- nroff -*-
.\" $Id: telnet_starter.1 550 2014-02-03 08:16:57Z mueller $
.\"
.\" Copyright 2013- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
.\"
.\" ------------------------------------------------------------------
.
.TH TELNET_STARTER 1 2010-07-09 "Retro Project" "Retro Project Manual"
.\" ------------------------------------------------------------------
.SH NAME
telnet_starter \- setup vt52/vt100 emulator windows for ti_rri or simh
.\" ------------------------------------------------------------------
.SH SYNOPSIS
.
.SY telnet_starter
.OP \-t term
.OP \-d dev
.OP \-s
.OP \-w
.OP \-l
.
.SY telnet_starter
.B \-\-h
.YS
.
.\" ------------------------------------------------------------------
.SH DESCRIPTION
Script to setup a \fBxterm\fP vt52 or vt100 emulator window which
will connect to a DL11 or DZ11 serial interface emulation port of
\fBti_rri\fP or a CPU emulator from the \fBsimh\fP suite,
e.g. \fBpdp11\fP, via a \fBtelnet\fP connection.
If the connect to the interface emulation port fails or is terminated
a message like
.EX
localhost 8000
Trying 127.0.0.1...
telnet: Unable to connect to remote host: Connection refused
telnet failed with rc=256
enter q or <^D> to quit, otherwise hit <ENTER> to reconnect:
.EE
is displayed in the \fBxterm\fP window. Entering a 'q' or 'Control-D'
will terminate the \fBxterm\fP window, after pressing the '<ENTER>'
key a re-connect will be tried.
.
.\" ------------------------------------------------------------------
.SH OPTIONS
.
.\" ----------------------------------------------
.IP "\fB\-t \fIterm\fR"
defines the terminal emulator type. Allowed values are:
.RS
.RS 3
.PD 0
.IP \fBvt100\fP 8
use VT100 emulation. The default.
.IP \fBvt52\fP
use VT52 emulation. Useful in conjunction with OS which do not have VT100
support, like early DEC RSX-11M versions.
.RE
.RE
.PD
.
.\" ----------------------------------------------
.IP "\fB\-d \fIdev\fR"
defines the serial interface emulation port to connect to. Supported
are currently primary and secondary DL11 interface and eight lines of
the first DZ11 interface. Allowed values for \fIdev\fP are:
.RS
.RS 3
.PD 0
.IP \fBDL0\fP 6
first DL11 (usually console). The default.
.IP \fBDL1\fP 6
second DL11.
.IP \fBDZ\fIn\fP 6
eight lines of the first DZ11. \fIn\fP = 0,...,7.
.RE
.RE
.PD
.
.\" ----------------------------------------------
.IP "\fB\-s\fR"
Use simh port numbers. Default is to use \fBti_rri\fP ports.
.
.\" ----------------------------------------------
.IP "\fB\-w\fR"
Use a wide 132 column screen. Default is 80 column screen width.
.
.\" ----------------------------------------------
.IP "\fB\-l\fR"
Use a long 48 line screen. Default is a 24 lines screen height.
.
.\" ----------------------------------------------
.IP "\fB\-h\fR"
print full help text and exit.
.
.
.\" ------------------------------------------------------------------
.SH EXIT STATUS
In case of an error an exit status 1 is returned.
.
.\" ------------------------------------------------------------------
.SH BUGS
Stupid name, it's not telnet but a terminal emulator which is started.
.
.\" ------------------------------------------------------------------
.SH EXAMPLES
.IP "\fBtelnet_starter -d DL0 &\fR" 4
Creates a background process with a \fBxterm\fP in VT100 emulation mode
with a 80x24 screen size which will try to connect to the primary DL11
emulator port of \fBti_rri\fP.
.
.IP "\fBtelnet_starter -t vt52 -d DL1 -s &\fR"
Creates a background process with a \fBxterm\fP in VT52 emulation mode
with a 80x24 screen size which will try to connect to the secondary DL11
emulator port of a \fBsimh\fP suite CPU emulator.
.
.\" ------------------------------------------------------------------
.SH "SEE ALSO"
.BR telnet (1),
.BR ti_rri (1),
.BR xterm (1)
.\" ------------------------------------------------------------------
.SH AUTHOR
Walter F.J. Mueller <W.F.J.Mueller@gsi.de>

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.\" -*- nroff -*-
.\" $Id: xilinx_ghdl_simprim.1 522 2013-05-24 17:50:29Z mueller $
.\"
.\" Copyright 2010- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
.\"
.\" ------------------------------------------------------------------
.
.TH XILINX_GHDL_SIMPRIM 1 2010-07-25 "Retro Project" "Retro Project Manual"
.\" ------------------------------------------------------------------
.SH NAME
xilinx_ghdl_simprim \- compile Xilinx ISE SIMPRIM libraries for ghdl
.\" ------------------------------------------------------------------
.SH SYNOPSIS
.
.B xilinx_ghdl_simprim
.
.\" ------------------------------------------------------------------
.SH DESCRIPTION
\fBxilinx_ghdl_simprim\fP compiles the Xilinx ISE/WebPack SIMPRIM libraries
for \fBghdl\fP.
The object files generated by \fBghdl\fP are stored in the directory
tree of the currently active version of ISE/WebPack under
\fI$XILINX/ghdl/simprim\fP.
This is convenient when several ISE/WebPack versions are installed in
parallel, the \fB$XILINX\fP
environment variable is enough to setup the context for the synthesis
flows as well as for build of \fBghdl\fP models. Just use the \fBghdl\fP
option
.EX
-P${XILINX}/ghdl/simprim
.EE
to link to the SIMPRIM library.
Up to ISE 10 the VITAL models were all concatinated in one large file
\fIsimprim_VITAL.vhd\fP.
In this case the \fBxilinx_vhdl_chop\fP
helper script will create individual source files for each model.
For ISE 11 and later the modules are shipped as separate files.
The XILINX source code has since many releases some buggy statements with
self-referencial initializations. They seem to be tolerated by the commercial
tools but not by \fBghdl\fP.
The \fBxilinx_vhdl_memcolltype_fix\fP
helper script simply removes them, no further problems seen so far.
.\" ------------------------------------------------------------------
.SH ENVIRONMENT VARIABLES
.TP
.B XILINX
points to the root of the currently active ISE/WebPack installation.
.
.\" ------------------------------------------------------------------
.SH FILES
.IP \fI$XILINX/vhdl/src/simprims\fP
The vhdl sources for the SIMPRIM library are looked for in this directory tree.
.IP \fI$XILINX/ghdl/simprim\fP
The created object files will be written into this directory. The directory
is created if not yet existing. Note that the \fI$XILINX\fP
directory must be writable for the script.
.
.\" ------------------------------------------------------------------
.SH "SEE ALSO"
.BR ghdl (1),
.BR xilinx_ghdl_unisim (1)
.
.\" ------------------------------------------------------------------
.SH AUTHOR
Walter F.J. Mueller <W.F.J.Mueller@gsi.de>

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.\" -*- nroff -*-
.\" $Id: xilinx_ghdl_unisim.1 522 2013-05-24 17:50:29Z mueller $
.\"
.\" Copyright 2010- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
.\"
.\" ------------------------------------------------------------------
.
.TH XILINX_GHDL_UNISIM 1 2010-07-25 "Retro Project" "Retro Project Manual"
.\" ------------------------------------------------------------------
.SH NAME
xilinx_ghdl_unisim \- compile Xilinx ISE UNISIM libraries for ghdl
.\" ------------------------------------------------------------------
.SH SYNOPSIS
.
.B xilinx_ghdl_unisim
.
.\" ------------------------------------------------------------------
.SH DESCRIPTION
\fBxilinx_ghdl_unisim\fP compiles the Xilinx ISE/WebPack UNISIM libraries for
\fBghdl\fP. The object files generated by \fBghdl\fP
are stored in the directory tree of the currently active version of
ISE/WebPack under \fI$XILINX/ghdl/unisim\fP.
This is convenient when several ISE/WebPack versions are installed in
parallel, the \fB$XILINX\fP
environment variable is enough to setup the context for the synthesis
flows as well as for build of \fBghdl\fP models. Just use the
\fBghdl\fP option
.EX
-P${XILINX}/ghdl/unisim
.EE
to link to the UNISIM library.
Up to ISE 10 the VITAL models were all concatinated in one large file
\fIunisim_VITAL.vhd\fP. In this case the \fBxilinx_vhdl_chop\fP
helper script will create individual source files for each model.
For ISE 11 and later the modules are shipped as separate files.
The XILINX source code has since many releases some buggy statements with
self-referencial initializations. They seem to be tolerated by the commercial
tools but not by \fBghdl\fP.
The \fBxilinx_vhdl_memcolltype_fix\fP
helper script simply removes them, no further problems seen so far.
.\" ------------------------------------------------------------------
.SH ENVIRONMENT VARIABLES
.IP \fBXILINX\fP
points to the root of the currently active ISE/WebPack installation.
.
.\" ------------------------------------------------------------------
.SH FILES
.IP \fI$XILINX/vhdl/src/unisims\fP
The vhdl sources for the UNISIM library are looked for in this directory tree.
.IP \fI$XILINX/ghdl/unisim\fP
The created object files will be written into this directory. The directory
is created if not yet existing. Note that the \fI$XILINX\fP
directory must be writable for the script.
.
.\" ------------------------------------------------------------------
.SH "SEE ALSO"
.BR ghdl (1),
.BR xilinx_ghdl_simprim (1)
.
.\" ------------------------------------------------------------------
.SH AUTHOR
Walter F.J. Mueller <W.F.J.Mueller@gsi.de>

74
doc/man/man5/vbom.5
View File

@@ -1,5 +1,5 @@
.\" -*- nroff -*-
.\" $Id: vbom.5 320 2010-07-30 19:35:01Z mueller $
.\" $Id: vbom.5 522 2013-05-24 17:50:29Z mueller $
.\"
.\" Copyright 2010- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
.\"
@@ -12,86 +12,54 @@ vbom \- 'vhdl bill of material' file format
.
.\" ------------------------------------------------------------------
.SH DESCRIPTION
These files describe the sources needed to build a
.I vhdl
These files describe the sources needed to build a \fIvhdl\fP
module. The source files are either given directly in case of libraries
or via other
.IR vbom 's
in case of instantiated components. They are used by
.BR vbomconv (1)
to build project descriptions for synthesis and simulation tools.
or via other \fIvbom\fP's in case of instantiated components.
They are used by \fBvbomconv\fP(1) to build project descriptions
for synthesis and simulation tools.
The format has four types of lines:
.
.\" ----------------------------------------------
.TP
.B comments
each line starting with
.B #
is treated as comment and ignored.
.IP \fBcomments\fP
each line starting with \fB#\fP is treated as comment and ignored.
.
.\" ----------------------------------------------
.TP
.B file names
either source files with a
.I '.vhd'
file type or nested
.IR vbom 's
with a
.I '.vbom'
file type. The must be given as relative path name
from the directory the
.I vbom
file is located in. Absolute path names are not allowed, nor is expansion of
environment variables.
.IP "\fBfile names\fP"
either source files with a '\fI.vhd\fP' file type or nested \fIvbom\fP's
with a '\fI.vbom\fP' file type. The must be given as relative path name
from the directory the \fIvbom\fP file is located in.
Absolute path names are not allowed, nor is expansion of environment variables.
.
.\" ----------------------------------------------
.TP
.B logical names
.IP "\fBlogical names\fP"
A logical name can be defined with
.EX
<lname> = <filename>
.EE
The first definition of a logical name encountered in the traversal of the
.IR vbom 's
by
.BR vbomconv (1)
is taken, all later definitions are ignored.
\fIvbom\fP's by \fBvbomconv\fP(1) is taken, all later definitions are ignored.
A logical name can be used with
.EX
<lname> : <filename>
.EE
If it wasn't
If it wasn't ???
Again, the filenames, either of type
.I vhd
or
.IR vbom ,
must be given as relative path name from the directory the
.I vbom
Again, the filenames, either of type \fI.vhd\fP or \fI.vbom\fP ,
must be given as relative path name from the directory the \fIvbom\fP
file is located in.
The definition clause just sets up the logical name for later usage.
The usage clause
.\" ----------------------------------------------
.TP
.B directives
.IP \fBdirectives\fP
The format is simple, essentially a list of file names, either
source files with a
.I '.vhd'
file type or nested
.IR vbom 's
with a
.I '.vbom'
file type. Lines starting with
.B #
are treated as comments.
source files with a '\fI.vhd\fP' file type or nested \fIvbom\fP's
with a '\fI.vbom\fP' file type.
Lines starting with \fB#\fP are treated as comments.
.

4
doc/w11a_os_guide.txt
View File

@@ -1,4 +1,4 @@
# $Id: w11a_os_guide.txt 518 2013-05-12 16:45:02Z mueller $
# $Id: w11a_os_guide.txt 547 2013-12-29 13:10:07Z mueller $
Guide to run operating system images on w11a systems
@@ -120,7 +120,7 @@ Guide to run operating system images on w11a systems
- setup vt100 emulator window for 2nd DL11
cd $RETROBASE/tools/oskit/<oskit-name>
telnet_starter -d -s DL1 &
telnet_starter -s -d DL1 &
{Note: the -s ensures that the port numbers used by simh are taken!}

13
doc/w11a_tb_guide.txt
View File

@@ -1,4 +1,4 @@
# $Id: w11a_tb_guide.txt 511 2013-04-27 13:51:46Z mueller $
# $Id: w11a_tb_guide.txt 547 2013-12-29 13:10:07Z mueller $
Guide to running w11a test benches
@@ -36,7 +36,7 @@ Guide to running w11a test benches
- 'tbw' is a small perl script setting up a symbolic link to the
stimulus file, the default extracted from the file tbw.dat, if
an optional file name is give this one will be used instead.
- 'tee' ensured that the full log is saved
- 'tee' ensures that the full log is saved
- 'egrep' filters FAIL and DONE lines, a successful run will
produce a single DONE line
@@ -253,7 +253,7 @@ Guide to running w11a test benches
"rw11::run_pdpcp ../../../../w11a/tb/tb_pdp11core_stim.dat" |\
tee tb_w11a_s3_stim2_dsim.log | egrep "(-[EFW]:|FAIL|PEND|DONE)"
-> 10225140.0 ns 511247: DONE
-> real 0m52.105s user 0m0.260s sys 0m0.132s
-> real 0m52.105s user 0m51.871s sys 0m0.376s
- sys_w11a_n2 test bench
@@ -264,7 +264,7 @@ Guide to running w11a test benches
"rw11::run_pdpcp ../../../../w11a/tb/tb_pdp11core_stim.dat" |\
tee tb_w11a_n2_stim2_dsim.log | egrep "(-[EFW]:|FAIL|PEND|DONE)"
-> 10278380.0 ns 513908: DONE
-> real 1m26.388s user 0m0.312s sys 0m0.156s
-> real 1m2.951s user 1m2.628s sys 0m0.532s
- sys_w11a_n3 test bench
@@ -275,7 +275,7 @@ Guide to running w11a test benches
"rw11::run_pdpcp ../../../../w11a/tb/tb_pdp11core_stim.dat" |\
tee tb_w11a_n3_stim2_dsim.log | egrep "(-[EFW]:|FAIL|PEND|DONE)"
-> 5167410.0 ns 516720: DONE
-> real 1m26.611s user 0m0.248s sys 0m0.196s
-> real 1m5.322s user 1m5.072s sys 0m0.500s
A new, modular w11a test bench is under construction. So far it is very
incomplete. This very preliminary version can be executed with
@@ -288,4 +288,5 @@ Guide to running w11a test benches
"rw11::setup_cpu" "rw11::tbench @w11a_all.dat" | \
tee w11a_tbench_dsim.log | egrep "(-[EFW]:|FAIL|PASS|DONE)"
-> 904180.0 ns 45198: DONE
-> real 0m5.739s user 0m0.576s sys 0m0.076s
-> real 0m5.539s user 0m5.748s sys 0m0.204s

7
rtl/bplib/atlys/atlys_time_fx2_ic.ucf
View File

@@ -1,7 +1,8 @@
## $Id: atlys_time_fx2_ic.ucf 471 2013-01-05 19:46:38Z mueller $
## $Id: atlys_time_fx2_ic.ucf 537 2013-10-06 09:06:23Z mueller $
##
## Revision History:
## Date Rev Version Comment
## 2013-10-05 537 1.1 add VALID for hold time check
## 2013-01-05 471 1.0 Initial version (copied from nexys3)
##
## timing rules for a 30 MHz internal clock design:
@@ -13,5 +14,5 @@
NET "I_FX2_IFCLK" TNM_NET = "I_FX2_IFCLK";
TIMESPEC "TS_I_FX2_IFCLK" = PERIOD "I_FX2_IFCLK" 33.34 ns HIGH 50 %;
OFFSET = IN 2 ns BEFORE "I_FX2_IFCLK";
OFFSET = OUT 10 ns AFTER "I_FX2_IFCLK";
OFFSET = IN 2 ns VALID 33 ns BEFORE "I_FX2_IFCLK";
OFFSET = OUT 10 ns VALID 33 ns AFTER "I_FX2_IFCLK";

4
rtl/bplib/bpgen/bp_rs232_2l4l_iob.vhd
View File

@@ -1,4 +1,4 @@
-- $Id: bp_rs232_2l4l_iob.vhd 426 2011-11-18 18:14:08Z mueller $
-- $Id: bp_rs232_2l4l_iob.vhd 534 2013-09-22 21:37:24Z mueller $
--
-- Copyright 2010-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@@ -13,7 +13,7 @@
--
------------------------------------------------------------------------------
-- Module Name: bp_rs232_2l4l_iob - syn
-- Description: iob's for internal + external rs232, with select
-- Description: iob's for internal(2line) + external(4line) rs232, with select
--
-- Dependencies: bp_rs232_2line_iob
-- bp_rs232_4line_iob

25
rtl/bplib/bpgen/bpgenlib.vhd
View File

@@ -1,4 +1,4 @@
-- $Id: bpgenlib.vhd 476 2013-01-26 22:23:53Z mueller $
-- $Id: bpgenlib.vhd 534 2013-09-22 21:37:24Z mueller $
--
-- Copyright 2011-2013 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@@ -19,6 +19,7 @@
-- Tool versions: 12.1, 13.3; ghdl 0.26-0.29
-- Revision History:
-- Date Rev Version Comment
-- 2013-09-21 534 1.1.1 add bp_rs232_4l4l_iob
-- 2013-01-26 476 1.1 moved rbus depended components to bpgenrbuslib
-- 2013-01-06 472 1.0.7 add sn_humanio_demu_rbus
-- 2011-11-16 426 1.0.6 now numeric_std clean
@@ -82,6 +83,28 @@ component bp_rs232_2l4l_iob is -- iob's for dual 2l+4l rs232, w/ select
);
end component;
component bp_rs232_4l4l_iob is -- iob's for dual 4l+4l rs232, w/ select
generic (
RELAY : boolean := false); -- add a relay stage towards IOB's
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset
SEL : in slbit; -- select, '0' for port 0
RXD : out slbit; -- receive data (board view)
TXD : in slbit; -- transmit data (board view)
CTS_N : out slbit; -- clear to send (act. low)
RTS_N : in slbit; -- request to send (act. low)
I_RXD0 : in slbit; -- pad-i: p0: receive data (board view)
O_TXD0 : out slbit; -- pad-o: p0: transmit data (board view)
I_CTS0_N : in slbit; -- pad-i: p0: clear to send (act. low)
O_RTS0_N : out slbit; -- pad-o: p0: request to send (act. low)
I_RXD1 : in slbit; -- pad-i: p1: receive data (board view)
O_TXD1 : out slbit; -- pad-o: p1: transmit data (board view)
I_CTS1_N : in slbit; -- pad-i: p1: clear to send (act. low)
O_RTS1_N : out slbit -- pad-o: p1: request to send (act. low)
);
end component;
component bp_swibtnled is -- generic SWI, BTN and LED handling
generic (
SWIDTH : positive := 4; -- SWI port width

2
rtl/bplib/fx2rlink/Makefile
View File

@@ -1,4 +1,4 @@
# $Id: $
# $Id: Makefile 525 2013-07-06 12:19:39Z mueller $
#
# Revision History:
# Date Rev Version Comment

2
rtl/bplib/fx2rlink/fx2rlinklib.vhd
View File

@@ -1,4 +1,4 @@
-- $Id: $
-- $Id: fx2rlinklib.vhd 525 2013-07-06 12:19:39Z mueller $
--
-- Copyright 2013- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--

2
rtl/bplib/fx2rlink/rlink_sp1c_fx2.vhd
View File

@@ -1,4 +1,4 @@
-- $Id: $
-- $Id: rlink_sp1c_fx2.vhd 525 2013-07-06 12:19:39Z mueller $
--
-- Copyright 2013- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--

7
rtl/bplib/nexys2/nexys2_time_fx2_ic.ucf
View File

@@ -1,7 +1,8 @@
## $Id: nexys2_time_fx2_ic.ucf 448 2012-01-02 21:55:11Z mueller $
## $Id: nexys2_time_fx2_ic.ucf 537 2013-10-06 09:06:23Z mueller $
##
## Revision History:
## Date Rev Version Comment
## 2013-10-05 537 1.1 add VALID for hold time check
## 2012-01-01 448 1.0 Initial version
##
## timing rules for a 30 MHz internal clock design:
@@ -22,5 +23,5 @@ NET "I_FX2_IFCLK" CLOCK_DEDICATED_ROUTE = FALSE;
##
NET "I_FX2_IFCLK" TNM_NET = "I_FX2_IFCLK";
TIMESPEC "TS_I_FX2_IFCLK" = PERIOD "I_FX2_IFCLK" 33.34 ns HIGH 50 %;
OFFSET = IN 2.5 ns BEFORE "I_FX2_IFCLK";
OFFSET = OUT 10 ns AFTER "I_FX2_IFCLK";
OFFSET = IN 2.5 ns VALID 33 ns BEFORE "I_FX2_IFCLK";
OFFSET = OUT 10 ns VALID 33 ns AFTER "I_FX2_IFCLK";

3
rtl/bplib/nexys3/nexys3_pins_pmb0_rs232.ucf
View File

@@ -1,4 +1,4 @@
## $Id: nexys3_pins_pmb0_rs232.ucf 430 2011-11-20 20:48:39Z mueller $
## $Id: nexys3_pins_pmb0_rs232.ucf 534 2013-09-22 21:37:24Z mueller $
##
## Revision History:
## Date Rev Version Comment
@@ -10,3 +10,4 @@ NET "O_FUSP_RTS_N" LOC = "k2" | IOSTANDARD=LVCMOS33 | DRIVE=4 | SLEW=SLOW;
NET "I_FUSP_CTS_N" LOC = "k1" | IOSTANDARD=LVCMOS33 | PULLDOWN;
NET "I_FUSP_RXD" LOC = "l4" | IOSTANDARD=LVCMOS33 | PULLUP;
NET "O_FUSP_TXD" LOC = "l3" | IOSTANDARD=LVCMOS33 | DRIVE=4 | SLEW=SLOW;
##

7
rtl/bplib/nexys3/nexys3_time_fx2_ic.ucf
View File

@@ -1,7 +1,8 @@
## $Id: nexys3_time_fx2_ic.ucf 448 2012-01-02 21:55:11Z mueller $
## $Id: nexys3_time_fx2_ic.ucf 537 2013-10-06 09:06:23Z mueller $
##
## Revision History:
## Date Rev Version Comment
## 2013-10-05 537 1.1 add VALID for hold time check
## 2012-01-01 448 1.0 Initial version
##
## timing rules for a 30 MHz internal clock design:
@@ -13,5 +14,5 @@
NET "I_FX2_IFCLK" TNM_NET = "I_FX2_IFCLK";
TIMESPEC "TS_I_FX2_IFCLK" = PERIOD "I_FX2_IFCLK" 33.34 ns HIGH 50 %;
OFFSET = IN 2 ns BEFORE "I_FX2_IFCLK";
OFFSET = OUT 10 ns AFTER "I_FX2_IFCLK";
OFFSET = IN 2 ns VALID 33 ns BEFORE "I_FX2_IFCLK";
OFFSET = OUT 10 ns VALID 33 ns AFTER "I_FX2_IFCLK";

2
rtl/bplib/nexys3/tb/tb_nexys3_fusp.vbom
View File

@@ -16,7 +16,7 @@ ${sys_conf := sys_conf_sim.vhd}
../../../vlib/simlib/simclk.vbom
../../../vlib/simlib/simclkcnt.vbom
../../../vlib/rlink/tb/tbcore_rlink.vbom
../../../vlib/xlib/dcm_sfs_gsim.vbom
../../../vlib/xlib/s6_cmt_sfs_gsim.vbom
tb_nexys3_core.vbom
../../../vlib/serport/serport_uart_rxtx.vbom
${nexys3_fusp_aif := nexys3_fusp_dummy.vbom}

21
rtl/bplib/nexys3/tb/tb_nexys3_fusp.vhd
View File

@@ -1,6 +1,6 @@
-- $Id: tb_nexys3_fusp.vhd 476 2013-01-26 22:23:53Z mueller $
-- $Id: tb_nexys3_fusp.vhd 538 2013-10-06 17:21:25Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2011-2013 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
@@ -17,7 +17,7 @@
--
-- Dependencies: simlib/simclk
-- simlib/simclkcnt
-- xlib/dcm_sfs
-- xlib/s6_cmt_sfs
-- rlink/tb/tbcore_rlink
-- tb_nexys3_core
-- serport/serport_uart_rxtx
@@ -26,10 +26,11 @@
-- To test: generic, any nexys3_fusp_aif target
--
-- Target Devices: generic
-- Tool versions: xst 13.1; ghdl 0.29
-- Tool versions: xst 13.1, 14.6; ghdl 0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2013-10-06 538 1.2 pll support, use clksys_vcodivide ect
-- 2011-12-23 444 1.1 new system clock scheme, new tbcore_rlink iface
-- 2011-11-25 432 1.0 Initial version (derived from tb_nexys2_fusp)
------------------------------------------------------------------------------
@@ -123,11 +124,15 @@ begin
CLK_STOP => CLK_STOP
);
DCM_COM : dcm_sfs
CLKGEN_COM : s6_cmt_sfs
generic map (
CLKFX_DIVIDE => sys_conf_clkfx_divide,
CLKFX_MULTIPLY => sys_conf_clkfx_multiply,
CLKIN_PERIOD => 10.0)
VCO_DIVIDE => sys_conf_clksys_vcodivide,
VCO_MULTIPLY => sys_conf_clksys_vcomultiply,
OUT_DIVIDE => sys_conf_clksys_outdivide,
CLKIN_PERIOD => 10.0,
CLKIN_JITTER => 0.01,
STARTUP_WAIT => false,
GEN_TYPE => sys_conf_clksys_gentype)
port map (
CLKIN => CLKOSC,
CLKFX => CLKCOM,

2
rtl/bplib/nexys3/tb/tb_nexys3_fusp_cuff.vbom
View File

@@ -16,7 +16,7 @@ ${sys_conf := sys_conf_sim.vhd}
../../../vlib/simlib/simclk.vbom
../../../vlib/simlib/simclkcnt.vbom
../../../vlib/rlink/tb/tbcore_rlink.vbom
../../../vlib/xlib/dcm_sfs_gsim.vbom
../../../vlib/xlib/s6_cmt_sfs_gsim.vbom
tb_nexys3_core.vbom
../../../vlib/serport/serport_uart_rxtx.vbom
../../../bplib/fx2lib/tb/fx2_2fifo_core.vbom

19
rtl/bplib/nexys3/tb/tb_nexys3_fusp_cuff.vhd
View File

@@ -1,4 +1,4 @@
-- $Id: tb_nexys3_fusp_cuff.vhd 509 2013-04-21 20:46:20Z mueller $
-- $Id: tb_nexys3_fusp_cuff.vhd 538 2013-10-06 17:21:25Z mueller $
--
-- Copyright 2013- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@@ -17,7 +17,7 @@
--
-- Dependencies: simlib/simclk
-- simlib/simclkcnt
-- xlib/dcm_sfs
-- xlib/s6_cmt_sfs
-- rlink/tb/tbcore_rlink
-- tb_nexys3_core
-- serport/serport_uart_rxtx
@@ -27,10 +27,11 @@
-- To test: generic, any nexys3_fusp_cuff_aif target
--
-- Target Devices: generic
-- Tool versions: xst 13.1; ghdl 0.29
-- Tool versions: xst 13.1, 14.6; ghdl 0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2013-10-06 538 1.1 pll support, use clksys_vcodivide ect
-- 2013-04-21 509 1.0 Initial version (derived from tb_nexys3_fusp and
-- tb_nexys2_fusp_cuff)
------------------------------------------------------------------------------
@@ -147,11 +148,15 @@ begin
SB_CLKSTOP <= CLK_STOP;
DCM_COM : dcm_sfs
CLKGEN_COM : s6_cmt_sfs
generic map (
CLKFX_DIVIDE => sys_conf_clkfx_divide,
CLKFX_MULTIPLY => sys_conf_clkfx_multiply,
CLKIN_PERIOD => 10.0)
VCO_DIVIDE => sys_conf_clksys_vcodivide,
VCO_MULTIPLY => sys_conf_clksys_vcomultiply,
OUT_DIVIDE => sys_conf_clksys_outdivide,
CLKIN_PERIOD => 10.0,
CLKIN_JITTER => 0.01,
STARTUP_WAIT => false,
GEN_TYPE => sys_conf_clksys_gentype)
port map (
CLKIN => CLKOSC,
CLKFX => CLKCOM,

11
rtl/make/generic_isim.mk
View File

@@ -1,7 +1,8 @@
# $Id: generic_isim.mk 477 2013-01-27 14:07:10Z mueller $
# $Id: generic_isim.mk 539 2013-10-13 17:06:35Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2013-10-12 539 1.3 use xtwi
# 2013-01-27 477 1.2.1 use dontincdep.mk to suppress .dep include on clean
# 2011-08-13 405 1.2 renamed, moved to rtl/make;
# 2010-04-26 284 1.1 add _[sft]sim support
@@ -11,26 +12,26 @@ FUSE = fuse
#
%_ISim : %.vbom
vbomconv -isim_prj $< > $*_isim.prj
$(FUSE) $* -prj $*_isim.prj -o $*_ISim
xtwi $(FUSE) $* -prj $*_isim.prj -o $*_ISim
rm -rf $*_isim.prj
#
# rule for _ssim to call FUSE with right top level name
#
%_ISim_ssim : %_ssim.vbom
vbomconv -isim_prj $*_ssim.vbom > $*_isim_ssim.prj
$(FUSE) $* -prj $*_isim_ssim.prj -o $*_ISim_ssim
xtwi $(FUSE) $* -prj $*_isim_ssim.prj -o $*_ISim_ssim
rm -rf $*_isim_ssim.prj
#
# rule for _[ft]sim to use 'virtual' _[ft]sim vbom's (derived from _ssim)
#
%_ISim_fsim : %_ssim.vbom
vbomconv -isim_prj $*_fsim.vbom > $*_isim_fsim.prj
$(FUSE) $* -prj $*_isim_fsim.prj -o $*_ISim_fsim
xtwi $(FUSE) $* -prj $*_isim_fsim.prj -o $*_ISim_fsim
rm -rf $*_isim_fsim.prj
#
%_ISim_tsim : %_ssim.vbom
vbomconv -isim_prj $*_tsim.vbom > $*_isim_tsim.prj
$(FUSE) $* -prj $*_isim_tsim.prj -o $*_ISim_tsim
xtwi $(FUSE) $* -prj $*_isim_tsim.prj -o $*_ISim_tsim
rm -rf $*_isim_tsim.prj
#
%.dep_isim: %.vbom

30
rtl/make/generic_xflow.mk
View File

@@ -1,7 +1,8 @@
# $Id: generic_xflow.mk 477 2013-01-27 14:07:10Z mueller $
# $Id: generic_xflow.mk 539 2013-10-13 17:06:35Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2013-10-12 539 1.9 use xtwi; support trce tsi file; use -C for cpp
# 2013-01-27 477 1.8 remove defaults for ISE_(BOARD|PATH) and XFLOWOPT_*
# use dontincdep.mk to suppress .dep include on clean
# 2013-01-05 470 1.7.6 remove '-r' from all non-dir clean rm's
@@ -85,7 +86,7 @@ XFLOW = xflow -p ${ISE_PATH}
if [ -r ${RETROBASE}/rtl/make/${XFLOWOPT_SYN} ]; then \
cp ${RETROBASE}/rtl/make/${XFLOWOPT_SYN} ./ise; fi
if [ -r ${XFLOWOPT_SYN} ]; then cp ${XFLOWOPT_SYN} ./ise; fi
${XFLOW} -wd ise -synth ${XFLOWOPT_SYN} \
xtwi ${XFLOW} -wd ise -synth ${XFLOWOPT_SYN} \
-g top_entity:`vbomconv --get_top $<` $*.prj
(cd ./ise; chmod -x *.* )
if [ -r ./ise/$*.ngc ]; then cp -p ./ise/$*.ngc .; fi
@@ -107,7 +108,7 @@ XFLOW = xflow -p ${ISE_PATH}
if [ -r ${RETROBASE}/rtl/make/${XFLOWOPT_SYN} ]; then \
cp ${RETROBASE}/rtl/make/${XFLOWOPT_SYN} ./ise; fi
if [ -r ${XFLOWOPT_SYN} ]; then cp ${XFLOWOPT_SYN} ./ise; fi
${XFLOW} -wd ise -synth ${XFLOWOPT_SYN} \
xtwi ${XFLOW} -wd ise -synth ${XFLOWOPT_SYN} \
-g top_entity:`vbomconv --get_top $<` $*.prj
(cd ./ise; chmod -x *.* )
if [ -r ./ise/$*.ngc ]; then cp -p ./ise/$*.ngc .; fi
@@ -128,6 +129,7 @@ XFLOW = xflow -p ${ISE_PATH}
# %_map.log map log file (renamed %_map.mrp)
# %_par.log par log file (renamed %.par)
# %_pad.log pad file (renamed %_pad.txt)
# %_tsi.log trce tsi file (renamed %.tsi)
# %_twr.log trce log file (renamed %.twr)
#
%.ncd %.pcf: %.ngc
@@ -137,7 +139,7 @@ XFLOW = xflow -p ${ISE_PATH}
if [ -r ${RETROBASE}/rtl/make/${XFLOWOPT_IMP} ]; then \
cp ${RETROBASE}/rtl/make/${XFLOWOPT_IMP} ./ise; fi
if [ -r ${XFLOWOPT_IMP} ]; then cp -p ${XFLOWOPT_IMP} ./ise; fi
${XFLOW} -wd ise -implement ${XFLOWOPT_IMP} $<
xtwi ${XFLOW} -wd ise -implement ${XFLOWOPT_IMP} $<
(cd ./ise; chmod -x *.* )
if [ -r ./ise/$*.ncd ]; then cp -p ./ise/$*.ncd .; fi
if [ -r ./ise/$*.pcf ]; then cp -p ./ise/$*.pcf .; fi
@@ -146,6 +148,7 @@ XFLOW = xflow -p ${ISE_PATH}
if [ -r ./ise/$*.par ]; then cp -p ./ise/$*.par ./$*_par.log; fi
if [ -r ./ise/$*_pad.txt ]; then cp -p ./ise/$*_pad.txt ./$*_pad.log; fi
if [ -r ./ise/$*.twr ]; then cp -p ./ise/$*.twr ./$*_twr.log; fi
if [ -r ./ise/$*.tsi ]; then cp -p ./ise/$*.tsi ./$*_tsi.log; fi
@ if [ -r $*.mfset ]; then \
echo "=============================================================";\
echo "* Translate Diagnostic Summary *";\
@@ -171,7 +174,7 @@ XFLOW = xflow -p ${ISE_PATH}
%.bit: %.ncd
if [ ! -d ./ise ]; then mkdir ./ise; fi
if [ -r $*.ncd ]; then cp -p $*.ncd ./ise; fi
(cd ./ise; bitgen -l -w -m -g ReadBack -g UserId:${ISE_USERID} -intstyle xflow $*.ncd)
(cd ./ise; xtwi bitgen -l -w -m -g ReadBack -g UserId:${ISE_USERID} -intstyle xflow $*.ncd)
(cd ./ise; chmod -x *.* )
if [ -r ./ise/$*.bit ]; then cp -p ./ise/$*.bit .; fi
if [ -r ./ise/$*.msk ]; then cp -p ./ise/$*.msk .; fi
@@ -189,7 +192,7 @@ XFLOW = xflow -p ${ISE_PATH}
# output: %.svf
#
%.svf: %.bit
config_wrapper --board=${ISE_BOARD} --path=${ISE_PATH} bit2svf $*.bit
xtwi config_wrapper --board=${ISE_BOARD} --path=${ISE_PATH} bit2svf $*.bit
#
# Configure FPGA with impact
@@ -197,7 +200,7 @@ XFLOW = xflow -p ${ISE_PATH}
# output: .PHONY
#
%.iconfig: %.bit
config_wrapper --board=${ISE_BOARD} --path=${ISE_PATH} iconfig $*.bit
xtwi config_wrapper --board=${ISE_BOARD} --path=${ISE_PATH} iconfig $*.bit
#
# Configure FPGA with jtag
@@ -210,7 +213,7 @@ endif
#
%.jconfig: %.svf
fx2load_wrapper --board=${ISE_BOARD} ${FX2LOAD_OPT}
config_wrapper --board=${ISE_BOARD} --path=${ISE_PATH} jconfig $*.svf
xtwi config_wrapper --board=${ISE_BOARD} --path=${ISE_PATH} jconfig $*.svf
#
# Print log file summary
@@ -239,7 +242,7 @@ endif
%_ssim.vhd: %.ngc
if [ ! -d ./ise ]; then mkdir ./ise; fi
if [ -r $*.ngc ]; then cp -p $*.ngc ./ise; fi
(cd ise; netgen -sim -intstyle xflow -ofmt vhdl -w $*.ngc)
(cd ise; xtwi netgen -sim -intstyle xflow -ofmt vhdl -w $*.ngc)
(cd ./ise; chmod -x *.* )
if [ -r ./ise/$*.vhd ]; then cp -p ./ise/$*.vhd ./$*_ssim.vhd; fi
if [ -r ./ise/$*.nlf ]; then cp -p ./ise/$*.nlf ./$*_ngn_ssim.log; fi
@@ -253,7 +256,7 @@ endif
%_fsim.vhd: %.ngc
if [ ! -d ./ise ]; then mkdir ./ise; fi
if [ -r $*.ngc ]; then cp -p $*.ngc ./ise; fi
(cd ise; ngdbuild -p ${ISE_PATH} -nt timestamp -intstyle xflow \
(cd ise; xtwi ngdbuild -p ${ISE_PATH} -nt timestamp -intstyle xflow \
$*.ngc $*.ngd)
(cd ise; netgen -sim -intstyle xflow -ofmt vhdl -w $*.ngd)
(cd ./ise; chmod -x *.* )
@@ -275,7 +278,7 @@ endif
if [ ! -d ./ise ]; then mkdir ./ise; fi
if [ -r $*.ncd ]; then cp -p $*.ncd ./ise; fi
if [ -r $*.pcf ]; then cp -p $*.pcf ./ise; fi
(cd ise; netgen -ofmt vhdl -sim -w -intstyle xflow -pcf \
(cd ise; xtwi netgen -ofmt vhdl -sim -w -intstyle xflow -pcf \
$*.pcf $*.ncd $*_tsim.vhd )
(cd ./ise; chmod -x *.* )
if [ -r ./ise/$*_tsim.vhd ]; then cp -p ./ise/$*_tsim.vhd .; fi
@@ -292,12 +295,12 @@ endif
# generate cpp'ed ucf files from ucf_cpp
#
%.ucf : %.ucf_cpp
cpp -I${RETROBASE}/rtl $*.ucf_cpp $*.ucf
cpp -C -I${RETROBASE}/rtl $*.ucf_cpp $*.ucf
#
# generate nested dependency rules for cpp'ed ucf files from ucf_cpp
#
%.dep_ucf_cpp : %.ucf_cpp
cpp -I${RETROBASE}/rtl -MM $*.ucf_cpp |\
cpp -C -I${RETROBASE}/rtl -MM $*.ucf_cpp |\
sed 's/\.o:/\.ucf:/' > $*.dep_ucf_cpp
#
include $(RETROBASE)/rtl/make/dontincdep.mk
@@ -320,6 +323,7 @@ ise_clean: ise_tmp_clean
rm -f *_par.log
rm -f *_pad.log
rm -f *_twr.log
rm -f *_tsi.log
rm -f *_bgn.log
rm -f *_ngn_[sft]sim.log
rm -f *_svn.log

9
rtl/make/generic_xflow_cpld.mk
View File

@@ -1,7 +1,8 @@
# $Id: generic_xflow_cpld.mk 470 2013-01-05 17:28:46Z mueller $
# $Id: generic_xflow_cpld.mk 539 2013-10-13 17:06:35Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2013-10-12 539 1.2 use xtwi
# 2013-01-05 470 1.1.1 remove '-r' from all non-dir clean rm's
# 2011-08-13 405 1.1 renamed, moved to rtl/make;
# 2010-03-13 268 1.0 Initial version, cloned from .xflow Rev 252
@@ -45,7 +46,7 @@ XFLOW = xflow -p ${ISE_PATH}
(cd ./ise; touch $*.xcf)
if [ -r $*.xcf ]; then cp $*.xcf ./ise; fi
if [ -r ${XFLOWOPT_SYN} ]; then cp ${XFLOWOPT_SYN} ./ise; fi
${XFLOW} -wd ise -synth ${XFLOWOPT_SYN} $*.prj
xtwi ${XFLOW} -wd ise -synth ${XFLOWOPT_SYN} $*.prj
(cd ./ise; chmod -x *.* )
if [ -r ./ise/$*.ngc ]; then cp -p ./ise/$*.ngc .; fi
if [ -r ./ise/$*_xst.log ]; then cp -p ./ise/$*_xst.log .; fi
@@ -63,7 +64,7 @@ XFLOW = xflow -p ${ISE_PATH}
(cd ./ise; touch $*.xcf)
if [ -r $*.xcf ]; then cp $*.xcf ./ise; fi
if [ -r ${XFLOWOPT_SYN} ]; then cp ${XFLOWOPT_SYN} ./ise; fi
${XFLOW} -wd ise -synth ${XFLOWOPT_SYN} $*.prj
xtwi ${XFLOW} -wd ise -synth ${XFLOWOPT_SYN} $*.prj
(cd ./ise; chmod -x *.* )
if [ -r ./ise/$*.ngc ]; then cp -p ./ise/$*.ngc .; fi
if [ -r ./ise/$*_xst.log ]; then cp -p ./ise/$*_xst.log .; fi
@@ -90,7 +91,7 @@ XFLOW = xflow -p ${ISE_PATH}
if [ -r $*.ngc ]; then cp -p $*.ngc ./ise; fi
if [ -r $*.ucf ]; then cp -p $*.ucf ./ise; fi
if [ -r ${XFLOWOPT_IMP} ]; then cp -p ${XFLOWOPT_IMP} ./ise; fi
${XFLOW} -wd ise -fit ${XFLOWOPT_IMP} $<
xtwi ${XFLOW} -wd ise -fit ${XFLOWOPT_IMP} $<
(cd ./ise; chmod -x *.* )
if [ -r ./ise/$*.ncd ]; then cp -p ./ise/$*.ncd .; fi
if [ -r ./ise/$*.jed ]; then cp -p ./ise/$*.jed .; fi

97
rtl/make/imp_7a_speed.opt Normal file
View File

@@ -0,0 +1,97 @@
FLOWTYPE = FPGA;
#
# $Id: imp_7a_speed.opt 539 2013-10-13 17:06:35Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2013-10-11 539 1.1.1 use -fastpaths, -u, -tsi for trce
# 2013-10-02 537 1.1 Proper options for Artix-7 (RegDup only); -detail
# 2013-09-21 534 1.0 Initial version (cloned from imp_s6_speed.opt)
#
# Derived from ISE balanced.opt
# Uses uses settings like 'mapgloboptlogoptregdup' SmartExplorer strategy
#
# ----------------------------------------------------------------------------
# Options for Translator
#
# Type "ngdbuild -h" for a detailed list of ngdbuild command line options
#
Program ngdbuild
-p <partname>; # Partname to use - picked from xflow commandline
-nt timestamp; # NGO File generation. Regenerate only when
# source netlist is newer than existing
# NGO file (default)
-intstyle xflow; # Message Reporting Style: ise, xflow, or silent
<userdesign>; # User design - pick from xflow command line
<design>.ngd; # Name of NGD file. Filebase same as design filebase
End Program ngdbuild
#
# ----------------------------------------------------------------------------
# Options for Mapper
#
# Type "map -h <arch>" for a detailed list of map command line options
#
Program map
-o <design>_map.ncd; # Output Mapped ncd file
-intstyle xflow; # Message Reporting Style: ise, xflow, or silent
-ol high; # Effort level
-xe n; # Extra effort level for timing-driven packing (normal)
-register_duplication on;# Duplicate registers/luts during timing-driven packing
-w; # Always overwrite any existing output files
-mt 2; # Multi-threading
-detail; # detailed map report
<inputdir><design>.ngd; # Input NGD file
<inputdir><design>.pcf; # Physical constraints file
END Program map
#
# ----------------------------------------------------------------------------
# Options for Post Map Trace
#
# Type "trce -h" for a detailed list of trce command line options
#
Program post_map_trce
-v 3; # Produce verbose timing report
#-e 3; # Produce error report (limit 3 items/constraint)
-xml <design>_map.twx; # Output XML version of the timing report
-intstyle xflow; # Message Reporting Style: ise, xflow, or silent
<inputdir><design>_map.ncd; # Input mapped ncd
<inputdir><design>.pcf; # Physical constraints file
END Program post_map_trce
#
# ----------------------------------------------------------------------------
# Options for Place and Route
#
# Type "par -h" for a detailed list of par command line options
#
Program par
-w; # Overwrite existing placed and routed ncd
-ol high; # Overall effort level
-xe n; # extra effort level
-intstyle xflow; # Message Reporting Style: ise, xflow, or silent
-mt 2; # Multi-threading
<design>_map.ncd; # Input mapped NCD file
<inputdir><design>.ncd; # Output placed and routed NCD
<inputdir><design>.pcf; # Input physical constraints file
END Program par
#
# ----------------------------------------------------------------------------
# Options for Post Par Trace
#
# Type "trce -h" for a detailed list of trce command line options
#
Program post_par_trce
-v 3; # Produce verbose timing report
-fastpaths; # report fastest paths/verbose hold paths
-u 25; # report unconstrained paths
-intstyle xflow; # Message Reporting Style: ise, xflow, or silent
-xml <design>.twx; # Output XML version of the timing report
-tsi <design>.tsi; # produce timing specification interaction report
<inputdir><design>.ncd; # Input placed and routed ncd
<inputdir><design>.pcf; # Physical constraints file
END Program post_par_trce

11
rtl/make/imp_s3_speed.opt
View File

@@ -1,9 +1,11 @@
FLOWTYPE = FPGA;
#
# $Id: imp_s3_speed.opt 405 2011-08-14 08:16:28Z mueller $
# $Id: imp_s3_speed.opt 539 2013-10-13 17:06:35Z mueller $
#
# Revision History:
# Date Rev Version Comment
# Date Rev Version Comment
# 2013-10-11 539 1.2.1 use -fastpaths, -u, -tsi for trce
# 2013-10-05 537 1.2 use -detail for map
# 2011-08-13 405 1.1 renamed, moved to rtl/make;
# 2007-07-20 67 1.0 Initial version
#
@@ -33,6 +35,7 @@ End Program ngdbuild
Program map
-o <design>_map.ncd; # Output Mapped ncd file
-intstyle xflow; # Message Reporting Style: ise, xflow, or silent
-detail; # detailed map report
<inputdir><design>.ngd; # Input NGD file
<inputdir><design>.pcf; # Physical constraints file
END Program map
@@ -76,9 +79,11 @@ END Program par
#
Program post_par_trce
-v 3; # Produce verbose timing report
#-e 3; # Produce error report (limit 3 items/constraint)
-fastpaths; # report fastest paths/verbose hold paths
-u 25; # report unconstrained paths
-intstyle xflow; # Message Reporting Style: ise, xflow, or silent
-xml <design>.twx; # Output XML version of the timing report
-tsi <design>.tsi; # produce timing specification interaction report
<inputdir><design>.ncd; # Input placed and routed ncd
<inputdir><design>.pcf; # Physical constraints file
END Program post_par_trce

13
rtl/make/imp_s3_speed_maptd.opt
View File

@@ -1,9 +1,11 @@
FLOWTYPE = FPGA;
#
# $Id: imp_s3_speed_maptd.opt 405 2011-08-14 08:16:28Z mueller $
# $Id: imp_s3_speed_maptd.opt 539 2013-10-13 17:06:35Z mueller $
#
# Revision History:
# Date Rev Version Comment
# Date Rev Version Comment
# 2013-10-11 539 1.2.1 use -fastpaths, -u, -tsi for trce
# 2013-10-05 537 1.2 use -detail for map
# 2011-08-13 405 1.1 renamed, moved to rtl/make;
# 2007-07-20 67 1.0 Initial version
#
@@ -39,6 +41,7 @@ Program map
-xe n; # Extra effort level for timing-driven packing (normal)
-register_duplication on;# Duplicate registers/luts during timing-driven packing
-logic_opt on; # Perform physical synthesis combinatorial logic opt.
-detail; # detailed map report
<inputdir><design>.ngd; # Input NGD file
<inputdir><design>.pcf; # Physical constraints file
END Program map
@@ -51,9 +54,11 @@ END Program map
#
Program post_map_trce
-v 3; # Produce verbose timing report
#-e 3; # Produce error report (limit 3 items/constraint)
-xml <design>_map.twx; # Output XML version of the timing report
-fastpaths; # report fastest paths/verbose hold paths
-u 25; # report unconstrained paths
-intstyle xflow; # Message Reporting Style: ise, xflow, or silent
-xml <design>_map.twx; # Output XML version of the timing report
-tsi <design>.tsi; # produce timing specification interaction report
<inputdir><design>_map.ncd; # Input mapped ncd
<inputdir><design>.pcf; # Physical constraints file
END Program post_map_trce

18
rtl/make/imp_s6_speed.opt
View File

@@ -1,11 +1,14 @@
FLOWTYPE = FPGA;
#
# $Id: imp_s6_speed.opt 449 2012-01-04 08:14:11Z mueller $
# $Id: imp_s6_speed.opt 539 2013-10-13 17:06:35Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2012-01-03 449 1.1 use '-mt 2' in map and par
# 2011-08-13 405 1.0 Initial version
# Date Rev Version Comment
# 2013-10-11 539 1.2.1 use -fastpaths, -u, -tsi for trce
# 2013-10-02 537 1.2 for ISE 14.x: for map drop -global_opt and -logic_opt
# use only -register_duplication; use -detail
# 2012-01-03 449 1.1 use '-mt 2' in map and par
# 2011-08-13 405 1.0 Initial version
#
# Derived from ISE balanced.opt
# Uses uses settings like 'mapgloboptlogoptregdup' SmartExplorer strategy
@@ -36,11 +39,10 @@ Program map
-intstyle xflow; # Message Reporting Style: ise, xflow, or silent
-ol high; # Effort level
-xe n; # Extra effort level for timing-driven packing (normal)
-global_opt speed; # Perform global optimization before mapping
-logic_opt on; # Perform physical synthesis combinatorial logic opt.
-register_duplication on;# Duplicate registers/luts during timing-driven packing
-w; # Always overwrite any existing output files
-mt 2; # Multi-threading
-detail; # detailed map report
<inputdir><design>.ngd; # Input NGD file
<inputdir><design>.pcf; # Physical constraints file
END Program map
@@ -85,9 +87,11 @@ END Program par
#
Program post_par_trce
-v 3; # Produce verbose timing report
#-e 3; # Produce error report (limit 3 items/constraint)
-fastpaths; # report fastest paths/verbose hold paths
-u 100; # report unconstrained paths
-intstyle xflow; # Message Reporting Style: ise, xflow, or silent
-xml <design>.twx; # Output XML version of the timing report
-tsi <design>.tsi; # produce timing specification interaction report
<inputdir><design>.ncd; # Input placed and routed ncd
<inputdir><design>.pcf; # Physical constraints file
END Program post_par_trce

96
rtl/make/imp_s6_speed_ise133.opt Normal file
View File

@@ -0,0 +1,96 @@
FLOWTYPE = FPGA;
#
# $Id: imp_s6_speed_ise133.opt 537 2013-10-06 09:06:23Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2012-01-03 449 1.1 use '-mt 2' in map and par
# 2011-08-13 405 1.0 Initial version
#
# Derived from ISE balanced.opt
# Uses uses settings like 'mapgloboptlogoptregdup' SmartExplorer strategy
#
# ----------------------------------------------------------------------------
# Options for Translator
#
# Type "ngdbuild -h" for a detailed list of ngdbuild command line options
#
Program ngdbuild
-p <partname>; # Partname to use - picked from xflow commandline
-nt timestamp; # NGO File generation. Regenerate only when
# source netlist is newer than existing
# NGO file (default)
-intstyle xflow; # Message Reporting Style: ise, xflow, or silent
<userdesign>; # User design - pick from xflow command line
<design>.ngd; # Name of NGD file. Filebase same as design filebase
End Program ngdbuild
#
# ----------------------------------------------------------------------------
# Options for Mapper
#
# Type "map -h <arch>" for a detailed list of map command line options
#
Program map
-o <design>_map.ncd; # Output Mapped ncd file
-intstyle xflow; # Message Reporting Style: ise, xflow, or silent
-ol high; # Effort level
-xe n; # Extra effort level for timing-driven packing (normal)
-global_opt speed; # Perform global optimization before mapping
-logic_opt on; # Perform physical synthesis combinatorial logic opt.
-register_duplication on;# Duplicate registers/luts during timing-driven packing
-w; # Always overwrite any existing output files
-mt 2; # Multi-threading
-detail; # detailed map report
<inputdir><design>.ngd; # Input NGD file
<inputdir><design>.pcf; # Physical constraints file
END Program map
#
# ----------------------------------------------------------------------------
# Options for Post Map Trace
#
# Type "trce -h" for a detailed list of trce command line options
#
Program post_map_trce
-v 3; # Produce verbose timing report
#-e 3; # Produce error report (limit 3 items/constraint)
-xml <design>_map.twx; # Output XML version of the timing report
-intstyle xflow; # Message Reporting Style: ise, xflow, or silent
<inputdir><design>_map.ncd; # Input mapped ncd
<inputdir><design>.pcf; # Physical constraints file
END Program post_map_trce
#
# ----------------------------------------------------------------------------
# Options for Place and Route
#
# Type "par -h" for a detailed list of par command line options
#
Program par
-w; # Overwrite existing placed and routed ncd
-ol high; # Overall effort level
-xe n; # extra effort level
-intstyle xflow; # Message Reporting Style: ise, xflow, or silent
-mt 2; # Multi-threading
<design>_map.ncd; # Input mapped NCD file
<inputdir><design>.ncd; # Output placed and routed NCD
<inputdir><design>.pcf; # Input physical constraints file
END Program par
#
# ----------------------------------------------------------------------------
# Options for Post Par Trace
#
# Type "trce -h" for a detailed list of trce command line options
#
Program post_par_trce
-v 3; # Produce verbose timing report
#-e 3; # Produce error report (limit 3 items/constraint)
-intstyle xflow; # Message Reporting Style: ise, xflow, or silent
-xml <design>.twx; # Output XML version of the timing report
<inputdir><design>.ncd; # Input placed and routed ncd
<inputdir><design>.pcf; # Physical constraints file
END Program post_par_trce

42
rtl/make/syn_7a_speed.opt Normal file
View File

@@ -0,0 +1,42 @@
FLOWTYPE = FPGA_SYNTHESIS;
#
# $Id: syn_7a_speed.opt 540 2013-10-13 18:42:50Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2013-10-13 540 1.2 use -shreg_min_size=3
# 2013-09-21 534 1.0 Initial version (cloned from imp_s6_speed.opt)
#
# Derived from ISE xst_mixed.opt
#
# ----------------------------------------------------------------------------
# Options for XST
#
Program xst
-ifn <design>_xst.scr; # input XST script file
-ofn <design>_xst.log; # output XST log file
-intstyle xflow; # Message Reporting Style
#
# ParamFile lists the XST Properties that can be set by the user.
#
ParamFile: <design>_xst.scr
"run";
#
# Global Synthesis Options
#
"-ifn <synthdesign>"; # Input/Project File Name
"-ifmt mixed"; # Input Format (Verilog and VHDL)
"-ofn <design>"; # Output File Name
"-ofmt ngc"; # Output File Format
"-top $top_entity"; # Top Design Name
"-p <partname>"; # Target Device
"-opt_mode SPEED"; # Optimization Criteria # AREA or SPEED
"-opt_level 2"; # Optimization Effort Criteria: 2=High
"-shreg_min_size 3"; # default is 2 !!
"-uc <design>.xcf"; # Constraint File name
#
# The following are HDL Options
#
End ParamFile
End Program xst
#

7
rtl/make/syn_s3_speed.opt
View File

@@ -1,9 +1,10 @@
FLOWTYPE = FPGA_SYNTHESIS;
#
# $Id: syn_s3_speed.opt 405 2011-08-14 08:16:28Z mueller $
# $Id: syn_s3_speed.opt 540 2013-10-13 18:42:50Z mueller $
#
# Revision History:
# Date Rev Version Comment
# Date Rev Version Comment
# 2013-10-05 540 1.2 use -shreg_extract NO to avoid shreg capture flops
# 2011-08-13 405 1.1 renamed, moved to rtl/make;
# 2007-07-20 67 1.0 Initial version
#
@@ -31,6 +32,8 @@ ParamFile: <design>_xst.scr
"-p <partname>"; # Target Device
"-opt_mode SPEED"; # Optimization Criteria # AREA or SPEED
"-opt_level 2"; # Optimization Effort Criteria: 2=High
## "-shreg_min_size 3"; # not available for Spartan-3 !!
"-shreg_extract NO"; # --> switch shreg extrtaction off instead
"-uc <design>.xcf"; # Constraint File name
#
# The following are HDL Options

50
rtl/make/syn_s6_speed.opt
View File

@@ -1,9 +1,10 @@
FLOWTYPE = FPGA_SYNTHESIS;
#
# $Id: syn_s6_speed.opt 456 2012-02-05 22:19:44Z mueller $
# $Id: syn_s6_speed.opt 537 2013-10-06 09:06:23Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2013-10-05 537 1.2 define all, use -opt_level=2, -shreg_min_size=3
# 2012-02-05 456 1.1 use $top_entity variable for -top attribute
# 2011-08-13 405 1.0 Initial version
#
@@ -30,9 +31,52 @@ ParamFile: <design>_xst.scr
"-ofmt ngc"; # Output File Format
"-top $top_entity"; # Top Design Name
"-p <partname>"; # Target Device
"-opt_mode SPEED"; # Optimization Criteria # AREA or SPEED
"-opt_level 2"; # Optimization Effort Criteria: 2=High
"-uc <design>.xcf"; # Constraint File name
"-opt_mode SPEED"; # Optimization Criteria # AREA or SPEED
"-opt_level 2"; # Optimization Effort Criteria def=1 !
"-power NO"; # def
"-iuc NO"; # def
"-keep_hierarchy No"; # def
"-netlist_hierarchy As_Optimized";# def
"-rtlview No"; # def=yes if from ISE
"-glob_opt AllClockNets"; # likely def
"-read_cores YES"; # def (irrelevant)
"-write_timing_constraints NO"; # def
"-cross_clock_analysis NO"; # def
"-hierarchy_separator /"; # ?
"-bus_delimiter <>"; # def
"-case Maintain"; # def
"-slice_utilization_ratio 100"; # ?
"-bram_utilization_ratio 100"; # ?
"-dsp_utilization_ratio 100"; # ?
"-lc Auto"; # def
"-reduce_control_sets Auto"; # def
"-fsm_extract YES"; # def
"-fsm_encoding Auto"; # def
"-safe_implementation No"; # def
"-fsm_style LUT"; # def
"-ram_extract Yes"; # def
"-ram_style Auto"; # def
"-rom_extract Yes"; # def
"-rom_style Auto"; # def
"-shreg_extract YES"; # def
"-shreg_min_size 3"; # default is 2 !!
"-auto_bram_packing NO"; # def
"-resource_sharing YES"; # def
"-async_to_sync NO"; # def
"-use_dsp48 Auto"; # def
"-iobuf YES"; # def
"-max_fanout 100000"; # def
"-bufg 16"; # def (for S-6)
"-register_duplication YES"; # def
"-register_balancing No"; # def
"-optimize_primitives NO"; # def
"-use_clock_enable Auto"; # def
"-use_sync_set Auto"; # def
"-use_sync_reset Auto"; # def
"-iob Auto"; # ?
"-equivalent_register_removal YES"; # def
"-slice_utilization_ratio_maxmargin 5"; # ?
#
# The following are HDL Options
#

41
rtl/make/syn_s6_speed_ise133.opt Normal file
View File

@@ -0,0 +1,41 @@
FLOWTYPE = FPGA_SYNTHESIS;
#
# $Id: syn_s6_speed_ise133.opt 537 2013-10-06 09:06:23Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2012-02-05 456 1.1 use $top_entity variable for -top attribute
# 2011-08-13 405 1.0 Initial version
#
# Derived from ISE xst_mixed.opt
#
# ----------------------------------------------------------------------------
# Options for XST
#
Program xst
-ifn <design>_xst.scr; # input XST script file
-ofn <design>_xst.log; # output XST log file
-intstyle xflow; # Message Reporting Style
#
# ParamFile lists the XST Properties that can be set by the user.
#
ParamFile: <design>_xst.scr
"run";
#
# Global Synthesis Options
#
"-ifn <synthdesign>"; # Input/Project File Name
"-ifmt mixed"; # Input Format (Verilog and VHDL)
"-ofn <design>"; # Output File Name
"-ofmt ngc"; # Output File Format
"-top $top_entity"; # Top Design Name
"-p <partname>"; # Target Device
"-opt_mode SPEED"; # Optimization Criteria # AREA or SPEED
"-opt_level 2"; # Optimization Effort Criteria: 2=High
"-uc <design>.xcf"; # Constraint File name
#
# The following are HDL Options
#
End ParamFile
End Program xst
#

24
rtl/make/xflow_default_nexys4.mk Normal file
View File

@@ -0,0 +1,24 @@
# $Id: xflow_default_nexys4.mk 534 2013-09-22 21:37:24Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2013-09-21 534 1.0 Initial version
#---
#
# Setup for Digilent Nexys4
#
# setup default board (for impact), device and userid (for bitgen)
#
ISE_BOARD = nexys4
ISE_PATH = xc7a100t-csg324-1
#
# setup defaults for xflow option files for synthesis and implementation
#
ifndef XFLOWOPT_SYN
XFLOWOPT_SYN = syn_7a_speed.opt
endif
#
ifndef XFLOWOPT_IMP
XFLOWOPT_IMP = imp_7a_speed.opt
endif
#

14
rtl/sys_gen/tst_fx2loop/nexys3/ic/sys_conf.vhd
View File

@@ -1,4 +1,4 @@
-- $Id: sys_conf.vhd 510 2013-04-26 16:14:57Z mueller $
-- $Id: sys_conf.vhd 538 2013-10-06 17:21:25Z mueller $
--
-- Copyright 2012-2013 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@@ -16,9 +16,10 @@
-- Description: Definitions for sys_tst_fx2loop_ic_n3 (for synthesis)
--
-- Dependencies: -
-- Tool versions: xst 13.3, 14.5; ghdl 0.29
-- Tool versions: xst 13.3, 14.5, 14.6; ghdl 0.29
-- Revision History:
-- Date Rev Version Comment
-- 2013-10-06 538 1.2 pll support, use clksys_vcodivide ect
-- 2012-04-24 510 1.1 use 3/2 clock-> 150 MHz sysclk
-- 2012-04-09 461 1.0 Initial version
------------------------------------------------------------------------------
@@ -30,8 +31,10 @@ use work.slvtypes.all;
package sys_conf is
constant sys_conf_clkfx_divide : positive := 2;
constant sys_conf_clkfx_multiply : positive := 3;
constant sys_conf_clksys_vcodivide : positive := 2;
constant sys_conf_clksys_vcomultiply : positive := 3; -- dcm 150 MHz
constant sys_conf_clksys_outdivide : positive := 1; -- sys 150 MHz
constant sys_conf_clksys_gentype : string := "DCM";
constant sys_conf_fx2_type : string := "ic2";
@@ -53,7 +56,8 @@ package sys_conf is
-- derived constants
constant sys_conf_clksys : integer :=
(100000000/sys_conf_clkfx_divide)*sys_conf_clkfx_multiply;
((100000000/sys_conf_clksys_vcodivide)*sys_conf_clksys_vcomultiply) /
sys_conf_clksys_outdivide;
constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000;
end package sys_conf;

30
rtl/sys_gen/tst_fx2loop/nexys3/ic/sys_tst_fx2loop_ic_n3.ucf_cpp
View File

@@ -1,7 +1,8 @@
## $Id: sys_tst_fx2loop_ic_n3.ucf_cpp 461 2012-04-09 21:17:54Z mueller $
## $Id: sys_tst_fx2loop_ic_n3.ucf_cpp 556 2014-05-29 19:01:39Z mueller $
##
## Revision History:
## Date Rev Version Comment
## 2013-10-13 540 1.1 add pad->clk and fx2 cdc constraints
## 2012-04-09 461 1.0 Initial version
##
@@ -10,6 +11,33 @@ TIMESPEC "TS_I_CLK100" = PERIOD "I_CLK100" 10.0 ns HIGH 50 %;
OFFSET = IN 10 ns BEFORE "I_CLK100";
OFFSET = OUT 20 ns AFTER "I_CLK100";
## constrain pad->net clock delay
NET CLK TNM = TNM_CLK;
TIMESPEC TS_PAD_CLK=FROM PADS(I_CLK100) TO TNM_CLK 10 ns;
NET I_FX2_IFCLK_BUFGP TNM = TNM_IFCLK;
TIMESPEC TS_PAD_IFCLK=FROM PADS(I_FX2_IFCLK) TO TNM_IFCLK 10 ns;
## constrain async pad->pad delays
TIMEGRP TG_SLOW_INS = PADS(I_RXD);
TIMEGRP TG_SLOW_OUTS = PADS(O_TXD);
TIMESPEC TS_ASYNC_PADS=FROM TG_SLOW_INS TO TG_SLOW_OUTS 10 ns;
## FX2 controller specific constraints
## constrain cdc path in fifos and reset
TIMESPEC TS_CDC_FIFO =
FROM FFS(*FIFO/GC?/GRAY_*.CNT/R_DATA*
*FIFO/R_REG?_rst?
*FIFO/R_REG?_rst?_s)
TO FFS(*FIFO/R_REG?_?addr_c*
*FIFO/R_REG?_rst?_c
*FIFO/R_REG?_rst?_sc)
5 ns DATAPATHONLY;
## constrain cdc path in monitor
TIMESPEC TS_CDC_FX2MONI = FROM FFS
TO FFS(FX2_CNTL*/R_MONI_C*) 5 ns DATAPATHONLY;
##
## std board
##
#include "bplib/nexys3/nexys3_pins.ucf"

14
rtl/sys_gen/tst_fx2loop/nexys3/ic3/sys_conf.vhd
View File

@@ -1,4 +1,4 @@
-- $Id: sys_conf.vhd 510 2013-04-26 16:14:57Z mueller $
-- $Id: sys_conf.vhd 538 2013-10-06 17:21:25Z mueller $
--
-- Copyright 2012-2013 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@@ -16,9 +16,10 @@
-- Description: Definitions for sys_tst_fx2loop_ic3_n3 (for synthesis)
--
-- Dependencies: -
-- Tool versions: xst 13.3, 14.5; ghdl 0.29
-- Tool versions: xst 13.3, 14.5, 14.6; ghdl 0.29
-- Revision History:
-- Date Rev Version Comment
-- 2013-10-06 538 1.2 pll support, use clksys_vcodivide ect
-- 2012-04-25 510 1.1 use 3/2 clock-> 150 MHz sysclk
-- 2012-04-09 461 1.0 Initial version
------------------------------------------------------------------------------
@@ -30,8 +31,10 @@ use work.slvtypes.all;
package sys_conf is
constant sys_conf_clkfx_divide : positive := 2;
constant sys_conf_clkfx_multiply : positive := 3;
constant sys_conf_clksys_vcodivide : positive := 2;
constant sys_conf_clksys_vcomultiply : positive := 3; -- dcm 150 MHz
constant sys_conf_clksys_outdivide : positive := 1; -- sys 150 MHz
constant sys_conf_clksys_gentype : string := "DCM";
constant sys_conf_fx2_type : string := "ic3";
@@ -53,7 +56,8 @@ package sys_conf is
-- derived constants
constant sys_conf_clksys : integer :=
(100000000/sys_conf_clkfx_divide)*sys_conf_clkfx_multiply;
((100000000/sys_conf_clksys_vcodivide)*sys_conf_clksys_vcomultiply) /
sys_conf_clksys_outdivide;
constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000;
end package sys_conf;

4
rtl/sys_gen/tst_fx2loop/nexys3/sys_tst_fx2loop_n3.vbom
View File

@@ -14,8 +14,8 @@
../../../bplib/nxcramlib/nxcramlib.vhd
${sys_conf}
# components
[xst,isim]../../../vlib/xlib/dcm_sfs_unisim_s3e.vbom
[ghdl]../../../vlib/xlib/dcm_sfs_gsim.vbom
[xst,isim]../../../vlib/xlib/s6_cmt_sfs_unisim.vbom
[ghdl]../../../vlib/xlib/s6_cmt_sfs_gsim.vbom
../../../vlib/genlib/clkdivce.vbom
../../../bplib/bpgen/sn_humanio.vbom
../tst_fx2loop_hiomap.vbom

19
rtl/sys_gen/tst_fx2loop/nexys3/sys_tst_fx2loop_n3.vhd
View File

@@ -1,4 +1,4 @@
-- $Id: sys_tst_fx2loop_n3.vhd 514 2013-05-03 16:11:23Z mueller $
-- $Id: sys_tst_fx2loop_n3.vhd 538 2013-10-06 17:21:25Z mueller $
--
-- Copyright 2012-2013 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@@ -15,7 +15,7 @@
-- Module Name: sys_tst_fx2loop_n3 - syn
-- Description: test of Cypress EZ-USB FX2 controller
--
-- Dependencies: vlib/xlib/dcm_sfs
-- Dependencies: vlib/xlib/s6_cmt_sfs
-- vlib/genlib/clkdivce
-- bpgen/sn_humanio
-- tst_fx2loop_hiomap
@@ -28,7 +28,7 @@
-- Test bench: -
--
-- Target Devices: generic
-- Tool versions: xst 13.3, 14.5; ghdl 0.29
-- Tool versions: xst 13.3, 14.5, 14.6; ghdl 0.29
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri ctl/MHz
@@ -45,6 +45,7 @@
--
-- Revision History:
-- Date Rev Version Comment
-- 2013-10-06 538 1.1 pll support, use clksys_vcodivide ect
-- 2013-04-24 510 1.0.1 CLKDIV.CDUWIDTH now 8, support >127 sysclk
-- 2012-04-09 461 1.0 Initial version (derived from sys_tst_fx2loop_n2)
------------------------------------------------------------------------------
@@ -137,11 +138,15 @@ begin
report "assert sys_conf_clksys on MHz grid"
severity failure;
DCM : dcm_sfs
GEN_CLKSYS : s6_cmt_sfs
generic map (
CLKFX_DIVIDE => sys_conf_clkfx_divide,
CLKFX_MULTIPLY => sys_conf_clkfx_multiply,
CLKIN_PERIOD => 10.0)
VCO_DIVIDE => sys_conf_clksys_vcodivide,
VCO_MULTIPLY => sys_conf_clksys_vcomultiply,
OUT_DIVIDE => sys_conf_clksys_outdivide,
CLKIN_PERIOD => 10.0,
CLKIN_JITTER => 0.01,
STARTUP_WAIT => false,
GEN_TYPE => sys_conf_clksys_gentype)
port map (
CLKIN => I_CLK100,
CLKFX => CLK,

7
rtl/sys_gen/tst_fx2loop/tst_fx2loop.c
View File

@@ -1,6 +1,6 @@
/* $Id: tst_fx2loop.c 465 2012-12-27 21:29:38Z mueller $ */
/* $Id: tst_fx2loop.c 530 2013-08-09 21:25:04Z mueller $ */
/*
* Copyright 2011-2012 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
* Copyright 2011-2013 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
*
* This program is free software; you may redistribute and/or modify it under
* the terms of the GNU General Public License as published by the Free
@@ -14,6 +14,7 @@
*
* Revision History:
* Date Rev Version Comment
* 2013-08-09 530 2.1.2 -read: write up to 9 nstead of 7 words
* 2012-04-09 461 2.1.1 fix loop back code: fix run-down, add pipe drain
* 2012-03-24 460 2.1 add message loop back code (preliminary)
* 2012-03-10 459 2.0 re-write for asynchronous libusb interface
@@ -436,7 +437,7 @@ void do_read(int ep)
prt_time();
printf("read %4d word:", ntrans/2);
int nprt = ntrans/2;
if (nprt > 7) nprt = 7;
if (nprt > 9) nprt = 9;
for (i = 0; i < nprt; i++) printf(" %4.4x", (uint16_t)buf[i]);
printf("\n");
if (nsigint>0) break;

18
rtl/sys_gen/tst_rlink/nexys3/sys_conf.vhd
View File

@@ -1,6 +1,6 @@
-- $Id: sys_conf.vhd 433 2011-11-27 22:04:39Z mueller $
-- $Id: sys_conf.vhd 538 2013-10-06 17:21:25Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2011-2013 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
@@ -13,12 +13,13 @@
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for sys_tst_rlink_n2 (for synthesis)
-- Description: Definitions for sys_tst_rlink_n3 (for synthesis)
--
-- Dependencies: -
-- Tool versions: xst 13.1; ghdl 0.29
-- Tool versions: xst 13.1, 14.6; ghdl 0.29
-- Revision History:
-- Date Rev Version Comment
-- 2013-10-06 538 1.1 pll support, use clksys_vcodivide ect
-- 2011-11-26 433 1.0 Initial version
------------------------------------------------------------------------------
@@ -29,8 +30,10 @@ use work.slvtypes.all;
package sys_conf is
constant sys_conf_clkfx_divide : positive := 1;
constant sys_conf_clkfx_multiply : positive := 1; --
constant sys_conf_clksys_vcodivide : positive := 1;
constant sys_conf_clksys_vcomultiply : positive := 1; -- dcm 100 MHz
constant sys_conf_clksys_outdivide : positive := 1; -- sys 100 MHz
constant sys_conf_clksys_gentype : string := "DCM";
constant sys_conf_ser2rri_defbaud : integer := 115200; -- default 115k baud
@@ -39,7 +42,8 @@ package sys_conf is
-- derived constants
constant sys_conf_clksys : integer :=
(100000000/sys_conf_clkfx_divide)*sys_conf_clkfx_multiply;
((100000000/sys_conf_clksys_vcodivide)*sys_conf_clksys_vcomultiply) /
sys_conf_clksys_outdivide;
constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000;
constant sys_conf_ser2rri_cdinit : integer :=

4
rtl/sys_gen/tst_rlink/nexys3/sys_tst_rlink_n3.vbom
View File

@@ -10,8 +10,8 @@
../../../bplib/nxcramlib/nxcramlib.vhd
${sys_conf := sys_conf.vhd}
# components
[xst,isim]../../../vlib/xlib/dcm_sfs_unisim_s3e.vbom
[ghdl]../../../vlib/xlib/dcm_sfs_gsim.vbom
[xst,isim]../../../vlib/xlib/s6_cmt_sfs_unisim.vbom
[ghdl]../../../vlib/xlib/s6_cmt_sfs_gsim.vbom
../../../vlib/genlib/clkdivce.vbom
../../../bplib/bpgen/bp_rs232_2l4l_iob.vbom
../../../bplib/bpgen/sn_humanio_rbus.vbom

21
rtl/sys_gen/tst_rlink/nexys3/sys_tst_rlink_n3.vhd
View File

@@ -1,6 +1,6 @@
-- $Id: sys_tst_rlink_n3.vhd 476 2013-01-26 22:23:53Z mueller $
-- $Id: sys_tst_rlink_n3.vhd 538 2013-10-06 17:21:25Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2011-2013 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
@@ -15,7 +15,7 @@
-- Module Name: sys_tst_rlink_n3 - syn
-- Description: rlink tester design for nexys3
--
-- Dependencies: vlib/xlib/dcm_sfs
-- Dependencies: vlib/xlib/s6_cmt_sfs
-- vlib/genlib/clkdivce
-- bplib/bpgen/bp_rs232_2l4l_iob
-- bplib/bpgen/sn_humanio_rbus
@@ -27,7 +27,7 @@
-- Test bench: tb/tb_tst_rlink_n3
--
-- Target Devices: generic
-- Tool versions: xst 13.1; ghdl 0.29
-- Tool versions: xst 13.1, 14.6; ghdl 0.29
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
@@ -36,6 +36,7 @@
--
-- Revision History:
-- Date Rev Version Comment
-- 2013-10-06 538 1.2 pll support, use clksys_vcodivide ect
-- 2011-12-18 440 1.1.1 use [rt]xok for DSP_DP
-- 2011-12-11 438 1.1 use now rbd_tst_rlink and rlink_sp1c
-- 2011-11-26 433 1.0 Initial version (derived from sys_tst_rlink_n2)
@@ -145,11 +146,15 @@ begin
RESET <= '0'; -- so far not used
DCM : dcm_sfs
GEN_CLKSYS : s6_cmt_sfs
generic map (
CLKFX_DIVIDE => sys_conf_clkfx_divide,
CLKFX_MULTIPLY => sys_conf_clkfx_multiply,
CLKIN_PERIOD => 10.0)
VCO_DIVIDE => sys_conf_clksys_vcodivide,
VCO_MULTIPLY => sys_conf_clksys_vcomultiply,
OUT_DIVIDE => sys_conf_clksys_outdivide,
CLKIN_PERIOD => 10.0,
CLKIN_JITTER => 0.01,
STARTUP_WAIT => false,
GEN_TYPE => sys_conf_clksys_gentype)
port map (
CLKIN => I_CLK100,
CLKFX => CLK,

16
rtl/sys_gen/tst_rlink/nexys3/tb/sys_conf_sim.vhd
View File

@@ -1,6 +1,6 @@
-- $Id: sys_conf_sim.vhd 433 2011-11-27 22:04:39Z mueller $
-- $Id: sys_conf_sim.vhd 538 2013-10-06 17:21:25Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2011-2013 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
@@ -16,9 +16,10 @@
-- Description: Definitions for sys_tst_rlink_n3 (for simulation)
--
-- Dependencies: -
-- Tool versions: xst 13.1; ghdl 0.29
-- Tool versions: xst 13.1, 14.6; ghdl 0.29
-- Revision History:
-- Date Rev Version Comment
-- 2013-10-06 538 1.1 pll support, use clksys_vcodivide ect
-- 2011-11-26 433 1.0 Initial version
------------------------------------------------------------------------------
@@ -29,8 +30,10 @@ use work.slvtypes.all;
package sys_conf is
constant sys_conf_clkfx_divide : positive := 1;
constant sys_conf_clkfx_multiply : positive := 1;
constant sys_conf_clksys_vcodivide : positive := 1;
constant sys_conf_clksys_vcomultiply : positive := 1; -- dcm 100 MHz
constant sys_conf_clksys_outdivide : positive := 1; -- sys 100 MHz
constant sys_conf_clksys_gentype : string := "DCM";
constant sys_conf_ser2rri_cdinit : integer := 1-1; -- 1 cycle/bit in sim
@@ -39,7 +42,8 @@ package sys_conf is
-- derived constants
constant sys_conf_clksys : integer :=
(100000000/sys_conf_clkfx_divide)*sys_conf_clkfx_multiply;
((100000000/sys_conf_clksys_vcodivide)*sys_conf_clksys_vcomultiply) /
sys_conf_clksys_outdivide;
constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000;
end package sys_conf;

2
rtl/sys_gen/tst_rlink/nexys3/tb/tb_tst_rlink_n3_ssim.vbom
View File

@@ -1,6 +1,6 @@
# configure for _*sim case
# Note: this tb uses sys_tst_rlink_n3.vbom in local directory
# (not in .. as usual) to allow a tb specific configure !!!
nexys2_aif = sys_tst_rlink_n3_ssim.vhd
nexys3_fusp_aif = sys_tst_rlink_n3_ssim.vhd
tb_tst_rlink_n3.vbom
@top:tb_tst_rlink_n3

14
rtl/sys_gen/tst_rlink_cuff/nexys3/ic/sys_conf.vhd
View File

@@ -1,4 +1,4 @@
-- $Id: sys_conf.vhd 469 2013-01-05 12:29:44Z mueller $
-- $Id: sys_conf.vhd 538 2013-10-06 17:21:25Z mueller $
--
-- Copyright 2013- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@@ -16,9 +16,10 @@
-- Description: Definitions for sys_tst_rlink_cuff_ic_n3 (for synthesis)
--
-- Dependencies: -
-- Tool versions: xst 13.3; ghdl 0.29
-- Tool versions: xst 13.3, 14.6; ghdl 0.29
-- Revision History:
-- Date Rev Version Comment
-- 2013-10-06 538 1.1 pll support, use clksys_vcodivide ect
-- 2013-01-04 469 1.0 Initial version
------------------------------------------------------------------------------
@@ -29,8 +30,10 @@ use work.slvtypes.all;
package sys_conf is
constant sys_conf_clkfx_divide : positive := 1;
constant sys_conf_clkfx_multiply : positive := 1;
constant sys_conf_clksys_vcodivide : positive := 1;
constant sys_conf_clksys_vcomultiply : positive := 1; -- dcm 100 MHz
constant sys_conf_clksys_outdivide : positive := 1; -- sys 100 MHz
constant sys_conf_clksys_gentype : string := "DCM";
constant sys_conf_ser2rri_defbaud : integer := 115200; -- default 115k baud
constant sys_conf_hio_debounce : boolean := true; -- instantiate debouncers
@@ -53,7 +56,8 @@ package sys_conf is
-- derived constants
constant sys_conf_clksys : integer :=
(100000000/sys_conf_clkfx_divide)*sys_conf_clkfx_multiply;
((100000000/sys_conf_clksys_vcodivide)*sys_conf_clksys_vcomultiply) /
sys_conf_clksys_outdivide;
constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000;
constant sys_conf_ser2rri_cdinit : integer :=

16
rtl/sys_gen/tst_rlink_cuff/nexys3/ic/tb/sys_conf_sim.vhd
View File

@@ -1,4 +1,4 @@
-- $Id: sys_conf_sim.vhd 512 2013-04-28 07:44:02Z mueller $
-- $Id: sys_conf_sim.vhd 538 2013-10-06 17:21:25Z mueller $
--
-- Copyright 2013- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@@ -16,9 +16,10 @@
-- Description: Definitions for sys_tst_rlink_cuff_ic_n3 (for simulation)
--
-- Dependencies: -
-- Tool versions: xst 13.3; ghdl 0.29
-- Tool versions: xst 13.3, 14.6; ghdl 0.29
-- Revision History:
-- Date Rev Version Comment
-- 2013-10-06 538 1.1 pll support, use clksys_vcodivide ect
-- 2013-04-27 512 1.0 Initial version
------------------------------------------------------------------------------
@@ -29,8 +30,10 @@ use work.slvtypes.all;
package sys_conf is
constant sys_conf_clkfx_divide : positive := 1;
constant sys_conf_clkfx_multiply : positive := 1;
constant sys_conf_clksys_vcodivide : positive := 1;
constant sys_conf_clksys_vcomultiply : positive := 1; -- dcm 100 MHz
constant sys_conf_clksys_outdivide : positive := 1; -- sys 100 MHz
constant sys_conf_clksys_gentype : string := "DCM";
constant sys_conf_ser2rri_cdinit : integer := 1-1; -- 1 cycle/bit in sim
@@ -49,12 +52,13 @@ package sys_conf is
-- petowidth=10 -> 2^10 30 MHz clocks -> ~33 usec (normal operation)
constant sys_conf_fx2_petowidth : positive := 10;
constant sys_conf_clksys : integer :=
((100000000/sys_conf_clksys_vcodivide)*sys_conf_clksys_vcomultiply) /
sys_conf_clksys_outdivide;
constant sys_conf_fx2_ccwidth : positive := 5;
-- derived constants
constant sys_conf_clksys : integer :=
(100000000/sys_conf_clkfx_divide)*sys_conf_clkfx_multiply;
constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000;
end package sys_conf;

6
rtl/sys_gen/tst_rlink_cuff/nexys3/ic/tb/tbw.dat Normal file
View File

@@ -0,0 +1,6 @@
# $Id: tbw.dat 538 2013-10-06 17:21:25Z mueller $
#
[tb_tst_rlink_cuff_ic_n3]
rlink_cext_fifo_rx = <fifo>
rlink_cext_fifo_tx = <fifo>
rlink_cext_conf = <null>

4
rtl/sys_gen/tst_rlink_cuff/nexys3/sys_tst_rlink_cuff_n3.vbom
View File

@@ -15,8 +15,8 @@
../../../bplib/nxcramlib/nxcramlib.vhd
${sys_conf}
# components
[xst,isim]../../../vlib/xlib/dcm_sfs_unisim_s3e.vbom
[ghdl]../../../vlib/xlib/dcm_sfs_gsim.vbom
[xst,isim]../../../vlib/xlib/s6_cmt_sfs_unisim.vbom
[ghdl]../../../vlib/xlib/s6_cmt_sfs_gsim.vbom
../../../vlib/genlib/clkdivce.vbom
../../../bplib/bpgen/bp_rs232_2l4l_iob.vbom
../../../bplib/bpgen/sn_humanio_rbus.vbom

19
rtl/sys_gen/tst_rlink_cuff/nexys3/sys_tst_rlink_cuff_n3.vhd
View File

@@ -1,4 +1,4 @@
-- $Id: sys_tst_rlink_cuff_n3.vhd 512 2013-04-28 07:44:02Z mueller $
-- $Id: sys_tst_rlink_cuff_n3.vhd 538 2013-10-06 17:21:25Z mueller $
--
-- Copyright 2013- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@@ -15,7 +15,7 @@
-- Module Name: sys_tst_rlink_cuff_n3 - syn
-- Description: rlink tester design for nexys3 with fx2 interface
--
-- Dependencies: vlib/xlib/dcm_sfs
-- Dependencies: vlib/xlib/s6_cmt_sfs
-- vlib/genlib/clkdivce
-- bplib/bpgen/bp_rs232_2l4l_iob
-- bplib/bpgen/sn_humanio_rbus
@@ -28,7 +28,7 @@
-- Test bench: -
--
-- Target Devices: generic
-- Tool versions: xst 13.3; ghdl 0.29
-- Tool versions: xst 13.3, 14.6; ghdl 0.29
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri ctl/MHz
@@ -36,6 +36,7 @@
--
-- Revision History:
-- Date Rev Version Comment
-- 2013-10-06 538 1.1 pll support, use clksys_vcodivide ect
-- 2012-12-29 466 1.0 Initial version; derived from sys_tst_rlink_cuff_n2
-- and sys_tst_fx2loop_n3
------------------------------------------------------------------------------
@@ -164,11 +165,15 @@ begin
report "assert sys_conf_clksys on MHz grid"
severity failure;
DCM : dcm_sfs
GEN_CLKSYS : s6_cmt_sfs
generic map (
CLKFX_DIVIDE => sys_conf_clkfx_divide,
CLKFX_MULTIPLY => sys_conf_clkfx_multiply,
CLKIN_PERIOD => 10.0)
VCO_DIVIDE => sys_conf_clksys_vcodivide,
VCO_MULTIPLY => sys_conf_clksys_vcomultiply,
OUT_DIVIDE => sys_conf_clksys_outdivide,
CLKIN_PERIOD => 10.0,
CLKIN_JITTER => 0.01,
STARTUP_WAIT => false,
GEN_TYPE => sys_conf_clksys_gentype)
port map (
CLKIN => I_CLK100,
CLKFX => CLK,

9
rtl/sys_gen/w11a/nexys2/sys_w11a_n2.ucf_cpp
View File

@@ -1,7 +1,8 @@
## $Id: sys_w11a_n2.ucf_cpp 509 2013-04-21 20:46:20Z mueller $
## $Id: sys_w11a_n2.ucf_cpp 540 2013-10-13 18:42:50Z mueller $
##
## Revision History:
## Date Rev Version Comment
## 2013-10-13 540 1.1 add pad->clk constraints
## 2013-04-20 509 1.1 add fx2 support
## 2010-11-06 336 1.0.1 rename input pin CLK -> I_CLK50
## 2010-05-26 295 1.0 Initial version
@@ -12,6 +13,12 @@ TIMESPEC "TS_I_CLK50" = PERIOD "I_CLK50" 20.0 ns HIGH 50 %;
OFFSET = IN 10 ns BEFORE "I_CLK50";
OFFSET = OUT 20 ns AFTER "I_CLK50";
## constrain pad->net clock delay
NET CLK TNM = TNM_CLK;
TIMESPEC TS_PAD_CLK=FROM PADS(I_CLK50) TO TNM_CLK 10 ns;
NET I_FX2_IFCLK_BUFGP TNM = TNM_IFCLK;
TIMESPEC TS_PAD_IFCLK=FROM PADS(I_FX2_IFCLK) TO TNM_IFCLK 10 ns;
## std board
##
#include "bplib/nexys2/nexys2_pins.ucf"

19
rtl/sys_gen/w11a/nexys3/sys_conf.vhd
View File

@@ -1,4 +1,4 @@
-- $Id: sys_conf.vhd 509 2013-04-21 20:46:20Z mueller $
-- $Id: sys_conf.vhd 538 2013-10-06 17:21:25Z mueller $
--
-- Copyright 2011-2013 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@@ -16,9 +16,11 @@
-- Description: Definitions for sys_w11a_n3 (for synthesis)
--
-- Dependencies: -
-- Tool versions: xst 13.1; ghdl 0.29
-- Tool versions: xst 13.1, 14.6; ghdl 0.29
-- Revision History:
-- Date Rev Version Comment
-- 2013-10-06 538 1.2 pll support, use clksys_vcodivide ect
-- 2013-10-05 537 1.1.1 use 72 MHz, no closure w/ ISE 14.x for 80 anymore
-- 2013-04-21 509 1.1 add fx2 settings
-- 2011-11-26 433 1.0.1 use 80 MHz clksys (no closure for 85 after rev 432)
-- 2011-11-20 430 1.0 Initial version (derived from _n2 version)
@@ -40,10 +42,12 @@ use work.slvtypes.all;
package sys_conf is
constant sys_conf_clkfx_divide : positive := 5;
constant sys_conf_clkfx_multiply : positive := 4; -- ==> 80 MHz
constant sys_conf_memctl_read0delay : positive := 5;
constant sys_conf_clksys_vcodivide : positive := 25;
constant sys_conf_clksys_vcomultiply : positive := 18; -- dcm 72 MHz
constant sys_conf_clksys_outdivide : positive := 1; -- sys 72 MHz
constant sys_conf_clksys_gentype : string := "DCM";
constant sys_conf_memctl_read0delay : positive := 4;
constant sys_conf_memctl_read1delay : positive := sys_conf_memctl_read0delay;
constant sys_conf_memctl_writedelay : positive := 5;
@@ -69,7 +73,8 @@ package sys_conf is
-- derived constants
constant sys_conf_clksys : integer :=
(100000000/sys_conf_clkfx_divide)*sys_conf_clkfx_multiply;
((100000000/sys_conf_clksys_vcodivide)*sys_conf_clksys_vcomultiply) /
sys_conf_clksys_outdivide;
constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000;
constant sys_conf_ser2rri_cdinit : integer :=

18
rtl/sys_gen/w11a/nexys3/sys_w11a_n3.ucf_cpp
View File

@@ -1,7 +1,8 @@
## $Id: sys_w11a_n3.ucf_cpp 509 2013-04-21 20:46:20Z mueller $
## $Id: sys_w11a_n3.ucf_cpp 540 2013-10-13 18:42:50Z mueller $
##
## Revision History:
## Date Rev Version Comment
## 2013-10-13 540 1.1 add pad->clk and fx2 cdc constraints
## 2013-04-21 509 1.1 add fx2 support
## 2011-11-20 430 1.0 Initial version
##
@@ -11,11 +12,24 @@ TIMESPEC "TS_I_CLK100" = PERIOD "I_CLK100" 10.0 ns HIGH 50 %;
OFFSET = IN 10 ns BEFORE "I_CLK100";
OFFSET = OUT 20 ns AFTER "I_CLK100";
## constrain pad->net clock delay
NET CLK TNM = TNM_CLK;
TIMESPEC TS_PAD_CLK=FROM PADS(I_CLK100) TO TNM_CLK 10 ns;
NET I_FX2_IFCLK_BUFGP TNM = TNM_IFCLK;
TIMESPEC TS_PAD_IFCLK=FROM PADS(I_FX2_IFCLK) TO TNM_IFCLK 10 ns;
## FX2 controller specific constraints
## constrain cdc path in fifos and reset
TIMESPEC TS_CDC_FIFO =
FROM FFS(*FIFO/GC?/GRAY_*.CNT/R_DATA*)
TO FFS(*FIFO/R_REG?_?addr_c*)
5 ns DATAPATHONLY;
## std board
##
#include "bplib/nexys3/nexys3_pins.ucf"
##
## Pmod B0 - RS232
## Pmod B0 - RS232
##
#include "bplib/nexys3/nexys3_pins_pmb0_rs232.ucf"
##

4
rtl/sys_gen/w11a/nexys3/sys_w11a_n3.vbom
View File

@@ -15,8 +15,8 @@
../../../w11a/pdp11.vhd
sys_conf = sys_conf.vhd
# components
[xst,isim]../../../vlib/xlib/dcm_sfs_unisim_s3e.vbom
[ghdl]../../../vlib/xlib/dcm_sfs_gsim.vbom
[xst,isim]../../../vlib/xlib/s6_cmt_sfs_unisim.vbom
[ghdl]../../../vlib/xlib/s6_cmt_sfs_gsim.vbom
../../../vlib/genlib/clkdivce.vbom
../../../bplib/bpgen/bp_rs232_2l4l_iob.vbom
../../../bplib/bpgen/sn_humanio_rbus.vbom

19
rtl/sys_gen/w11a/nexys3/sys_w11a_n3.vhd
View File

@@ -1,4 +1,4 @@
-- $Id: sys_w11a_n3.vhd 509 2013-04-21 20:46:20Z mueller $
-- $Id: sys_w11a_n3.vhd 538 2013-10-06 17:21:25Z mueller $
--
-- Copyright 2011-2013 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@@ -15,7 +15,7 @@
-- Module Name: sys_w11a_n3 - syn
-- Description: w11a test design for nexys3
--
-- Dependencies: vlib/xlib/dcm_sfs
-- Dependencies: vlib/xlib/s6_cmt_sfs
-- vlib/genlib/clkdivce
-- bplib/bpgen/bp_rs232_2l4l_iob
-- bplib/bpgen/sn_humanio_rbus
@@ -37,7 +37,7 @@
-- Test bench: tb/tb_sys_w11a_n3
--
-- Target Devices: generic
-- Tool versions: xst 13.1; ghdl 0.29
-- Tool versions: xst 13.1, 14.6; ghdl 0.29
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
@@ -47,6 +47,7 @@
--
-- Revision History:
-- Date Rev Version Comment
-- 2013-10-06 538 1.5 pll support, use clksys_vcodivide ect
-- 2013-04-21 509 1.4 added fx2 (cuff) support
-- 2011-12-18 440 1.0.4 use rlink_sp1c
-- 2011-12-04 435 1.0.3 increase ATOWIDTH 6->7 (saw i/o timeouts on wblks)
@@ -241,11 +242,15 @@ begin
report "assert sys_conf_clksys on MHz grid"
severity failure;
DCM : dcm_sfs
GEN_CLKSYS : s6_cmt_sfs
generic map (
CLKFX_DIVIDE => sys_conf_clkfx_divide,
CLKFX_MULTIPLY => sys_conf_clkfx_multiply,
CLKIN_PERIOD => 10.0)
VCO_DIVIDE => sys_conf_clksys_vcodivide,
VCO_MULTIPLY => sys_conf_clksys_vcomultiply,
OUT_DIVIDE => sys_conf_clksys_outdivide,
CLKIN_PERIOD => 10.0,
CLKIN_JITTER => 0.01,
STARTUP_WAIT => false,
GEN_TYPE => sys_conf_clksys_gentype)
port map (
CLKIN => I_CLK100,
CLKFX => CLK,

20
rtl/sys_gen/w11a/nexys3/tb/sys_conf_sim.vhd
View File

@@ -1,4 +1,4 @@
-- $Id: sys_conf_sim.vhd 509 2013-04-21 20:46:20Z mueller $
-- $Id: sys_conf_sim.vhd 538 2013-10-06 17:21:25Z mueller $
--
-- Copyright 2011-2013 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@@ -16,9 +16,10 @@
-- Description: Definitions for sys_w11a_n3 (for simulation)
--
-- Dependencies: -
-- Tool versions: xst 13.1; ghdl 0.29
-- Tool versions: xst 13.1, 14.6; ghdl 0.29
-- Revision History:
-- Date Rev Version Comment
-- 2013-10-06 538 1.3 pll support, use clksys_vcodivide ect
-- 2013-04-21 509 1.2 add fx2 settings
-- 2011-11-25 432 1.0 Initial version (cloned from _n3)
------------------------------------------------------------------------------
@@ -30,14 +31,14 @@ use work.slvtypes.all;
package sys_conf is
constant sys_conf_clkfx_divide : positive := 1;
constant sys_conf_clkfx_multiply : positive := 1; -- no dcm in sim...
-- constant sys_conf_clkfx_divide : positive := 5;
-- constant sys_conf_clkfx_multiply : positive := 4; -- ==> 80 MHz
constant sys_conf_clksys_vcodivide : positive := 25;
constant sys_conf_clksys_vcomultiply : positive := 18; -- dcm 72 MHz
constant sys_conf_clksys_outdivide : positive := 1; -- sys 72 MHz
constant sys_conf_clksys_gentype : string := "DCM";
constant sys_conf_memctl_read0delay : positive := 6; -- for 100 MHz
constant sys_conf_memctl_read0delay : positive := 4; -- for <75 MHz
constant sys_conf_memctl_read1delay : positive := sys_conf_memctl_read0delay;
constant sys_conf_memctl_writedelay : positive := 7;
constant sys_conf_memctl_writedelay : positive := 5;
constant sys_conf_ser2rri_cdinit : integer := 1-1; -- 1 cycle/bit in sim
@@ -61,7 +62,8 @@ package sys_conf is
-- derived constants
constant sys_conf_clksys : integer :=
(100000000/sys_conf_clkfx_divide)*sys_conf_clkfx_multiply;
((100000000/sys_conf_clksys_vcodivide)*sys_conf_clksys_vcomultiply) /
sys_conf_clksys_outdivide;
constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000;
end package sys_conf;

4
rtl/vlib/xlib/dcm_sfs_unisim_s3e.vhd
View File

@@ -1,4 +1,4 @@
-- $Id: dcm_sfs_unisim_s3e.vhd 426 2011-11-18 18:14:08Z mueller $
-- $Id: dcm_sfs_unisim_s3e.vhd 534 2013-09-22 21:37:24Z mueller $
--
-- Copyright 2010-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@@ -18,7 +18,7 @@
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic Spartan-3A,-3E
-- Target Devices: generic Spartan-3A,-3E; Spartan-6
-- Tool versions: xst 12.1; ghdl 0.29
--
-- Revision History:

4
rtl/vlib/xlib/s6_cmt_sfs_gsim.vbom Normal file
View File

@@ -0,0 +1,4 @@
# libs
../slvtypes.vhd
# design
s6_cmt_sfs_gsim.vhd

202
rtl/vlib/xlib/s6_cmt_sfs_gsim.vhd Normal file
View File

@@ -0,0 +1,202 @@
-- $Id: s6_cmt_sfs_gsim.vhd 556 2014-05-29 19:01:39Z mueller $
--
-- Copyright 2013- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: s6_cmt_sfs - sim
-- Description: Spartan-6 CMT for simple frequency synthesis
-- simple vhdl model, without Xilinx UNISIM primitives
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic Spartan-6
-- Tool versions: xst 14.5, 14.6; ghdl 0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2013-10-06 538 1.0 Initial version (derived from s7_cmt_sfs_gsim)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
entity s6_cmt_sfs is -- Spartan-6 CMT for simple freq. synth.
generic (
VCO_DIVIDE : positive := 1; -- vco clock divide
VCO_MULTIPLY : positive := 1; -- vco clock multiply
OUT_DIVIDE : positive := 1; -- output divide
CLKIN_PERIOD : real := 10.0; -- CLKIN period (def is 10.0 ns)
CLKIN_JITTER : real := 0.01; -- CLKIN jitter (def is 10 ps)
STARTUP_WAIT : boolean := false; -- hold FPGA startup till LOCKED
GEN_TYPE : string := "PLL"); -- PLL or MMCM
port (
CLKIN : in slbit; -- clock input
CLKFX : out slbit; -- clock output (synthesized freq.)
LOCKED : out slbit -- pll/mmcm locked
);
end s6_cmt_sfs;
architecture sim of s6_cmt_sfs is
signal CLK_DIVPULSE : slbit := '0';
signal CLKOUT_PERIOD : time := 0 ns;
signal R_CLKOUT : slbit := '0';
signal R_LOCKED : slbit := '0';
begin
proc_init : process
-- currently frequency limits taken from Spartan-6 speed grade -2
constant f_vcomin_pll : integer := 400;
constant f_vcomax_pll : integer := 1000;
constant f_pdmin_pll : integer := 19;
constant f_pdmax_pll : integer := 375;
variable t_vco : time := 0 ns;
variable t_vcomin : time := 0 ns;
variable t_vcomax : time := 0 ns;
variable t_pd : time := 0 ns;
variable t_pdmin : time := 0 ns;
variable t_pdmax : time := 0 ns;
begin
-- validate generics
if not (GEN_TYPE = "PLL" or GEN_TYPE = "DCM") then
assert false
report "assert(GEN_TYPE='PLL' or GEN_TYPE='DCM')"
severity failure;
end if;
if VCO_DIVIDE/=1 or VCO_MULTIPLY/=1 or OUT_DIVIDE/=1 then
if GEN_TYPE = "PLL" then
-- check DIV/MULT parameter range
if VCO_DIVIDE<1 or VCO_DIVIDE>52 or
VCO_MULTIPLY<1 or VCO_MULTIPLY>64 or
OUT_DIVIDE<1 or OUT_DIVIDE>128
then
assert false
report
"assert(VCO_DIVIDE in 1:52 VCO_MULTIPLY in 1:64 OUT_DIVIDE in 1:128)"
severity failure;
end if;
-- setup VCO and PD range check boundaries
t_vcomin := (1000 ns / f_vcomax_pll) - 1 ps;
t_vcomax := (1000 ns / f_vcomin_pll) + 1 ps;
t_pdmin := (1000 ns / f_pdmax_pll) - 1 ps;
t_pdmax := (1000 ns / f_pdmin_pll) + 1 ps;
-- now check whether VCO and PD frequency is in range
t_pd := (1 ps * (1000.0*CLKIN_PERIOD)) * VCO_DIVIDE;
t_vco := t_pd / VCO_MULTIPLY;
if t_vco<t_vcomin or t_vco>t_vcomax then
assert false
report "assert(VCO frequency out of range)"
severity failure;
end if;
if t_pd<t_pdmin or t_pd>t_pdmax then
assert FALSE
report "assert(PD frequency out of range)"
severity failure;
end if;
end if; -- GEN_TYPE = "PLL"
if GEN_TYPE = "DCM" then
-- check DIV/MULT parameter range
if VCO_DIVIDE<1 or VCO_DIVIDE>32 or
VCO_MULTIPLY<2 or VCO_MULTIPLY>32 or
OUT_DIVIDE/=1
then
assert false
report
"assert(VCO_DIVIDE in 1:32 VCO_MULTIPLY in 2:32 OUT_DIVIDE=1)"
severity failure;
end if;
end if; -- GEN_TYPE = "MMCM"
end if; -- one factor /= 1
wait;
end process proc_init;
proc_clkin : process (CLKIN)
variable t_lastclkin : time := 0 ns;
variable t_lastperiod : time := 0 ns;
variable t_period : time := 0 ns;
variable nclkin : integer := 1;
begin
if CLKIN'event then
if CLKIN = '1' then -- if CLKIN rising edge
if t_lastclkin > 0 ns then
t_lastperiod := t_period;
t_period := now - t_lastclkin;
CLKOUT_PERIOD <= (t_period * VCO_DIVIDE * OUT_DIVIDE) / VCO_MULTIPLY;
if t_lastperiod > 0 ns and abs(t_period-t_lastperiod) > 1 ps then
report "s6_cmt_sp_sfs: CLKIN unstable" severity warning;
end if;
end if;
t_lastclkin := now;
if t_period > 0 ns then
nclkin := nclkin - 1;
if nclkin <= 0 then
nclkin := VCO_DIVIDE * OUT_DIVIDE;
CLK_DIVPULSE <= '1';
R_LOCKED <= '1';
end if;
end if;
else -- if CLKIN falling edge
CLK_DIVPULSE <= '0';
end if;
end if;
end process proc_clkin;
proc_clkout : process
variable t_lastclkin : time := 0 ns;
variable t_lastperiod : time := 0 ns;
variable t_period : time := 0 ns;
variable nclkin : integer := 1;
begin
loop
wait until CLK_DIVPULSE = '1';
for i in 1 to VCO_MULTIPLY loop
R_CLKOUT <= '1';
wait for CLKOUT_PERIOD/2;
R_CLKOUT <= '0';
if i /= VCO_MULTIPLY then
wait for CLKOUT_PERIOD/2;
end if;
end loop; -- i
end loop;
end process proc_clkout;
CLKFX <= R_CLKOUT;
LOCKED <= R_LOCKED;
end sim;

5
rtl/vlib/xlib/s6_cmt_sfs_unisim.vbom Normal file
View File

@@ -0,0 +1,5 @@
# libs
../slvtypes.vhd
@lib:unisim
# design
s6_cmt_sfs_unisim.vhd

147
rtl/vlib/xlib/s6_cmt_sfs_unisim.vhd Normal file
View File

@@ -0,0 +1,147 @@
-- $Id: $
--
-- Copyright 2013- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: s6_cmt_sfs - syn
-- Description: Spartan-6 CMT for simple frequency synthesis
-- Direct instantiation of Xilinx UNISIM primitives
--
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic Spartan-6
-- Tool versions: xst 14.5; ghdl 0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2013-10-05 537 1.0 Initial version (derived from s7_cmt_sfs)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.ALL;
use work.slvtypes.all;
entity s6_cmt_sfs is -- Spartan-6 CMT for simple freq. synth.
generic (
VCO_DIVIDE : positive := 1; -- vco clock divide
VCO_MULTIPLY : positive := 1; -- vco clock multiply
OUT_DIVIDE : positive := 1; -- output divide
CLKIN_PERIOD : real := 10.0; -- CLKIN period (def is 10.0 ns)
CLKIN_JITTER : real := 0.01; -- CLKIN jitter (def is 10 ps)
STARTUP_WAIT : boolean := false; -- hold FPGA startup till LOCKED
GEN_TYPE : string := "PLL"); -- PLL or DCM
port (
CLKIN : in slbit; -- clock input
CLKFX : out slbit; -- clock output (synthesized freq.)
LOCKED : out slbit -- pll/dcm locked
);
end s6_cmt_sfs;
architecture syn of s6_cmt_sfs is
begin
assert GEN_TYPE = "PLL" or GEN_TYPE = "DCM"
report "assert(GEN_TYPE='PLL' or GEN_TYPE='DCM')"
severity failure;
NOGEN: if VCO_DIVIDE=1 and VCO_MULTIPLY=1 and OUT_DIVIDE=1 generate
CLKFX <= CLKIN;
LOCKED <= '1';
end generate NOGEN;
USEPLL: if GEN_TYPE = "PLL" and
not(VCO_DIVIDE=1 and VCO_MULTIPLY=1 and OUT_DIVIDE=1) generate
signal CLKFBOUT : slbit;
signal CLKOUT0 : slbit;
signal CLKOUT1_UNUSED : slbit;
signal CLKOUT2_UNUSED : slbit;
signal CLKOUT3_UNUSED : slbit;
signal CLKOUT4_UNUSED : slbit;
signal CLKOUT5_UNUSED : slbit;
begin
PLL : pll_base
generic map (
BANDWIDTH => "OPTIMIZED",
CLK_FEEDBACK => "CLKFBOUT",
COMPENSATION => "INTERNAL",
DIVCLK_DIVIDE => VCO_DIVIDE,
CLKFBOUT_MULT => VCO_MULTIPLY,
CLKFBOUT_PHASE => 0.000,
CLKOUT0_DIVIDE => OUT_DIVIDE,
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKIN_PERIOD => CLKIN_PERIOD,
REF_JITTER => CLKIN_JITTER)
port map (
CLKFBOUT => CLKFBOUT,
CLKOUT0 => CLKOUT0,
CLKOUT1 => CLKOUT1_UNUSED,
CLKOUT2 => CLKOUT2_UNUSED,
CLKOUT3 => CLKOUT3_UNUSED,
CLKOUT4 => CLKOUT4_UNUSED,
CLKOUT5 => CLKOUT5_UNUSED,
CLKFBIN => CLKFBOUT,
CLKIN => CLKIN,
LOCKED => LOCKED,
RST => '0'
);
BUFG_CLKOUT : bufg
port map (
I => CLKOUT0,
O => CLKFX
);
end generate USEPLL;
USEDCM: if GEN_TYPE = "DCM" and
not(VCO_DIVIDE=1 and VCO_MULTIPLY=1 and OUT_DIVIDE=1) generate
signal CLKOUT0 : slbit;
begin
DCM : dcm_sp
generic map (
CLK_FEEDBACK => "NONE",
CLKFX_DIVIDE => VCO_DIVIDE,
CLKFX_MULTIPLY => VCO_MULTIPLY,
CLKIN_DIVIDE_BY_2 => false,
CLKIN_PERIOD => CLKIN_PERIOD,
CLKOUT_PHASE_SHIFT => "NONE",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
DSS_MODE => "NONE",
STARTUP_WAIT => STARTUP_WAIT)
port map (
CLKIN => CLKIN,
CLKFX => CLKOUT0,
LOCKED => LOCKED
);
BUFG_CLKOUT : bufg
port map (
I => CLKOUT0,
O => CLKFX
);
end generate USEDCM;
end syn;

42
rtl/vlib/xlib/xlib.vhd
View File

@@ -1,6 +1,6 @@
-- $Id: xlib.vhd 432 2011-11-25 20:16:28Z mueller $
-- $Id: xlib.vhd 538 2013-10-06 17:21:25Z mueller $
--
-- Copyright 2007-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2007-2013 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
@@ -16,9 +16,11 @@
-- Description: Xilinx specific components
--
-- Dependencies: -
-- Tool versions: xst 8.2, 9.1, 9.2, 13.1; ghdl 0.18-0.29
-- Tool versions: xst 8.2, 9.1, 9.2, 13.1, 14.5, 14.6; ghdl 0.18-0.29
-- Revision History:
-- Date Rev Version Comment
-- 2013-10-06 538 1.0.10 add s6_cmt_sfs
-- 2013-09-28 535 1.0.9 add s7_cmt_sfs
-- 2011-11-24 432 1.0.8 add iob_oddr2_simple
-- 2011-11-17 426 1.0.7 rename dcm_sp_sfs -> dcm_sfs; remove family generic
-- 2011-11-10 423 1.0.6 add family generic for dcm_sp_sfs
@@ -171,7 +173,7 @@ end component;
component dcm_sfs is -- DCM for simple frequency synthesis
generic (
CLKFX_DIVIDE : positive := 2; -- FX clock divide (1-32)
CLKFX_MULTIPLY : positive := 2; -- FX clock divide (2-32)
CLKFX_MULTIPLY : positive := 2; -- FX clock multiply (2-32) (1->no DCM)
CLKIN_PERIOD : real := 20.0); -- CLKIN period (def is 20.0 ns)
port (
CLKIN : in slbit; -- clock input
@@ -180,4 +182,36 @@ component dcm_sfs is -- DCM for simple frequency synthesis
);
end component;
component s7_cmt_sfs is -- 7-Series CMT for simple freq. synth.
generic (
VCO_DIVIDE : positive := 1; -- vco clock divide
VCO_MULTIPLY : positive := 1; -- vco clock multiply
OUT_DIVIDE : positive := 1; -- output divide
CLKIN_PERIOD : real := 10.0; -- CLKIN period (def is 10.0 ns)
CLKIN_JITTER : real := 0.01; -- CLKIN jitter (def is 10 ps)
STARTUP_WAIT : boolean := false; -- hold FPGA startup till LOCKED
GEN_TYPE : string := "PLL"); -- PLL or MMCM
port (
CLKIN : in slbit; -- clock input
CLKFX : out slbit; -- clock output (synthesized freq.)
LOCKED : out slbit -- pll/mmcm locked
);
end component;
component s6_cmt_sfs is -- Spartan-6 CMT for simple freq. synth.
generic (
VCO_DIVIDE : positive := 1; -- vco clock divide
VCO_MULTIPLY : positive := 1; -- vco clock multiply
OUT_DIVIDE : positive := 1; -- output divide
CLKIN_PERIOD : real := 10.0; -- CLKIN period (def is 10.0 ns)
CLKIN_JITTER : real := 0.01; -- CLKIN jitter (def is 10 ps)
STARTUP_WAIT : boolean := false; -- hold FPGA startup till LOCKED
GEN_TYPE : string := "PLL"); -- PLL or DCM
port (
CLKIN : in slbit; -- clock input
CLKFX : out slbit; -- clock output (synthesized freq.)
LOCKED : out slbit -- pll/mmcm locked
);
end component;
end package xlib;

7
rtl/w11a/pdp11_core_rbus.vhd
View File

@@ -1,6 +1,6 @@
-- $Id: pdp11_core_rbus.vhd 427 2011-11-19 21:04:11Z mueller $
-- $Id: pdp11_core_rbus.vhd 553 2014-03-17 06:40:08Z mueller $
--
-- Copyright 2007-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2007-2014 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
@@ -68,6 +68,9 @@
-- bbb00011 psw r/w/- processor status word access
-- bbb00100 al r/w/- address register, low
-- bbb00101 ah r/w/- address register, high
-- 7 ubm r/w/- ubmap access
-- 6 p22 r/w/- 22bit access
-- 5: 0 addr r/w/- addr(21:16)
-- bbb00110 mem r/w/- memory access
-- bbb00111 memi r/w/- memory access, inc address
-- bbb01rrr gpr[] r/w/- general purpose regs

12
rtl/w11a/pdp11_sequencer.vhd
View File

@@ -1,6 +1,6 @@
-- $Id: pdp11_sequencer.vhd 427 2011-11-19 21:04:11Z mueller $
-- $Id: pdp11_sequencer.vhd 556 2014-05-29 19:01:39Z mueller $
--
-- Copyright 2006-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2006-2014 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
@@ -18,10 +18,11 @@
-- Dependencies: ib_sel
-- Test bench: tb/tb_pdp11_core (implicit)
-- Target Devices: generic
-- Tool versions: xst 8.2, 9.1, 9.2, 12.1, 13.1; ghdl 0.18-0.29
-- Tool versions: xst 8.2-14.7; viv 2014.1; ghdl 0.18-0.29
--
-- Revision History:
-- Date Rev Version Comment
-- 2014-04-20 554 1.5 now vivado compatible (add dummy assigns in procs)
-- 2011-11-18 427 1.4.2 now numeric_std clean
-- 2010-10-23 335 1.4.1 use ib_sel
-- 2010-10-17 333 1.4 use ibus V2 interface
@@ -412,6 +413,8 @@ begin
nstatus : inout cpustat_type;
mok : out boolean) is
begin
nstate := nstate; -- dummy to add driver (vivado)
nstatus := nstatus; -- "
mok := false;
if VM_STAT.ack = '1' then
mok := true;
@@ -429,6 +432,7 @@ begin
isdef : in slbit;
regnum : in slv3) is
begin
ndpcntl := ndpcntl; -- dummy to add driver (vivado)
if bytop='0' or isdef='1' or
regnum=c_gpr_pc or regnum=c_gpr_sp then
ndpcntl.ounit_const := "000000010";
@@ -503,6 +507,8 @@ begin
nvmcntl : inout vm_cntl_type;
nmmumoni : inout mmu_moni_type) is
begin
ndpcntl := ndpcntl; -- dummy to add driver (vivado)
nvmcntl := nvmcntl; -- "
nmmumoni.idone := '1';
if unsigned(INT_PRI) > unsigned(PSW.pri) then
nstate := s_idle;

1
tools/asm-11/tests-err/Makefile
View File

@@ -1,3 +1,4 @@
# $Id: Makefile 525 2013-07-06 12:19:39Z mueller $
#
# Revision History:
# Date Rev Version Comment

1
tools/asm-11/tests/Makefile
View File

@@ -1,3 +1,4 @@
# $Id: Makefile 525 2013-07-06 12:19:39Z mueller $
#
# Revision History:
# Date Rev Version Comment

14
tools/asm-11/tests/test_0040_asci.mac
View File

@@ -1,4 +1,4 @@
; $Id: test_0040_asci.mac 501 2013-03-30 13:53:39Z mueller $
; $Id: test_0040_asci.mac 548 2014-01-12 09:48:47Z mueller $
;
; test .ascii/.asciz
;
@@ -8,14 +8,14 @@
.asect
.blkw 400
.ascii /foobar/
.asciz /fooba/
.ascii /foobar/ ;;!! 001000:
.asciz /fooba/ ;;!! 001006:
a0: .ascii /test/
a1: .asciz /test1/
a0: .ascii /test/ ;;!! 001014:
a1: .asciz /test1/ ;;!! 001020:
a2: .ascii <CR><LF>/test/
a3: .asciz /test/<CR><LF>
a2: .ascii <CR><LF>/test/ ;;!! 001026:
a3: .asciz /test/<CR><LF> ;;!! 001034:
a4: .asciz <CR><LF>/retro/<CR><LF>|computing|
a5: .ascii /Hello World!/

1
tools/asm-11/w11/sys/dl11/Makefile
View File

@@ -1,3 +1,4 @@
# $Id: Makefile 525 2013-07-06 12:19:39Z mueller $
#
# Revision History:
# Date Rev Version Comment

31
tools/asm-11/w11/sys/dl11/noboot.mac Normal file
View File

@@ -0,0 +1,31 @@
; $Id: noboot.mac 521 2013-05-20 22:16:45Z mueller $
;
; Boot blocker, when loaded and started at 0, writes
; This is not a hardware bootable disk
;
RCSR = 177560
RBUF = 177562
XCSR = 177564
XBUF = 177566
;
CR = 015
LF = 012
;
; starts at 0 !
;
.asect
. = 0
;
start: mov #text, r0
1$: tstb (r0)
beq 3$
2$: tstb @#XCSR
bpl 2$
movb (r0)+,@#XBUF
br 1$
3$: halt
;
. = 100
text: .asciz /This is not a hardware bootable disk/<CR><LF>
;
.end

6
tools/bin/asm-11
View File

@@ -1,5 +1,5 @@
#!/usr/bin/perl -w
# $Id: asm-11 503 2013-04-06 19:44:13Z mueller $
# $Id: asm-11 547 2013-12-29 13:10:07Z mueller $
#
# Copyright 2013- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
#
@@ -2447,8 +2447,8 @@ sub savestr1 {
#-------------------------------------------------------------------------------
sub print_help {
print "usage: asm-11 <file>\n";
print " --I path adds path to the .include search path\n";
print "usage: asm-11 [OPTIONS]... [FILE]...\n";
print " --I=path adds path to the .include search path\n";
print " --lst create listing (default file name)\n";
print " --olst=fnam create listing (concrete file name)\n";
print " --lda create absolute loader output (default file name)\n";

9
tools/bin/config_wrapper
View File

@@ -1,5 +1,5 @@
#!/usr/bin/perl -w
# $Id: config_wrapper 467 2013-01-02 19:49:05Z mueller $
# $Id: config_wrapper 534 2013-09-22 21:37:24Z mueller $
#
# Copyright 2010-2013 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
#
@@ -14,6 +14,7 @@
#
# Revision History:
# Date Rev Version Comment
# 2013-09-21 534 1.1.8 add nexys4 support
# 2013-01-02 467 1.1.7 jconfig: prepend '0x' to support 'jtag #2007'
# 2012-02-11 457 1.1.6 jconfig: use RETRO_FX2_VID/PID for USB VID/PID
# 2011-12-03 435 1.1.5 add nexys3 support;
@@ -47,6 +48,7 @@ if (not defined $opts{path}) {
$opts{path} = "xc3s1000" if $opts{board} eq "s3board";
$opts{path} = "xc3s1200e" if $opts{board} eq "nexys2";
$opts{path} = "xc6slx16" if $opts{board} eq "nexys3";
$opts{path} = "xc7a100t" if $opts{board} eq "nexys4";
$opts{path} = "xc6slx45" if $opts{board} eq "atlys";
$opts{path} = "xc6slx45t" if $opts{board} eq "sp605";
}
@@ -93,6 +95,10 @@ if ($board eq "s3board" && $ipath eq "xc3s200") { # S3BOARD-200
@plist = ($ipath);
$pfpga = 1;
} elsif ($board eq "nexys4" && $ipath eq "xc7a100t") { # nexys4
@plist = ($ipath);
$pfpga = 1;
} elsif ($board eq "atlys" && $ipath eq "xc6slx45") { # atlys
@plist = ($ipath);
$pfpga = 1;
@@ -112,6 +118,7 @@ foreach my $part (@plist) {
elsif ($part =~ m/^xc3s\d*$/) { push @blist, "spartan3/data" } # s-3
elsif ($part =~ m/^xc3s\d*e$/) { push @blist, "spartan3e/data" } # s-3e
elsif ($part =~ m/^xc6slx\d*t?$/) { push @blist, "spartan6/data" }# s-6 lx
elsif ($part =~ m/^xc7a\d*t?$/) { push @blist, "artix7/data" } # 7-a
elsif ($part =~ m/^xccace$/) { push @blist, "acempm/data" } # sys-ace
else {
print STDERR "config_wrapper-E: no bsdl path known for $part\n";

267
tools/bin/create_disk Executable file
View File

@@ -0,0 +1,267 @@
#!/usr/bin/perl -w
# $Id: create_disk 522 2013-05-24 17:50:29Z mueller $
#
# Copyright 2013- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
#
# This program is free software; you may redistribute and/or modify it under
# the terms of the GNU General Public License as published by the Free
# Software Foundation, either version 2, or at your option any later version.
#
# This program is distributed in the hope that it will be useful, but
# WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
# or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
# for complete details.
#
# Revision History:
# Date Rev Version Comment
# 2013-05-20 521 1.0 First draft
#
use 5.10.0; # require Perl 5.10 or higher
use strict; # require strict checking
use Getopt::Long;
use FileHandle;
use Fcntl qw(:seek);
my %opts = ();
GetOptions(\%opts, "help", "typ=s", "ini=s", "bad", "boot"
)
or exit 1;
sub do_inipatt;
sub do_badtable;
sub do_noboot;
sub print_help;
# disk type table
my %disktype = (
RK05 => {cyl=> 203, hd=> 2, sec=> 12, bps=> 512, bad=>0},
RL01 => {cyl=> 256, hd=> 2, sec=> 40, bps=> 256, bad=>1},
RL02 => {cyl=> 512, hd=> 2, sec=> 40, bps=> 256, bad=>1},
RP06 => {cyl=> 815, hd=> 19, sec=> 22, bps=> 512, bad=>1}
);
autoflush STDOUT 1 if (-p STDOUT); # autoflush if output into pipe
if (exists $opts{help}) {
print_help(1);
exit 0;
}
if (scalar(@ARGV) != 1) {
print STDERR "create_disk-E: specify one and only one output file\n";
print_help(0);
exit 1;
}
my $fnam = shift @ARGV;
if (-e $fnam) {
print STDERR "create_disk-E: file '$fnam' exists already\n";
exit 1;
}
my $typ = uc($opts{typ});
unless (defined $typ && exists $disktype{$typ}) {
print STDERR "create_disk-E: no or invalid --typ specification, use --help\n";
exit 1;
}
my $cyl = $disktype{$typ}{cyl};
my $hd = $disktype{$typ}{hd};
my $sec = $disktype{$typ}{sec};
my $bps = $disktype{$typ}{bps};
my $bad = $disktype{$typ}{bad};
if ($opts{bad} && !$bad) {
print STDERR "create_disk-E: --bad not supported for type '$typ', abort\n";
exit 1;
}
my $nblk = $cyl*$hd*$sec;
my $cap = $nblk * $bps;
my $fh = new FileHandle;
sysopen($fh, $fnam, O_RDWR|O_CREAT)
or die "failed to create '$fnam': $!";
# seek to end, wrte 1 byte at end
my $rc = $fh->seek($cap-1, SEEK_SET);
if (not $rc) {die "seek failed: $!";}
my $buf = pack('C1',0);
$rc = syswrite($fh, $buf, length($buf));
if ($rc<=0) {die "write failed: $!";}
# handle init patterns
do_inipatt if $opts{ini};
# handle factory bad block table
do_badtable if $opts{bad};
# write dummy boot block
do_noboot if $opts{noboot};
#-------------------------------------------------------------------------------
sub do_inipatt {
my $ini = $opts{ini};
if ($ini eq 'zero' ||$ini eq 'ones' || $ini eq 'dead') {
my @dat;
for (my $i=0; $i<$bps/4; $i++) {
push @dat, 0,0 if $ini eq 'zero';
push @dat, -1,-1 if $ini eq 'ones';
push @dat, 0xdead,0xbeaf if $ini eq 'dead';
}
my $buf = pack('v*',@dat);
my $rc = $fh->seek(0, SEEK_SET);
if (not $rc) {die "seek failed: $!";}
for (my $i=0; $i<$nblk; $i++) {
$rc = syswrite($fh, $buf, length($buf));
if ($rc<=0) {die "write failed: $!";}
}
} elsif ($ini eq 'test') {
my $addr = 0;
my $cur_sec = 0;
my $cur_trk = 0;
my $cur_cyl = 0;
my $rc = $fh->seek(0, SEEK_SET);
if (not $rc) {die "seek failed: $!";}
for (my $i=0; $i<$nblk; $i++) {
my @dat;
for (my $i=0; $i<$bps/16; $i++) {
push @dat, ($addr & 0xffff);
push @dat, (($addr>>16) & 0xffff);
push @dat, $cur_cyl, $cur_trk, $cur_sec;
push @dat, $cyl, $hd, $sec;
$addr += 16;
}
my $buf = pack('v*',@dat);
$rc = syswrite($fh, $buf, length($buf));
if ($rc<=0) {die "write failed: $!";}
$cur_sec += 1;
if ($cur_sec >= $sec) {
$cur_sec = 0;
$cur_trk += 1;
if ($cur_trk >= $hd) {
$cur_trk = 0;
$cur_cyl += 1;
}
}
}
} else {
print STDERR "create_disk-W: unknown --ini mode '$ini', --ini ignored\n";
}
return;
}
#-------------------------------------------------------------------------------
sub do_badtable {
my @dat;
push @dat, 012345, 012345; # pack number
push @dat, 0,0; # dummy c/s/h spec
for (my $i=4; $i<$bps/2; $i++) {
push @dat, -1; # end of table
}
my $buf = pack('v*',@dat);
my $pos = $cap - $sec*$bps; # position of last track
my $rc = $fh->seek($pos, SEEK_SET);
if (not $rc) {die "seek failed: $!";}
my $nsec = ($sec > 10) ? 10 : $sec; # write last track, at most 10 sec
for (my $i=0; $i<$nsec; $i++) {
$rc = syswrite($fh, $buf, length($buf));
if ($rc<=0) {die "write failed: $!";}
}
return;
}
#-------------------------------------------------------------------------------
sub do_noboot {
my @dat;
push @dat, 0012700, 0000100; # start: mov #text, r0
push @dat, 0105710; # 1$: tstb (r0)
push @dat, 0001406; # beq 3$
push @dat, 0105737, 0177564; # 2$: tstb @#XCSR
push @dat, 0100375; # bpl 2$
push @dat, 0112037, 0177566; # movb (r0)+,@#XBUF
push @dat, 0000770; # br 1$
push @dat, 0000000; # 3$: halt
my $buf = pack('v*',@dat);
my $rc = $fh->seek(0, SEEK_SET);
if (not $rc) {die "seek failed: $!";}
$rc = syswrite($fh, $buf, length($buf));
if ($rc<=0) {die "write failed: $!";}
$buf = "\r\n";
$buf .= "\r\n";
$buf .= "++======================================++\r\n";
$buf .= "|| This is not a hardware bootable disk ||\r\n";
$buf .= "++======================================++\r\n";
$buf .= "\r\n";
$buf .= "Disk image created with 'create_disk --typ=$typ':\r\n";
$buf .= sprintf " number of cylinders: %6d\r\n", $cyl;
$buf .= sprintf " tracks per cylinder: %6d\r\n", $hd;
$buf .= sprintf " sectors per track: %6d\r\n", $sec;
$buf .= sprintf " block size: %6d\r\n", $bps;
$buf .= sprintf " total number of sectors: %6d\r\n", $nblk;
$buf .= sprintf " capacity in kByte: %6d\r\n", $cap/1024;
$buf .= "\r\n";
$buf .= "CPU WILL HALT\r\n";
$buf .= "\r\n";
# NOTE: the text above almost fills the first 512 bytes !!
# don't any more text, all has been said anyway !!
$rc = $fh->seek(0100, SEEK_SET);
if (not $rc) {die "seek failed: $!";}
$rc = syswrite($fh, $buf, length($buf));
if ($rc<=0) {die "write failed: $!";}
return;
}
#-------------------------------------------------------------------------------
sub print_help {
my ($ptyp) = @_;
print "usage: create_disk [options] <file>\n";
print " --typ=<type> specified disk type, must be specified\n";
print " --ini=<pat> initialization pattern, can be\n";
print " --bad create factory bad block table on last track\n";
print " --boot write dummy boot block, print volume info and HALT\n";
print " --help print full help, with list --typ and --ini options\n";
return unless $ptyp;
print "\n";
print "currently supported disk types:\n";
print " type #cyl #trk #sec bps tot_sec blocks -bad\n";
foreach my $typ (sort keys %disktype) {
my $cyl = $disktype{$typ}{cyl};
my $hd = $disktype{$typ}{hd};
my $sec = $disktype{$typ}{sec};
my $bps = $disktype{$typ}{bps};
printf " %4s %4d %4d %4d %4d %7d %7d %3s\n",
$typ, $cyl, $hd, $sec, $bps,
($cyl*$hd*$sec), ($cyl*$hd*$sec*$bps)/1024,
($disktype{$typ}{bad} ? 'yes' : ' no');
}
print "\n";
print "currently supported initialization patterns:\n";
print " zero all zero (the default anyway if no -ini given)\n";
print " ones all ones\n";
print " dead alternating 0xdead 0xbeaf pattern\n";
print " test writes unique groups of 8 16bit words\n";
print "\n";
print "For further details consults the create_disk man page.\n";
return;
}

4
tools/bin/fx2load_wrapper
View File

@@ -1,5 +1,5 @@
#!/usr/bin/perl -w
# $Id: fx2load_wrapper 470 2013-01-05 17:28:46Z mueller $
# $Id: fx2load_wrapper 547 2013-12-29 13:10:07Z mueller $
#
# Copyright 2011-2013 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
#
@@ -203,7 +203,7 @@ sub run_command {
#-------------------------------------------------------------------------------
sub print_help {
print "usage: fx2load_wrapper [--board=b] [--file=f] <opts>\n";
print "usage: fx2load_wrapper [--board=b] [--file=f] [OPTIONS]\n";
print " --help this message\n";
print " --dry_run print command only\n";
print " --force reload even when proper firmware detected\n";

27
tools/bin/isemsg_filter
View File

@@ -1,7 +1,7 @@
#!/usr/bin/perl -w
# $Id: isemsg_filter 450 2012-01-05 23:21:41Z mueller $
# $Id: isemsg_filter 550 2014-02-03 08:16:57Z mueller $
#
# Copyright 2011-2012 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
# Copyright 2011-2014 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
#
# This program is free software; you may redistribute and/or modify it under
# the terms of the GNU General Public License as published by the Free
@@ -14,6 +14,7 @@
#
# Revision History:
# Date Rev Version Comment
# 2014-02-01 550 1.1.1 rename --pack to --pacc (accepted is meant here)
# 2012-01-04 450 1.1 preliminary check for par 'all constraints met'
# 2011-08-14 406 1.0 Initial version
#
@@ -26,7 +27,7 @@ use Getopt::Long;
my %opts = ();
GetOptions(\%opts, "help", "pack") || exit 1;
GetOptions(\%opts, "help", "pacc") || exit 1;
sub print_help;
sub read_mfs;
@@ -50,7 +51,7 @@ if (exists $opts{help}) {
}
if (!defined $type || !defined $mfsnam || !defined $lognam) {
print STDERR "%isemsg_filter-E: one of 'type mfs log' missing \n\n";
print STDERR "%isemsg_filter-E: one of 'type mfset log' missing \n\n";
print_help;
exit 1;
}
@@ -83,7 +84,7 @@ foreach (@mlist) {
}
if ($nackcnt) {
print "Non-acknowledged messages of type [$type] from $lognam:\n";
print "Unexpected messages of type [$type] from $lognam:\n";
foreach (@mlist) {
next if $_->[2];
print $_->[0] . "\n";
@@ -99,8 +100,8 @@ foreach (@flist) {
}
}
if ($ackcnt && exists $opts{pack}) {
print "Acknowledged messages of type [$type] from $lognam:\n";
if ($ackcnt && exists $opts{pacc}) {
print "Accepted messages of type [$type] from $lognam:\n";
foreach (@flist) {
next if $_->[1] == 0;
printf "%4d: %s\n", $_->[1], $_->[0];
@@ -109,7 +110,7 @@ if ($ackcnt && exists $opts{pack}) {
}
if ($misscnt) {
print "Missed acknowledged messages of type [$type] from $lognam:\n";
print "Missed messages of type [$type] from $lognam:\n";
foreach (@flist) {
next if $_->[1] != 0;
printf "%4d: %s\n", $_->[1], $_->[0];
@@ -202,11 +203,11 @@ sub read_log {
#-------------------------------------------------------------------------------
sub print_help {
print "usage: isemsg_filter [options] type mfs log\n";
print " type log file type: xst,tra,map,par,twr, or bgn\n";
print " mfs message filter setup file\n";
print " log log file\n";
print "usage: isemsg_filter [options] type mfset log\n";
print " type log file type: xst,tra,map,par,twr, or bgn\n";
print " mfset message filter set file\n";
print " log log file\n";
print " Options:\n";
print " --pack print summary of acknowledged messages\n";
print " --pacc print summary of accepted messages\n";
print " --help this message\n";
}

3
tools/bin/svn_set_ignore
View File

@@ -1,5 +1,5 @@
#!/usr/bin/perl -w
# $Id: svn_set_ignore 314 2010-07-09 17:38:41Z mueller $
# $Id: svn_set_ignore 547 2013-12-29 13:10:07Z mueller $
#
# Copyright 2007-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
#
@@ -13,6 +13,7 @@
# for complete details.
#
# Revision History:
# Date Rev Vers Comment
# 2010-04-26 284 1.0.1 add error check for GetOptions
# 2007-06-16 56 1.0 Initial version
#

3
tools/bin/telnet_starter
View File

@@ -1,5 +1,5 @@
#!/usr/bin/perl -w
# $Id: telnet_starter 314 2010-07-09 17:38:41Z mueller $
# $Id: telnet_starter 547 2013-12-29 13:10:07Z mueller $
#
# Copyright 2009-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
#
@@ -13,6 +13,7 @@
# for complete details.
#
# Revision History:
# Date Rev Vers Comment
# 2010-07-04 312 1.0.3 correct telnet_wrapper path
# 2010-04-26 284 1.0.2 add error check for GetOptions
# 2009-11-08 248 1.0.1 proper -h handling & text; add -t support;

3
tools/bin/telnet_wrapper
View File

@@ -1,5 +1,5 @@
#!/usr/bin/perl -w
# $Id: telnet_wrapper 516 2013-05-05 21:24:52Z mueller $
# $Id: telnet_wrapper 547 2013-12-29 13:10:07Z mueller $
#
# Copyright 2009-2013 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
#
@@ -13,6 +13,7 @@
# for complete details.
#
# Revision History:
# Date Rev Vers Comment
# 2009-11-07 246 1.0 Initial version
#

55
tools/bin/ti_rri
View File

@@ -1,6 +1,6 @@
#! /usr/bin/env tclsh
# -*- tcl -*-
# $Id: ti_rri 511 2013-04-27 13:51:46Z mueller $
# $Id: ti_rri 522 2013-05-24 17:50:29Z mueller $
#
# Copyright 2011-2013 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
#
@@ -15,6 +15,7 @@
#
# Revision History:
# Date Rev Version Comment
# 2013-05-19 521 1.1.6 setup proper interactive handling; add --run reap
# 2013-04-26 510 1.1.5 reorganize readline startup
# 2013-04-12 504 1.1.4 add --pack; trailing '-' argv implies --int
# 2013-02-05 482 1.1.3 stop server is rls found
@@ -90,8 +91,9 @@ proc tirri_exit {{doexit 1}} {
# FIXME_code: should sync here with -run process run-down
# but no wait available in tcl (grr...)
if { "$runpid" ne "" } {
if { "$runpid" ne "" } {
after 100; # currently just wait 100ms
rutil::waitpid $runpid
}
if { $doexit } {
puts {}; # \n to ensure shell prompt on new line
@@ -144,43 +146,14 @@ if { $opts(help) } {
puts { useful to start test benches, usually via 'tbw'}
puts { --fifo[=ARGS] open fifo type rlink port. Optional arguments are:}
puts { --fifo=[NAME[,OPTS]]}
puts { NAME fifo name prefix, default 'rlink_cext_fifo'}
puts { OPTS further options (comma separated list):}
puts { keep fifo is kept open on exit}
puts { --term[=ARGS] open term type rlink port. Optional arguments are:}
puts { --term=[NAME[,BAUD[,OPTS]]]}
puts { NAME tty device name, default 'USB0'}
puts { if not starting with '/' the name is}
puts { prefixed with '/dev/tty'}
puts { BAUD serial port baud rate, default '115k'}
puts { allowed baud rate settings are:}
puts { 2400, 4800, 9600, 19200, 19k, 38400, 38k}
puts { 57600, 57k, 115200, 115k, 230400, 230k}
puts { 460800, 460k, 500000, 500k, 921600, 921k}
puts { 1000000, 1000k, 1M, 1500000, 1500k}
puts { 2000000, 2000k, 2M, 2500000, 2500k}
puts { 3000000, 3000k, 3M, 4000000, 4000k, 4M}
puts { OPTS further options (comma separated list):}
puts { break send a break, do autobaud}
puts { cts hardware flow control (cts/rts)}
puts { xon software flow control (xon/xoff)}
puts { --cuff[=ARGS] open cuff type rlink port. Optional arguments are:}
puts { --cuff=[NAME[,OPTS]]}
puts { NAME USB path, default derived from environment}
puts { variables RETRO_FX2_VID and RETRO_FX2_PID}
puts { OPTS further options (comma separated list):}
puts { trace trace USB activities}
puts { --log=FILE set log file name. Default is to write to stdout.}
puts { --logl=LVL set log level, default is '2' allowed values:}
puts { 0 no logging}
puts { 1 log rlink commands with communication errors}
puts { 2 log rlink commands with failed checks}
puts { 3 log all rlink commands}
puts { --logl=LVL set log level, default is '2' allowed values 0-3.}
puts { --dmpl=LVL set dump level, default is '0', values like logl}
puts { --tiol=LVL set i/o trace level, default is '0', allowed values:}
puts { 0 no i/o trace}
puts { 1 trace buffer activities}
puts { 2 trace character activities}
puts { --tiol=LVL set i/o trace level, default is '0', allowed 0-2.}
puts { --int enter interactive mode even when commands given}
puts { --help display this help and exit}
puts { -- all following arguments are treated as tcl commands}
@@ -210,13 +183,19 @@ if { $nopen > 1 } {
return 1
}
# setup auto path
lappend auto_path [file join $env(RETROBASE) tools tcl]
lappend auto_path [file join $env(RETROBASE) tools lib]
package require rlink
# setup default packages
package require rutiltpp
package require rlinktpp
package require rlink
# setup signal handling
rutil::sigaction -init
# setup connect and server objects
rlinkconnect rlc
rlinkserver rls rlc
@@ -301,11 +280,10 @@ set rlink::sim_mode [rlink::isfifo]
# so we have to check whether stdin/stdout is a terminal and set
# tcl_interactive accordingly
# FIXME_code: fstat not available (grr...), currently just assume istty
set tcl_interactive 1
set tcl_interactive [rutil::isatty STDIN]
# determine whether interactive mode, if yes, initialize readline
if {$opts(int) || [llength $clist] == 0 } {
if {$tcl_interactive && ($opts(int) || [llength $clist] == 0) } {
set tirri_interactive 1
package require tclreadline
@@ -349,8 +327,7 @@ foreach cmd $clist {
}
}
if { $tirri_interactive } {
if { $tcl_interactive && $tirri_interactive } {
::tclreadline::Loop
} else {
tirri_exit 0

5
tools/bin/ticonv_pdpcp
View File

@@ -1,5 +1,5 @@
#!/usr/bin/perl -w
# $Id: ticonv_pdpcp 504 2013-04-13 15:37:24Z mueller $
# $Id: ticonv_pdpcp 521 2013-05-20 22:16:45Z mueller $
#
# Copyright 2013- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
#
@@ -14,6 +14,7 @@
#
# Revision History:
# Date Rev Version Comment
# 2013-05-19 521 1.0.3 use -be subopt of -wibrb
# 2013-04-12 504 1.0.2 renamed from pi2ti_pdpcp; fix [rm]wi handling
# use wtcpu command; use wibrbbe command;
# 2013-02-05 483 1.0.1 make cpucmd parametrizable
@@ -104,7 +105,7 @@ while (<IFILE>) {
if ($be == 0) {
print "$cpu cp -wibrb 0$2\n";
} else {
printf "$cpu cp -wibrbbe 0%6.6o %o\n", $base&0177700, $be;
printf "$cpu cp -wibrb 0%6.6o -be %o\n", $base&0177700, $be;
}
# (read) [d=data] type commands: rrx,rps,rm,rmi --------------------

17
tools/bin/vbomconv
View File

@@ -1,7 +1,7 @@
#!/usr/bin/perl -w
# $Id: vbomconv 518 2013-05-12 16:45:02Z mueller $
# $Id: vbomconv 543 2013-11-03 22:43:41Z mueller $
#
# Copyright 2007-2012 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
# Copyright 2007-2013 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
#
# This program is free software; you may redistribute and/or modify it under
# the terms of the GNU General Public License as published by the Free
@@ -14,6 +14,7 @@
#
# Revision History:
# Date Rev Version Comment
# 2013-10-20 543 1.10 add --viv_vhdl
# 2012-02-05 456 1.9.4 redo filename substitution (= and :); add --get_top
# 2012-01-02 448 1.9.3 use in ghdl_m -fexplicit also when simprim used
# 2011-11-27 433 1.9.2 use in ghdl_m -fexplicit when unisim used
@@ -57,6 +58,7 @@ my %opts = ();
GetOptions(\%opts, "help", "trace", "ise_path=s",
"dep_xst", "dep_ghdl", "dep_isim",
"xst_prj", "isim_prj",
"viv_vhdl",
"ghdl_a", "ghdl_a_cmd",
"ghdl_i", "ghdl_i_cmd",
"ghdl_m", "ghdl_m_cmd",
@@ -343,6 +345,16 @@ if (exists $opts{isim_prj}) {
}
}
# --viv_vhdl ---------------------------------------------------------
if (exists $opts{viv_vhdl}) {
print "read_vhdl {\n";
foreach (@file_list) {
print " $_\n";
}
print "}\n";
}
# --dep_xst ----------------------------------------------------------
if (exists $opts{dep_xst}) {
@@ -813,6 +825,7 @@ sub print_help {
print " --dep_isim generate isim dependencies for make (on stdout)\n";
print " --xst_prj generate xst project file (on stdout)\n";
print " --isim_prj generate isim project file (on stdout)\n";
print " --viv_vhdl generate vivado read_vhdl command (on stdout)\n";
print " --ghdl_a generate and execute ghdl -a (analyse)\n";
print " --ghdl_a_cmd like ghdl_a, but only print command, no exec\n";
print " --ghdl_i generate and execute ghdl -i (inspect)\n";

3
tools/bin/xilinx_ghdl_simprim
View File

@@ -1,7 +1,8 @@
#!/bin/sh
# $Id: xilinx_ghdl_simprim 248 2009-11-08 22:51:38Z mueller $
# $Id: xilinx_ghdl_simprim 547 2013-12-29 13:10:07Z mueller $
#
# Revision History:
# Date Rev Vers Comment
# 2009-11-08 248 1.1 adopt to ISE 11.1, use VITAL models from ./primitive
# 2007-10-26 92 1.0 Initial version
#

3
tools/bin/xilinx_ghdl_unisim
View File

@@ -1,7 +1,8 @@
#!/bin/sh
# $Id: xilinx_ghdl_unisim 248 2009-11-08 22:51:38Z mueller $
# $Id: xilinx_ghdl_unisim 547 2013-12-29 13:10:07Z mueller $
#
# Revision History:
# Date Rev Vers Comment
# 2009-11-08 248 1.1 adopt to ISE 11.1, use VITAL models from ./primitive
# 2007-10-26 92 1.0 Initial version
#

62
tools/bin/xtwi Executable file
View File

@@ -0,0 +1,62 @@
#!/bin/bash
# $Id: xtwi 544 2013-11-10 22:42:16Z mueller $
#
# Xilinx Tool Wrapper script for ISE:
# define XTWI_PATH
# usage xwti <ise command>
#
# Revision History:
# Date Rev Version Comment
# 2013-10-12 539 1.0 Initial version
#
# Note: For Xilinx ISE installations with an install path <ipath> holds
# <ipath>/ISE_DS dir with settings(32|64).sh
# <ipath>/ISE_DS/ISE XILINX env var will point here
#
# store arg list on vars (will be dropped later to source scripts)
arglist_val=$@
arglist_num=$#
#
# check whether ISE already setup ($XILINX defined)
if [ -z "$XILINX" ]
then
# check whether $XTWI_PATH defined
if [ -z "$XTWI_PATH" ]
then
echo "XTWI_PATH not defined"
exit 1
fi
# check whether 32 or 64 bit system (uname -m gives 'i686' or 'x86_64')
if [ `uname -m` = "x86_64" ]
then
settings_filename=$XTWI_PATH/ISE_DS/settings64.sh
else
settings_filename=$XTWI_PATH/ISE_DS/settings32.sh
fi
if [ ! -e "$settings_filename" ]
then
echo "can't locate init script '$settings_filename'"
exit 1
fi
# drop arg list, suppress output
set --
. $settings_filename > /dev/null
# check that XILINX defined
if [ -z "$XILINX" ]
then
echo "Failed to setup XILINX"
exit 1
fi
else
echo "XILINX already defined"
fi
if [ $arglist_num != 0 ]
then
exec $arglist_val
fi

8
tools/dox/make_doxy
View File

@@ -1,5 +1,5 @@
#!/bin/sh
# $Id: make_doxy 488 2013-02-16 18:49:47Z mueller $
# $Id: make_doxy 523 2013-05-26 21:54:55Z mueller $
#
# Revision History:
# Date Rev Version Comment
@@ -35,6 +35,6 @@ doxygen w11_vhd_all.Doxyfile 2>&1 | tee w11_vhd_all.dox_log
#
echo ""
echo "to view use"
echo " firefox $RETRODOXY/w11/cpp/html/index.html &"
echo " firefox $RETRODOXY/w11/tcl/html/index.html &"
echo " firefox $RETRODOXY/w11/vhd/html/index.html &"
echo " firefox $RETRODOXY/doxy/w11/cpp/html/index.html &"
echo " firefox $RETRODOXY/doxy/w11/tcl/html/index.html &"
echo " firefox $RETRODOXY/doxy/w11/vhd/html/index.html &"

8
tools/dox/w11_cpp.Doxyfile
View File

@@ -5,10 +5,10 @@
#---------------------------------------------------------------------------
DOXYFILE_ENCODING = UTF-8
PROJECT_NAME = w11 - cpp
PROJECT_NUMBER = 0.57
PROJECT_NUMBER = 0.60
PROJECT_BRIEF = "Backend server for Rlink and w11"
PROJECT_LOGO =
OUTPUT_DIRECTORY = $(RETRODOXY)/w11/cpp
OUTPUT_DIRECTORY = $(RETRODOXY)/doxy/w11/cpp
CREATE_SUBDIRS = NO
OUTPUT_LANGUAGE = English
BRIEF_MEMBER_DESC = YES
@@ -262,8 +262,8 @@ SKIP_FUNCTION_MACROS = YES
#---------------------------------------------------------------------------
# Configuration::additions related to external references
#---------------------------------------------------------------------------
TAGFILES =
GENERATE_TAGFILE =
TAGFILES =
GENERATE_TAGFILE = $(RETRODOXY)/w11/cpp/cpp.tag
ALLEXTERNALS = NO
EXTERNAL_GROUPS = YES
PERL_PATH = /usr/bin/perl

11
tools/dox/w11_tcl.Doxyfile
View File

@@ -5,10 +5,10 @@
#---------------------------------------------------------------------------
DOXYFILE_ENCODING = UTF-8
PROJECT_NAME = w11 - tcl
PROJECT_NUMBER = 0.57
PROJECT_NUMBER = 0.60
PROJECT_BRIEF = "Backend server for Rlink and w11"
PROJECT_LOGO =
OUTPUT_DIRECTORY = $(RETRODOXY)/w11/tcl
OUTPUT_DIRECTORY = $(RETRODOXY)/doxy/w11/tcl
CREATE_SUBDIRS = NO
OUTPUT_LANGUAGE = English
BRIEF_MEMBER_DESC = YES
@@ -102,10 +102,11 @@ INPUT_ENCODING = UTF-8
FILE_PATTERNS = *.tcl \
*.dox
RECURSIVE = YES
EXCLUDE =
EXCLUDE =
EXCLUDE_SYMLINKS = NO
EXCLUDE_PATTERNS = */.svn* \
*/tests/*
*/tests/* \
*/pkgIndex.tcl
EXCLUDE_SYMBOLS =
EXAMPLE_PATH =
EXAMPLE_PATTERNS =
@@ -259,7 +260,7 @@ SKIP_FUNCTION_MACROS = YES
# Configuration::additions related to external references
#---------------------------------------------------------------------------
TAGFILES =
GENERATE_TAGFILE =
GENERATE_TAGFILE = $(RETRODOXY)/w11/tcl/tcl.tag
ALLEXTERNALS = NO
EXTERNAL_GROUPS = YES
PERL_PATH = /usr/bin/perl

8
tools/dox/w11_vhd_all.Doxyfile
View File

@@ -5,10 +5,10 @@
#---------------------------------------------------------------------------
DOXYFILE_ENCODING = UTF-8
PROJECT_NAME = w11 - vhd
PROJECT_NUMBER = 0.57
PROJECT_BRIEF = "Backend server for Rlink and w11"
PROJECT_NUMBER = 0.60
PROJECT_BRIEF = "W11 CPU core and support modules"
PROJECT_LOGO =
OUTPUT_DIRECTORY = $(RETRODOXY)/w11/vhd
OUTPUT_DIRECTORY = $(RETRODOXY)/doxy/w11/vhd
CREATE_SUBDIRS = NO
OUTPUT_LANGUAGE = English
BRIEF_MEMBER_DESC = YES
@@ -262,7 +262,7 @@ SKIP_FUNCTION_MACROS = YES
# Configuration::additions related to external references
#---------------------------------------------------------------------------
TAGFILES =
GENERATE_TAGFILE =
GENERATE_TAGFILE = $(RETRODOXY)/w11/vhd/vhd.tag
ALLEXTERNALS = NO
EXTERNAL_GROUPS = YES
PERL_PATH = /usr/bin/perl

2
tools/fx2/src/README_iso_jtag.txt
View File

@@ -1,4 +1,4 @@
$ Id: $
$Id: README_iso_jtag.txt 525 2013-07-06 12:19:39Z mueller $
usb_jtag using Cypress FX2 chip
===============================

2
tools/oskit/211bsd_rk/211bsd_rk_boot.scmd
View File

@@ -1,4 +1,4 @@
; $Id: 211bsd_rk_boot.scmd 517 2013-05-09 21:34:45Z mueller $
; $Id: 211bsd_rk_boot.scmd 519 2013-05-12 20:44:16Z mueller $
;
; Setup file for 211bsd RK based system
;

2
tools/oskit/rsx11m-40_rk/rsx11m-40_rk_boot.scmd
View File

@@ -1,4 +1,4 @@
; $Id: $
; $Id: rsx11m-40_rk_boot.scmd 525 2013-07-06 12:19:39Z mueller $
;
; Setup file for RSX11-M V4.0 RK05 based system
;

2
tools/oskit/rsx11m-40_rk/rsx11m-40_rk_boot.tcl
View File

@@ -1,4 +1,4 @@
# $Id: $
# $Id: rsx11m-40_rk_boot.tcl 525 2013-07-06 12:19:39Z mueller $
#
# Setup file for RSX11-M V4.0 RK05 based system
#

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