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Code Issues Releases Wiki Activity

- interim release w11a_V0.581 (untagged)

Browse Source 
- new reference system
  - switched from ISE 13.3 to 14.7.
  - map/par behaviour changed, unfortunately unfavorably for w11a. 
    On Nexys3 no timing closure anymore for 80 MHz, only 72 MHz can 
    be achieved now.
- new man pages (in doc/man/man1/)
- support for Spartan-6 CMTs in PLL and DCM mode
This commit is contained in:
Walter F.J. Mueller
2014-05-29 21:30:01 +00:00
parent 200ba69364
commit 4732555297
152 changed files with 4141 additions and 592 deletions
Download Patch File Download Diff File Expand all files Collapse all files

5
tools/tbench/test_cp_cpubasics.tcl
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@@ -1,4 +1,4 @@
# $Id: test_cp_cpubasics.tcl 504 2013-04-13 15:37:24Z mueller $
# $Id: test_cp_cpubasics.tcl 552 2014-03-02 23:02:00Z mueller $
#
# Copyright 2013- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
# License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory
@@ -13,8 +13,11 @@
# 3. single step code via -step
#
# ----------------------------------------------------------------------------
rlc log "test_cp_cpubasics: Test very basic cpu interface gymnastics"
rlc log " load code via lsasm"
#
$cpu ldasm -lst lst -sym sym {
. = 1000
start: inc r2

3
tools/tbench/test_cp_gpr.tcl
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@@ -1,4 +1,4 @@
# $Id: test_cp_gpr.tcl 502 2013-04-02 19:29:30Z mueller $
# $Id: test_cp_gpr.tcl 552 2014-03-02 23:02:00Z mueller $
#
# Copyright 2013- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
# License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory
@@ -13,6 +13,7 @@
# k,s,u mode sp are distinct
#
# ----------------------------------------------------------------------------
rlc log "test_cp_gpr: test cp access to general purpose registers"
rlc log " write set 0"
$cpu cp -wps 0000000

24
tools/tbench/test_cp_ibrbasics.tcl Normal file
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@@ -0,0 +1,24 @@
# $Id: test_cp_ibrbasics.tcl 552 2014-03-02 23:02:00Z mueller $
#
# Copyright 2014- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
# License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory
#
# Revision History:
# Date Rev Version Comment
# 2014-03-02 552 1.0 Initial version
#
# Test very basic memory interface gymnastics
# 2. write/read IB space via bwm/brm (use MMU SAR SM I regs)
#
# ----------------------------------------------------------------------------
rlc log "test_cp_membasics: Test very basic ibus interface gymnastics"
rlc log " write/read ibus space (MMU SAR SM I regs) via bwm/brm"
$cpu cp -wal 0172240 \
-bwm {012340 012342 012344}
$cpu cp -wal 0172240 \
-brm 3 -edata {012340 012342 012344}
# --------------------------------------------------------------------

74
tools/tbench/test_cp_membasics.tcl Normal file
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@@ -0,0 +1,74 @@
# $Id: test_cp_membasics.tcl 552 2014-03-02 23:02:00Z mueller $
#
# Copyright 2014- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
# License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory
#
# Revision History:
# Date Rev Version Comment
# 2014-03-02 552 1.0 Initial version
#
# Test very basic memory interface gymnastics
# 1. write/read address register
# 2. write/read memory via wm/wmi/rm/rmi (16 bit mode)
# 3. write/read memory via bwm/brm (16 bit mode)
#
# ----------------------------------------------------------------------------
rlc log "test_cp_membasics: Test very basic memory interface gymnastics"
# --------------------------------------------------------------------
rlc log " write/read address register"
# test wal
$cpu cp -wal 002000 \
-ral -edata 002000 \
-rah -edata 000000
# test wah+wal
$cpu cp -wal 003000 \
-wah 000001 \
-ral -edata 003000 \
-rah -edata 000001
# --------------------------------------------------------------------
rlc log " write/read memory via wm/wmi/rm/rmi (16 bit mode)"
# simple write/read without increment
$cpu cp -wal 002000 \
-wm 001100 \
-ral -edata 002000 \
-rah -edata 000000 \
-rm -edata 001100
# double write + single read, check overwrite
$cpu cp -wal 002000 \
-wm 002200 \
-wm 002210 \
-ral -edata 002000 \
-rah -edata 000000 \
-rm -edata 002210
# double write/read with increment
$cpu cp -wal 002100 \
-wmi 003300 \
-wmi 003310 \
-wmi 003320 \
-ral -edata 002106 \
-rah -edata 000000
$cpu cp -wal 002100 \
-rmi -edata 003300 \
-rmi -edata 003310 \
-rmi -edata 003320 \
-ral -edata 002106 \
-rah -edata 000000
# --------------------------------------------------------------------
rlc log " write/read memory via bwm/brm (16 bit mode)"
$cpu cp -wal 02200 \
-bwm {007700 007710 007720 007730}
$cpu cp -wal 02200 \
-brm 4 -edata {007700 007710 007720 007730}

3
tools/tbench/test_cp_psw.tcl
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@@ -1,4 +1,4 @@
# $Id: test_cp_psw.tcl 502 2013-04-02 19:29:30Z mueller $
# $Id: test_cp_psw.tcl 552 2014-03-02 23:02:00Z mueller $
#
# Copyright 2013- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
# License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory
@@ -16,6 +16,7 @@
# This test not only verifies psw, but also all basic access methods
#
# ----------------------------------------------------------------------------
rlc log "test_cp_psw: test psw access via all methods"
rlc log " write/read via cp"
foreach w { 000000 000017 } {

42
tools/tbench/test_w11a_dsta_flow.tcl
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@@ -1,19 +1,30 @@
# $Id: test_w11a_dsta_flow.tcl 510 2013-04-26 16:14:57Z mueller $
# $Id: test_w11a_dsta_flow.tcl 552 2014-03-02 23:02:00Z mueller $
#
# Copyright 2013- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
# Copyright 2013-2014 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
# License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory
#
# Revision History:
# Date Rev Version Comment
# 2014-03-01 552 1.0.1 use stack:; check sp;
# 2013-03-31 502 1.0 Initial version
#
# Test dsta flow with jsr pc,... instructions
#
# ----------------------------------------------------------------------------
rlc log "test_w11a_dsta_flow: test dsta flow with jsr pc,..."
rlc log " (r0),(r0)+,@(r0)+,-(r0),@-(r0) (mode=1,2,3,4,5)"
# code register pre/post conditions beyond defaults
# r0 #sub00 -> ..same
# r1 #sub10 -> #sub10+2
# r2 #psub2 -> #psub2+4
# r3 #sub30+2 -> #sub30
# r4 #psub4e -> #psub4
# r5 #data -> #data+7*2*2
$cpu ldasm -lst lst -sym sym {
. = 1000
stack:
start: jsr pc,(r0)
100$: jsr pc,(r1)+
110$: jsr pc,@(r2)+
@@ -23,6 +34,7 @@ start: jsr pc,(r0)
140$: jsr pc,@-(r4)
141$: halt
stop:
;
psub2: .word sub20, sub21
psub4: .word sub41, sub40
psub4e:
@@ -59,11 +71,12 @@ rw11::asmrun $cpu sym [list r0 $sym(sub00) \
r5 $sym(data) ]
rw11::asmwait $cpu sym 1.0
rw11::asmtreg $cpu [list r0 $sym(sub00) \
r1 [expr {$sym(sub10)+2}] \
r2 [expr {$sym(psub2)+4}] \
r3 $sym(sub30) \
r4 $sym(psub4) \
r5 [expr {$sym(data) + 7*2*2}] ]
r1 [expr {$sym(sub10)+2}] \
r2 [expr {$sym(psub2)+4}] \
r3 $sym(sub30) \
r4 $sym(psub4) \
r5 [expr {$sym(data) + 7*2*2}] \
sp $sym(stack) ]
rw11::asmtmem $cpu $sym(data) [list \
0100 $sym(start:100$) \
0110 $sym(start:110$) \
@@ -74,9 +87,16 @@ rw11::asmtmem $cpu $sym(data) [list \
0141 $sym(start:141$) \
0177777 ]
# ----------------------------------------------------------------------------
rlc log " nn(r0),@nn(r0),var,@var,@#var (mode=6,7,67,77,37)"
# code register pre/post conditions beyond defaults
# r0 #sub00-020 -> ..same
# r1 #psub10-040 -> ..same
# r5 #data -> #data+5*2*2
$cpu ldasm -lst lst -sym sym {
. = 1000
stack:
start: jsr pc,20(r0)
1100$: jsr pc,@40(r1)
1110$: jsr pc,sub20
@@ -84,6 +104,7 @@ start: jsr pc,20(r0)
1130$: jsr pc,@#sub40
1140$: halt
stop:
;
psub10: .word sub10
psub30: .word sub30
sub00: mov #1100,(r5)+
@@ -106,15 +127,16 @@ data: .blkw 2*5.
}
rw11::asmrun $cpu sym [list r0 [expr {$sym(sub00)-020}] \
r1 [expr {$sym(psub10)-040}] \
r5 $sym(data) ]
r1 [expr {$sym(psub10)-040}] \
r5 $sym(data) ]
rw11::asmwait $cpu sym 1.0
rw11::asmtreg $cpu [list r0 [expr {$sym(sub00)-020}] \
r1 [expr {$sym(psub10)-040}] \
r2 0 \
r3 0 \
r4 0 \
r5 [expr {$sym(data) + 5*2*2}] ]
r5 [expr {$sym(data) + 5*2*2}] \
sp $sym(stack) ]
rw11::asmtmem $cpu $sym(data) [list \
01100 $sym(start:1100$) \
01110 $sym(start:1110$) \

28
tools/tbench/test_w11a_dstm_word_flow.tcl
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@@ -1,17 +1,27 @@
# $Id: test_w11a_dstm_word_flow.tcl 510 2013-04-26 16:14:57Z mueller $
# $Id: test_w11a_dstm_word_flow.tcl 552 2014-03-02 23:02:00Z mueller $
#
# Copyright 2013- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
# Copyright 2013-2014 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
# License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory
#
# Revision History:
# Date Rev Version Comment
# 2014-03-01 552 1.0.1 check that unused regs stay 0
# 2013-03-31 502 1.0 Initial version
#
# Test dstm flow with inc ... instructions for word access
#
# ----------------------------------------------------------------------------
rlc log "test_w11a_dstm_word_flow: test dstm flow for word with inc ..."
rlc log " r0,(r0),(r0)+,@(r0)+,-(r0),@-(r0) (mode=0,1,2,3,4,5)"
# code register pre/post conditions beyond defaults
# r0 #010 -> #011
# r1 #data1 -> #data1
# r2 #data2 -> #data2+4
# r3 #pdata3 -> #pdata3+4
# r4 #data4e -> #data4e-4
# r5 #pdat5e -> #pdat5e-4
$cpu ldasm -lst lst -sym sym {
. = 1000
start: inc r0
@@ -26,6 +36,7 @@ start: inc r0
inc @-(r5)
halt
stop:
;
data1: .word 20
data2: .word 30,31
data3: .word 40,41
@@ -53,8 +64,12 @@ rw11::asmtreg $cpu [list r0 011 \
r5 [expr {$sym(pdat5e) - 4}] ]
rw11::asmtmem $cpu $sym(data1) {021 031 032 041 042 051 052 061 062}
# ----------------------------------------------------------------------------
rlc log " nn(r0),@nn(r0),var,@var,@#var (mode=6,7,67,77,37)"
# code register pre/post conditions beyond defaults
# r0 #data0-020 -> ..same
# r1 #pdata1-040 -> ..same
$cpu ldasm -lst lst -sym sym {
. = 1000
start: inc 20(r0)
@@ -64,6 +79,7 @@ start: inc 20(r0)
inc @#data4
halt
stop:
;
data0: .word 200
data1: .word 210
data2: .word 220
@@ -77,4 +93,10 @@ pdata3: .word data3
rw11::asmrun $cpu sym [list r0 [expr {$sym(data0)-020}] \
r1 [expr {$sym(pdata1)-040}] ]
rw11::asmwait $cpu sym 1.0
rw11::asmtreg $cpu [list r0 [expr {$sym(data0)-020}] \
r1 [expr {$sym(pdata1)-040}] \
r2 0 \
r3 0 \
r4 0 \
r5 0 ]
rw11::asmtmem $cpu $sym(data0) {0201 0211 0221 0231 0241}

37
tools/tbench/test_w11a_dstw_word_flow.tcl
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@@ -1,17 +1,27 @@
# $Id: test_w11a_dstw_word_flow.tcl 510 2013-04-26 16:14:57Z mueller $
# $Id: test_w11a_dstw_word_flow.tcl 552 2014-03-02 23:02:00Z mueller $
#
# Copyright 2013- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
# Copyright 2013-2014 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
# License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory
#
# Revision History:
# Date Rev Version Comment
# 2014-03-01 552 1.0.1 check that unused regs stay 0
# 2013-03-31 502 1.0 Initial version
#
# Test dstw flow with mov #nnn,... instructions for word access
#
# ----------------------------------------------------------------------------
rlc log "test_w11a_dstw_word_flow: test dstw flow for word with mov #nnn,..."
rlc log " r0,(r0),(r0)+,@(r0)+,-(r0),@-(r0) (mode=0,1,2,3,4,5)"
# code register pre/post conditions beyond defaults
# r0 -> 0100
# r1 #data1 -> ..same
# r2 #data2 -> #data2+4
# r3 #pdata3 -> #pdata3+4
# r4 #data4e -> #data4e-4
# r5 #pdat5e -> #pdat5e-4
$cpu ldasm -lst lst -sym sym {
. = 1000
start: mov #100,r0
@@ -26,6 +36,7 @@ start: mov #100,r0
mov #150,@-(r5)
halt
stop:
;
data1: .word 0
data2: .word 0,0
data3: .word 0,0
@@ -39,10 +50,10 @@ pdat5e:
}
rw11::asmrun $cpu sym [list r1 $sym(data1) \
r2 $sym(data2) \
r3 $sym(pdata3) \
r4 $sym(data4e) \
r5 $sym(pdat5e) ]
r2 $sym(data2) \
r3 $sym(pdata3) \
r4 $sym(data4e) \
r5 $sym(pdat5e) ]
rw11::asmwait $cpu sym 1.0
rw11::asmtreg $cpu [list r0 0100 \
r1 $sym(data1) \
@@ -52,9 +63,12 @@ rw11::asmtreg $cpu [list r0 0100 \
r5 [expr {$sym(pdat5e) - 4}] ]
rw11::asmtmem $cpu $sym(data1) {0110 0120 0121 0130 0131 0140 0141 0150 0151}
# ----------------------------------------------------------------------------
rlc log " nn(r0),@nn(r0),var,@var,@#var (mode=6,7,67,77,37)"
# code register pre/post conditions beyond defaults
# r0 #data0-020 -> ..same
# r1 #pdata0-040 -> ..same
$cpu ldasm -lst lst -sym sym {
. = 1000
start: mov #200,20(r0)
@@ -64,6 +78,7 @@ start: mov #200,20(r0)
mov #240,@#data4
halt
stop:
;
data0: .word 0
data1: .word 0
data2: .word 0
@@ -77,4 +92,10 @@ pdata3: .word data3
rw11::asmrun $cpu sym [list r0 [expr {$sym(data0)-020}] \
r1 [expr {$sym(pdata1)-040}] ]
rw11::asmwait $cpu sym 1.0
rw11::asmtreg $cpu [list r0 [expr {$sym(data0)-020}] \
r1 [expr {$sym(pdata1)-040}] \
r2 0 \
r3 0 \
r4 0 \
r5 0 ]
rw11::asmtmem $cpu $sym(data0) {0200 0210 0220 0230 0240}

33
tools/tbench/test_w11a_inst_traps.tcl
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@@ -1,16 +1,21 @@
# $Id: test_w11a_inst_traps.tcl 510 2013-04-26 16:14:57Z mueller $
# $Id: test_w11a_inst_traps.tcl 552 2014-03-02 23:02:00Z mueller $
#
# Copyright 2013- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
# Copyright 2013-2014 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
# License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory
#
# Revision History:
# Date Rev Version Comment
# 2014-03-01 552 1.0.1 check that unused regs stay 0; use stack:; check sp;
# 2013-04-01 502 1.0 Initial version
#
# Test trap type instructions: bpt,iot, emt nn, trap nn
#
# ----------------------------------------------------------------------------
rlc log "test_w11a_inst_traps: test trap type instructions"
# code register pre/post conditions beyond defaults
# r5 #data -> #data+6*5*2
$cpu ldasm -lst lst -sym sym {
. = 14
.word h.bpt ; vec 14: bpt
@@ -26,6 +31,7 @@ $cpu ldasm -lst lst -sym sym {
psw = 177776
;
. = 1000
stack:
start: mov #350,@#psw
bpt
350$: mov #351,@#psw
@@ -41,8 +47,8 @@ start: mov #350,@#psw
355$: halt
stop:
;
h.bpt: mov @#psw,(r5)+
mov #1014,(r5)+
h.bpt: mov @#psw,(r5)+ ; record psw
mov #1014,(r5)+ ; record trap id
br iexit
h.iot: mov @#psw,(r5)+
mov #1020,(r5)+
@@ -53,20 +59,25 @@ h.emt: mov @#psw,(r5)+
h.trp: mov @#psw,(r5)+
mov #1034,(r5)+
;
iexit: mov (sp),r4
mov r4,(r5)+
mov 2(sp),(r5)+
mov -2(r4),(r5)+
iexit: mov (sp),r4 ; get stack PC
mov r4,(r5)+ ; record PC
mov 2(sp),(r5)+ ; record stack PS
mov -2(r4),(r5)+ ; record opcode of trap
rti
;
data: .blkw 6.*5.
.word 177777
}
rw11::asmrun $cpu sym [list r5 $sym(data) ]
rw11::asmwait $cpu sym 1.0
rw11::asmtreg $cpu [list r0 0 r1 0 r2 0 r3 0 \
r5 [expr {$sym(data) + 6*5*2}] \
sp $sym(start) ]
rw11::asmtreg $cpu [list r0 0 \
r1 0 \
r2 0 \
r3 0 \
r5 [expr {$sym(data) + 6*5*2}] \
sp $sym(stack) ]
# data: trap ps; trap id; stack-pc; stack-ps opcode
rw11::asmtmem $cpu $sym(data) \
[list 000340 001014 $sym(start:350$) 000350 0000003 \

58
tools/tbench/test_w11a_srcr_word_flow.tcl
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@@ -1,17 +1,25 @@
# $Id: test_w11a_srcr_word_flow.tcl 510 2013-04-26 16:14:57Z mueller $
# $Id: test_w11a_srcr_word_flow.tcl 552 2014-03-02 23:02:00Z mueller $
#
# Copyright 2013- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
# License disclaimer see LICENSE_gpl_v2.txt in $RETROBASE directory
#
# Revision History:
# Date Rev Version Comment
# 2014-03-01 552 1.0.1 check sp
# 2013-03-31 502 1.0 Initial version
#
# Test srcr flow with mov ...,rx instructions for word access
#
# ----------------------------------------------------------------------------
rlc log "test_w11a_srcr_word_flow: test srcr flow for word with mov ...,rx"
rlc log " r0 (mode=0)"
# code register pre/post conditions beyond defaults
# r0 01234 -> ..same
# r1 -> 01234
# r2 -> #stack
# r3 -> #start
$cpu ldasm -lst lst -sym sym {
. = 1000
stack:
@@ -29,9 +37,19 @@ rw11::asmtreg $cpu [list r0 01234 \
r2 $sym(stack) \
r3 $sym(lpc) \
r4 0 \
r5 0]
r5 0 \
sp $sym(stack) ]
# ----------------------------------------------------------------------------
rlc log " (r0),(r0)+,-(r0) (mode=1,2,4)"
# code register pre/post conditions beyond defaults
# r0 #data -> ..same
# r1 -> 01001
# r2 -> 01001
# r3 -> 01002
# r4 -> 01002
# r5 -> 01001
$cpu ldasm -lst lst -sym sym {
. = 1000
start: mov (r0),r1
@@ -41,6 +59,7 @@ start: mov (r0),r1
mov -(r0),r5
halt
stop:
;
data: .word 1001
.word 1002
}
@@ -52,9 +71,18 @@ rw11::asmtreg $cpu [list r0 $sym(data) \
r2 001001 \
r3 001002 \
r4 001002 \
r5 001001]
r5 001001 ]
# ----------------------------------------------------------------------------
rlc log " @(r0)+,@-(r0) (mode=3,5)"
# code register pre/post conditions beyond defaults
# r0 #pdata -> ..same
# r1 -> 02001
# r2 -> 02002
# r3 -> #pdata+4
# r4 -> 02002
# r5 -> 02001
$cpu ldasm -lst lst -sym sym {
. = 1000
start: mov @(r0)+,r1
@@ -64,6 +92,7 @@ start: mov @(r0)+,r1
mov @-(r0),r5
halt
stop:
;
pdata: .word data0
.word data1
data0: .word 2001
@@ -78,9 +107,17 @@ rw11::asmtreg $cpu [list r0 $sym(pdata) \
r2 002002 \
r3 [expr {$sym(pdata)+4}] \
r4 002002 \
r5 002001]
r5 002001 ]
# ----------------------------------------------------------------------------
rlc log " nn(r0),@nn(r0) (mode=6,7)"
# code register pre/post conditions beyond defaults
# r0 #data -> ..same
# r1 -> 03001
# r2 -> 03002
# r3 -> 03003
# r4 -> 03004
$cpu ldasm -lst lst -sym sym {
. = 1000
start: mov 2(r0),r1
@@ -89,6 +126,7 @@ start: mov 2(r0),r1
mov @10(r0),r4
halt
stop:
;
data: .word 177777
.word 003001
.word data0
@@ -106,9 +144,16 @@ rw11::asmtreg $cpu [list r0 $sym(data) \
r2 003002 \
r3 003003 \
r4 003004 \
r5 0]
r5 0 ]
# ----------------------------------------------------------------------------
rlc log " #nn,@#nn,var,@var (mode=27,37,67,77)"
# code register pre/post conditions beyond defaults
# r1 -> 04001
# r2 -> 04002
# r3 -> 04003
# r4 -> 04004
$cpu ldasm -lst lst -sym sym {
. = 1000
start: mov #004001,r1
@@ -117,6 +162,7 @@ start: mov #004001,r1
mov @pdata4,r4
halt
stop:
;
pdata4: .word data4
data2: .word 004002
@@ -131,4 +177,4 @@ rw11::asmtreg $cpu [list r0 0 \
r2 004002 \
r3 004003 \
r4 004004 \
r5 0]
r5 0 ]

4
tools/tbench/w11a_all.dat
View File

@@ -1,9 +1,11 @@
# $Id: w11a_all.dat 504 2013-04-13 15:37:24Z mueller $
# $Id: w11a_all.dat 552 2014-03-02 23:02:00Z mueller $
#
## steering file for all w11a tests
#
test_cp_gpr.tcl
test_cp_psw.tcl
test_cp_membasics.tcl
test_cp_ibrbasics.tcl
test_cp_cpubasics.tcl
test_w11a_srcr_word_flow.tcl
test_w11a_dstw_word_flow.tcl