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Cleanups; 17bit support for tst_sram

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- s3_sram_memctl: drop superfluous idata_cei=1 in s_write2
- arty_bram/tb/tbrun.yml: retire mem70 - now in tbcpu
- tst_sram.vhd: allow AWIDTH=17; sstat_rbf_awidth instead of _wide
- tcl/tst_sram/*.tcl: 17bit support; use sstat(awidth); add isnarrow
- rtl/vlib/rutil.vhd: added package, with imin helper function
This commit is contained in:
wfjm
2017-06-25 20:20:48 +02:00
parent 691b95c786
commit 4aa1db49c7
10 changed files with 217 additions and 91 deletions
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8
doc/CHANGELOG.md
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@@ -18,6 +18,14 @@ The full set of tests is only run for tagged releases.
### Summary
- new modules/packages
- rtl/vlib/rutil.vhd: added package, with imin helper function
- cleanups
- s3_sram_memctl: drop superfluous idata_cei=1 in s_write2
- 17bit support for tst_sram
- tst_sram.vhd: allow AWIDTH=17; sstat_rbf_awidth instead of _wide
- tcl/tst_sram/*.tcl: 17bit support; use sstat(awidth); add isnarrow
- add test_w11a_mem70.tcl; retire old tests tb_w11a_mem70*.dat
- shell_egd.tcl: BUGFIX: shell_pspec_map: fix mapping for addr>20000
- get vivado 2017.1 ready
- xviv_msg_filter: add version-range tag support

10
rtl/bplib/s3board/s3_sram_memctl.vhd
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@@ -1,6 +1,6 @@
-- $Id: s3_sram_memctl.vhd 793 2016-07-23 19:38:55Z mueller $
-- $Id: s3_sram_memctl.vhd 912 2017-06-11 18:30:03Z mueller $
--
-- Copyright 2007-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2007-2017 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
@@ -13,7 +13,7 @@
--
------------------------------------------------------------------------------
-- Module Name: s3_sram_memctl - syn
-- Description: s3board: SRAM driver
-- Description: s3board: SRAM controller
--
-- Dependencies: vlib/xlib/iob_reg_o
-- vlib/xlib/iob_reg_o_gen
@@ -30,6 +30,7 @@
--
-- Revision History:
-- Date Rev Version Comment
-- 2017-06-11 912 1.0.8 drop superfluous idata_cei=1 in s_write2
-- 2016-07-23 793 1.0.7 drop "KEEP" for data (better for dbg)
-- 2011-11-19 427 1.0.6 now numeric_std clean
-- 2010-06-03 299 1.0.5 add "KEEP" for data iob;
@@ -83,7 +84,7 @@ use ieee.numeric_std.all;
use work.slvtypes.all;
use work.xlib.all;
entity s3_sram_memctl is -- SRAM driver for S3BOARD
entity s3_sram_memctl is -- SRAM controller for S3BOARD
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
@@ -311,7 +312,6 @@ begin
when s_write2 => -- s_write2: write cycle, 2nd half
iactw := '1'; -- signal mem write
iackw := '1'; -- signal write acknowledge
idata_cei := '1'; -- latch input data (from SRAM)
if REQ = '1' then -- if IO requested
if WE = '1' then -- if WRITE requested
iaddr_ce := '1'; -- latch address and be's

1
rtl/sys_gen/tst_sram/tst_sram.vbom
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@@ -1,5 +1,6 @@
# libs
../../vlib/slvtypes.vhd
../../vlib/rutil.vhd
../../vlib/memlib/memlib.vhd
../../vlib/rbus/rblib.vhd
${sys_conf}

31
rtl/sys_gen/tst_sram/tst_sram.vhd
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@@ -1,6 +1,6 @@
-- $Id: tst_sram.vhd 889 2017-04-30 13:31:27Z mueller $
-- $Id: tst_sram.vhd 917 2017-06-25 18:05:28Z mueller $
--
-- Copyright 2007-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2007-2017 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
@@ -13,22 +13,24 @@
--
------------------------------------------------------------------------------
-- Module Name: tst_sram - syn
-- Description: test of s3board sram and its controller
-- Description: test of sram (s3,c7) and cram (n2,n3,n4) and its controller
--
-- Dependencies: vlib/memlib/ram_1swsr_wfirst_gen
-- vlib/memlib/ram_2swsr_wfirst_gen
-- vlib/rlink/rlink_base_serport
--
-- Test bench: nexys4/tb/tb_tst_sram_n4 (with cram)
-- Test bench: cmoda7/tb/tb_tst_sram_c7 (with sram)
-- nexys4/tb/tb_tst_sram_n4 (with cram)
-- nexys3/tb/tb_tst_sram_n3 (with cram)
-- nexys2/tb/tb_tst_sram_n2 (with cram)
-- s3board/tb/tb_tst_sram_s3 (with sram)
--
-- Target Devices: generic
-- Tool versions: xst 8.2-14.7; viv 2014.4-2016.2; ghdl 0.18-0.33
-- Tool versions: xst 8.2-14.7; viv 2014.4-2017.1; ghdl 0.18-0.34
--
-- Revision History:
-- Date Rev Version Comment
-- 2017-06-25 917 1.6 allow AWIDTH=17; sstat_rbf_awidth instead of _wide
-- 2016-07-10 785 1.5.1 std SWI layout: now (7:4) disp select, SWI(1)->XON
-- 2016-07-09 784 1.5 AWIDTH generic, add 22bit support for cram
-- 2016-05-22 767 1.4.1 don't init N_REGS (vivado fix for fsm inference)
@@ -153,11 +155,14 @@
-- DP(0): SER_MONI.rxact (shows rx activity)
--
-- ----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.rutil.all;
use work.memlib.all;
use work.rblib.all;
@@ -194,6 +199,8 @@ entity tst_sram is -- tester for sram memctl
end tst_sram;
architecture syn of tst_sram is
constant IWIDTH : natural := imin(18, AWIDTH);
signal SEQ_RESET : slbit := '0';
@@ -284,7 +291,7 @@ architecture syn of tst_sram is
subtype maddr_f_wh is integer range AWIDTH-1 downto 16;
subtype maddr_f_wl is integer range 15 downto 0;
subtype maddr_f_scmd is integer range 17 downto 0;
subtype maddr_f_scmd is integer range IWIDTH-1 downto 0;
subtype maddr_f_top4 is integer range AWIDTH-1 downto AWIDTH-1-3;
subtype maddr_f_mid4 is integer range AWIDTH-1-4 downto AWIDTH-1-7;
subtype maddr_f_bot is integer range AWIDTH-1-8 downto 0;
@@ -300,7 +307,7 @@ architecture syn of tst_sram is
subtype mcmd_rbf_be is integer range 11 downto 8;
subtype mcmd_rbf_addrh is integer range AWIDTH-1-16 downto 0;
constant sstat_rbf_wide: integer := 15;
subtype sstat_rbf_awidth is integer range 15 downto 13;
constant sstat_rbf_wswap: integer := 9;
constant sstat_rbf_wloop: integer := 8;
constant sstat_rbf_loop: integer := 7;
@@ -313,7 +320,7 @@ architecture syn of tst_sram is
subtype scmd_rbf_wait is integer range 31 downto 28;
constant scmd_rbf_we: integer := 24;
subtype scmd_rbf_be is integer range 23 downto 20;
subtype scmd_rbf_addr is integer range 17 downto 0;
subtype scmd_rbf_addr is integer range IWIDTH-1 downto 0;
constant rbaddr_mdih: slv5 := "00000"; -- 0 -/r/w
constant rbaddr_mdil: slv5 := "00001"; -- 1 -/r/w
@@ -354,8 +361,8 @@ architecture syn of tst_sram is
begin
assert AWIDTH=18 or AWIDTH=22
report "assert(AWIDTH=18 or AWIDTH=22): unsupported AWIDTH"
assert AWIDTH=17 or AWIDTH=18 or AWIDTH=22
report "assert(AWIDTH=17 or AWIDTH=18 or AWIDTH=22): unsupported AWIDTH"
severity failure;
SMEM_B3 : ram_1swsr_wfirst_gen
@@ -1023,9 +1030,7 @@ begin
omux_dat(r.saddr'range) := r.saddr;
when omux_sstat =>
omux_dat := (others=>'0');
if AWIDTH = 22 then
omux_dat(sstat_rbf_wide) := '1';
end if;
omux_dat(sstat_rbf_awidth):= slv(to_unsigned(AWIDTH-16,3));
omux_dat(sstat_rbf_wswap) := r.swswap;
omux_dat(sstat_rbf_wloop) := r.swloop;
omux_dat(sstat_rbf_loop) := r.sloop;

8
rtl/sys_gen/w11a/arty_bram/tb/tbrun.yml
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@@ -1,7 +1,8 @@
# $Id: tbrun.yml 809 2016-09-18 19:49:14Z mueller $
# $Id: tbrun.yml 916 2017-06-25 13:30:07Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2017-06-25 916 1.1 retire mem70 - now in tbcpu
# 2016-09-18 809 1.0.1 use 60 sec tout for run_pdpcp tb_pdp11core_stim
# 2016-08-21 799 1.0 Initial version
#
@@ -13,11 +14,6 @@
tbrun_tbwrri --hxon --lsuf stim1 tb_w11a_br_arty${ms} \
"rlink::run_rri ../../../../w11a/tb/tb_rlink_tba_pdp11core_stim.dat"
- tag: [default, viv, sys_w11a, br_arty, mem70]
test: |
tbrun_tbwrri --hxon --lsuf mem70 --pack rw11 tb_w11a_br_arty${ms} \
"rw11::setup_cpu" "rw11::run_pdpcp ../../tb/tb_w11a_mem70.dat"
- tag: [default, viv, sys_w11a, br_arty, stim2]
test: |
tbrun_tbwrri --hxon --lsuf stim2 --pack rw11 tb_w11a_br_arty${ms} \

41
rtl/vlib/rutil.vhd Normal file
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@@ -0,0 +1,41 @@
-- $Id: rutil.vhd 917 2017-06-25 18:05:28Z mueller $
--
-- Copyright 2017- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Package Name: rutil
-- Description: Miscellaneous helper functions
--
-- Dependencies: -
-- Tool versions: ise 14.7; viv 2017.1; ghdl 0.34
-- Revision History:
-- Date Rev Version Comment
-- 2017-06-25 44 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package rutil is
function imin (left, right: integer) return integer;
end package rutil;
package body rutil is
function imin (left, right: integer) return integer is
begin
if left < right then
return left;
else
return right;
end if;
end imin;
end package body rutil;

7
tools/tcl/tst_sram/test_all.tcl
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@@ -1,6 +1,6 @@
# $Id: test_all.tcl 895 2017-05-07 07:38:47Z mueller $
# $Id: test_all.tcl 914 2017-06-25 06:17:18Z mueller $
#
# Copyright 2014-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
# Copyright 2014-2017 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
#
# This program is free software; you may redistribute and/or modify it under
# the terms of the GNU General Public License as published by the Free
@@ -13,6 +13,7 @@
#
# Revision History:
# Date Rev Version Comment
# 2017-06-19 914 2.2 17bit support; use sstat(awidth); add isnarrow
# 2016-07-09 784 2.1 add test_all test driver
# 2014-11-23 606 2.0 use new rlink v4 iface
# 2014-08-14 582 1.0 Initial version
@@ -105,7 +106,7 @@ namespace eval tst_sram {
set maddrh 0x0000
set maddrl 0x0000
if {[rlink::issim]} {
set maddrh [expr {$wide ? 0x003f : 0x0003}]
set maddrh [expr {[iswide] ? 0x3f : [isnarrow] ? 0x01: 0x03}]
set maddrl 0xfffc
}

136
tools/tcl/tst_sram/test_regs.tcl
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@@ -1,6 +1,6 @@
# $Id: test_regs.tcl 785 2016-07-10 12:22:41Z mueller $
# $Id: test_regs.tcl 917 2017-06-25 18:05:28Z mueller $
#
# Copyright 2016- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
# Copyright 2016-2017 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
#
# This program is free software; you may redistribute and/or modify it under
# the terms of the GNU General Public License as published by the Free
@@ -13,6 +13,7 @@
#
# Revision History:
# Date Rev Version Comment
# 2017-06-25 917 1.2 17bit support; use sstat(awidth); add isnarrow
# 2016-07-10 785 1.1 add memory test (touch evenly distributed addr)
# 2016-07-09 784 1.0 Initial version (ported from tb_tst_sram_stim.dat)
#
@@ -51,7 +52,7 @@ namespace eval tst_sram {
#
#-------------------------------------------------------------------------
rlc log " test 1b: test maddrh range"
set maddrh_max [expr {[iswide] ? 0x3f : 0x03}]
set maddrh_max [expr {[iswide] ? 0x3f : [isnarrow] ? 0x01: 0x03}]
rlc exec \
-wreg sr.maddrh 0xffff \
-rreg sr.maddrh -edata $maddrh_max
@@ -235,7 +236,7 @@ namespace eval tst_sram {
#
#-------------------------------------------------------------------------
rlc log " test 5: test sstat bits"
set sm [rutil::com16 [regbld tst_sram::SSTAT wide]]
set sm [rutil::com16 [regbld tst_sram::SSTAT {awidth -1}]]
rlc exec \
-wreg sr.sstat 0 \
-rreg sr.sstat -edata 0 $sm \
@@ -255,26 +256,51 @@ namespace eval tst_sram {
#-------------------------------------------------------------------------
rlc log " test 6: test memory (touch 5(+5) evenly spaced addresses)"
# writes
# 18bit: 0x000000 0x010001 0x020002 0x030003 0x03ffff
rlc exec \
-wreg sr.mdih 0x5500 \
-wreg sr.mdil 0xaa00 \
-wreg sr.maddrl 0x0000 \
-wreg sr.mcmd [regbld tst_sram::MCMD ld inc we {be 0xf} {addrh 0x00}] \
-wreg sr.mdih 0x5501 \
-wreg sr.mdil 0xaa01 \
-wreg sr.mcmd [regbld tst_sram::MCMD ld inc we {be 0xf} {addrh 0x01}] \
-wreg sr.mdih 0x5502 \
-wreg sr.mdil 0xaa02 \
-wreg sr.mcmd [regbld tst_sram::MCMD ld inc we {be 0xf} {addrh 0x02}] \
-wreg sr.mdih 0x5503 \
-wreg sr.mdil 0xaa03 \
-wreg sr.mcmd [regbld tst_sram::MCMD ld inc we {be 0xf} {addrh 0x03}] \
-rreg sr.maddrl -edata 0x0004 \
-wreg sr.mdih 0x5504 \
-wreg sr.mdil 0xaa04 \
-wreg sr.maddrl 0xffff \
-wreg sr.mcmd [regbld tst_sram::MCMD ld we {be 0xf} {addrh 0x03}]
if {[isnarrow]} {
# 17bit: 0x000000 0x004001 0x010002 0x014003 0x01ffff
rlc exec \
-wreg sr.mdih 0x5500 \
-wreg sr.mdil 0xaa00 \
-wreg sr.maddrl 0x0000 \
-wreg sr.mcmd [regbld tst_sram::MCMD ld inc we {be 0xf} {addrh 0x00}] \
-wreg sr.mdih 0x5501 \
-wreg sr.mdil 0xaa01 \
-wreg sr.maddrl 0x4001 \
-wreg sr.mcmd [regbld tst_sram::MCMD ld inc we {be 0xf} {addrh 0x00}] \
-wreg sr.mdih 0x5502 \
-wreg sr.mdil 0xaa02 \
-wreg sr.maddrl 0x0002 \
-wreg sr.mcmd [regbld tst_sram::MCMD ld inc we {be 0xf} {addrh 0x01}] \
-wreg sr.mdih 0x5503 \
-wreg sr.mdil 0xaa03 \
-wreg sr.maddrl 0x4003 \
-wreg sr.mcmd [regbld tst_sram::MCMD ld inc we {be 0xf} {addrh 0x01}] \
-wreg sr.mdih 0x5504 \
-wreg sr.mdil 0xaa04 \
-wreg sr.maddrl 0xffff \
-wreg sr.mcmd [regbld tst_sram::MCMD ld we {be 0xf} {addrh 0x01}]
} else {
# 18bit: 0x000000 0x010001 0x020002 0x030003 0x03ffff
rlc exec \
-wreg sr.mdih 0x5500 \
-wreg sr.mdil 0xaa00 \
-wreg sr.maddrl 0x0000 \
-wreg sr.mcmd [regbld tst_sram::MCMD ld inc we {be 0xf} {addrh 0x00}] \
-wreg sr.mdih 0x5501 \
-wreg sr.mdil 0xaa01 \
-wreg sr.mcmd [regbld tst_sram::MCMD ld inc we {be 0xf} {addrh 0x01}] \
-wreg sr.mdih 0x5502 \
-wreg sr.mdil 0xaa02 \
-wreg sr.mcmd [regbld tst_sram::MCMD ld inc we {be 0xf} {addrh 0x02}] \
-wreg sr.mdih 0x5503 \
-wreg sr.mdil 0xaa03 \
-wreg sr.mcmd [regbld tst_sram::MCMD ld inc we {be 0xf} {addrh 0x03}] \
-rreg sr.maddrl -edata 0x0004 \
-wreg sr.mdih 0x5504 \
-wreg sr.mdil 0xaa04 \
-wreg sr.maddrl 0xffff \
-wreg sr.mcmd [regbld tst_sram::MCMD ld we {be 0xf} {addrh 0x03}]
}
# 22bit: 0x040000 0x100001 0x200002 0x300003 0x3fffff
if {[iswide]} {
rlc exec \
@@ -298,25 +324,49 @@ namespace eval tst_sram {
-wreg sr.mcmd [regbld tst_sram::MCMD ld we {be 0xf} {addrh 0x3f}]
}
# reads
rlc exec \
-wreg sr.maddrl 0x0000 \
-wreg sr.mcmd [regbld tst_sram::MCMD ld inc {be 0xf} {addrh 0x00}] \
-rreg sr.mdoh -edata 0x5500 \
-rreg sr.mdol -edata 0xaa00 \
-wreg sr.mcmd [regbld tst_sram::MCMD ld inc {be 0xf} {addrh 0x01}] \
-rreg sr.mdoh -edata 0x5501 \
-rreg sr.mdol -edata 0xaa01 \
-wreg sr.mcmd [regbld tst_sram::MCMD ld inc {be 0xf} {addrh 0x02}] \
-rreg sr.mdoh -edata 0x5502 \
-rreg sr.mdol -edata 0xaa02 \
-wreg sr.mcmd [regbld tst_sram::MCMD ld inc {be 0xf} {addrh 0x03}] \
-rreg sr.mdoh -edata 0x5503 \
-rreg sr.mdol -edata 0xaa03 \
-rreg sr.maddrl -edata 0x0004 \
-wreg sr.maddrl 0xffff \
-wreg sr.mcmd [regbld tst_sram::MCMD ld {be 0xf} {addrh 0x03}] \
-rreg sr.mdoh -edata 0x5504 \
-rreg sr.mdol -edata 0xaa04
if {[isnarrow]} {
rlc exec \
-wreg sr.maddrl 0x0000 \
-wreg sr.mcmd [regbld tst_sram::MCMD ld inc {be 0xf} {addrh 0x00}] \
-rreg sr.mdoh -edata 0x5500 \
-rreg sr.mdol -edata 0xaa00 \
-wreg sr.maddrl 0x4001 \
-wreg sr.mcmd [regbld tst_sram::MCMD ld inc {be 0xf} {addrh 0x00}] \
-rreg sr.mdoh -edata 0x5501 \
-rreg sr.mdol -edata 0xaa01 \
-wreg sr.maddrl 0x0002 \
-wreg sr.mcmd [regbld tst_sram::MCMD ld inc {be 0xf} {addrh 0x01}] \
-rreg sr.mdoh -edata 0x5502 \
-rreg sr.mdol -edata 0xaa02 \
-wreg sr.maddrl 0x4003 \
-wreg sr.mcmd [regbld tst_sram::MCMD ld inc {be 0xf} {addrh 0x01}] \
-rreg sr.mdoh -edata 0x5503 \
-rreg sr.mdol -edata 0xaa03 \
-wreg sr.maddrl 0xffff \
-wreg sr.mcmd [regbld tst_sram::MCMD ld {be 0xf} {addrh 0x01}] \
-rreg sr.mdoh -edata 0x5504 \
-rreg sr.mdol -edata 0xaa04
} else {
rlc exec \
-wreg sr.maddrl 0x0000 \
-wreg sr.mcmd [regbld tst_sram::MCMD ld inc {be 0xf} {addrh 0x00}] \
-rreg sr.mdoh -edata 0x5500 \
-rreg sr.mdol -edata 0xaa00 \
-wreg sr.mcmd [regbld tst_sram::MCMD ld inc {be 0xf} {addrh 0x01}] \
-rreg sr.mdoh -edata 0x5501 \
-rreg sr.mdol -edata 0xaa01 \
-wreg sr.mcmd [regbld tst_sram::MCMD ld inc {be 0xf} {addrh 0x02}] \
-rreg sr.mdoh -edata 0x5502 \
-rreg sr.mdol -edata 0xaa02 \
-wreg sr.mcmd [regbld tst_sram::MCMD ld inc {be 0xf} {addrh 0x03}] \
-rreg sr.mdoh -edata 0x5503 \
-rreg sr.mdol -edata 0xaa03 \
-rreg sr.maddrl -edata 0x0004 \
-wreg sr.maddrl 0xffff \
-wreg sr.mcmd [regbld tst_sram::MCMD ld {be 0xf} {addrh 0x03}] \
-rreg sr.mdoh -edata 0x5504 \
-rreg sr.mdol -edata 0xaa04
}
if {[iswide]} {
rlc exec \
-wreg sr.maddrl 0x0000 \

29
tools/tcl/tst_sram/test_seq.tcl
View File

@@ -1,6 +1,6 @@
# $Id: test_seq.tcl 895 2017-05-07 07:38:47Z mueller $
# $Id: test_seq.tcl 917 2017-06-25 18:05:28Z mueller $
#
# Copyright 2016- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
# Copyright 2016-2017 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
#
# This program is free software; you may redistribute and/or modify it under
# the terms of the GNU General Public License as published by the Free
@@ -13,6 +13,7 @@
#
# Revision History:
# Date Rev Version Comment
# 2017-06-25 917 1.2 17bit support; use sstat(awidth); use isnarrow
# 2016-07-10 785 1.1 add wswap and wloop tests
# 2016-07-09 784 1.0 Initial version (ported from tb_tst_sram_stim.dat)
#
@@ -40,7 +41,7 @@ namespace eval tst_sram {
rlc wtlam $tout
# harvest attn and check sequencer status
# also check rlink command status (RB_STAT(1) <= R_REGS.sfail)
set seqmsk [rutil::com16 [regbld tst_sram::SSTAT wide]]; # ign sstat.wide !
set seqmsk [rutil::com16 [regbld tst_sram::SSTAT {awidth -1}]]
set stamsk [regbld rlink::STAT {stat -1} rbtout rbnak rberr];
if {$seaddr == 0} { # fail=0 --> check saddr
@@ -80,7 +81,7 @@ namespace eval tst_sram {
#
set errcnt 0
rlc errcnt -clear
set sm [rutil::com16 [regbld tst_sram::SSTAT wide]]
set sm [rutil::com16 [regbld tst_sram::SSTAT {awidth -1}]]
rlink::anena 1; # enable attn notify
@@ -416,21 +417,24 @@ namespace eval tst_sram {
lappend clist { 0 r 1111 0x000003 0x03132333};
scmd_write $clist
# start sequencer with loop=1,xora=1 and maddr=3fff0 (will loop to 3ffff)
test_seq_setxor 0x03 0xfff0 0x0000 0x0000
set maddrh_seq [expr {[isnarrow] ? 0x01: 0x03}]
# start seq >17bit: loop=1,xora=1 and maddr=3fff0 (will loop to 3ffff)
# start seq =17bit: loop=1,xora=1 and maddr=1fff0 (will loop to 1ffff)
test_seq_setxor $maddrh_seq 0xfff0 0x0000 0x0000
test_seq_srun [regbld tst_sram::SSTAT loop xora veri] $tout
# check that maddr incremented
rlc exec \
-rreg sr.maddrh -edata 0x0003 \
-rreg sr.maddrh -edata $maddrh_seq \
-rreg sr.maddrl -edata 0xffff
# last iteration will write into
# last iteration will write into (for >17bit):
# 00000 xor 03ffff -> 03ffff (00102030)
# 00001 xor 03ffff -> 03fffe (01112131)
# 00002 xor 03ffff -> 03fffd (02122232)
# 00003 xor 03ffff -> 03fffc (03132333)
# read back 4 longwords 03fffc..03ffff
rlc exec \
-wreg sr.maddrh 0x0003 \
-wreg sr.maddrh $maddrh_seq \
-wreg sr.maddrl 0xfffc \
-rblk sr.mblk 8 -edata {0x0313 0x2333 \
0x0212 0x2232 \
@@ -452,13 +456,14 @@ namespace eval tst_sram {
lappend clist { 0 r 1111 0x000103 0x00000000};
scmd_write $clist
# start with loop=1,xora=1 and maddr=03fff0 (tried to loop to 03ffff)
test_seq_setxor 0x03 0xfff0 0x0000 0x0000
# start seq >17bit: loop=1,xora=1 and maddr=03fff0 (tried to loop to 03ffff)
# start seq =17bit: loop=1,xora=1 and maddr=01fff0 (tried to loop to 01ffff)
test_seq_setxor $maddrh_seq 0xfff0 0x0000 0x0000
test_seq_srun [regbld tst_sram::SSTAT loop xora veri] $tout \
5 0x0111 0x2131
# check that maddr do not increment (fail on first loop !)
rlc exec \
-rreg sr.maddrh -edata 0x0003 \
-rreg sr.maddrh -edata $maddrh_seq \
-rreg sr.maddrl -edata 0xfff0
# finally clear veri error

37
tools/tcl/tst_sram/util.tcl
View File

@@ -1,4 +1,4 @@
# $Id: util.tcl 895 2017-05-07 07:38:47Z mueller $
# $Id: util.tcl 914 2017-06-25 06:17:18Z mueller $
#
# Copyright 2011-2017 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
#
@@ -13,6 +13,7 @@
#
# Revision History:
# Date Rev Version Comment
# 2017-06-19 914 1.3 17bit support; use sstat(awidth); add isnarrow
# 2017-04-22 883 1.2.1 setup: now idempotent
# 2016-07-09 784 1.2 22bit support: mask sstat(wide); add iswide
# 2015-04-03 661 1.1 drop estatdef (stat err check default now)
@@ -32,12 +33,13 @@ namespace eval tst_sram {
#
variable nscmd 0; # length of current sequencer command list
variable tout 10.; # default time out
variable iswide -1; # sstat.wide cache
variable iswide -1; # sstat.awidth=22 cache
variable isnarrow -1; # sstat.awidth=17 cache
#
# setup register descriptions for tst_sram core design ---------------------
#
regdsc MCMD {ld 14} {inc 13} {we 12} {be 11 4} {addrh 5 6}
regdsc SSTAT {wide 15} {wswap 9} {wloop 8} \
regdsc SSTAT {awidth 15 3} {wswap 9} {wloop 8} \
{loop 7} {xord 6} {xora 5} {veri 4} {fail 1} {run 0}
regdsc SCMD {wait 31 4} {we 24} {be 23 4} {addr 17 18}
#
@@ -74,17 +76,34 @@ namespace eval tst_sram {
-wreg sr.sstat 0
}
#
# checkawidth: inspect SSTAT(awidth) ---------------------------------------
#
proc checkawidth {} {
variable iswide
variable isnarrow
rlc exec -rreg sr.sstat sstat
set awidth [regget tst_sram::SSTAT(awidth) $sstat]
set iswide [expr {$awidth + 16 == 22}]
set isnarrow [expr {$awidth + 16 == 17}]
return ""
}
#
# iswide: 1 if 22bit system ------------------------------------------------
#
proc iswide {} {
variable iswide
if {$iswide < 0} {
rlc exec -rreg sr.sstat sstat
set iswide [regget tst_sram::SSTAT(wide) $sstat]
}
if {$iswide < 0} { checkawidth }
return $iswide
}
#
# isnarrow: 1 if 17bit system ----------------------------------------------
#
proc isnarrow {} {
variable isnarrow
if {$isnarrow < 0} { checkawidth }
return $isnarrow
}
#
# scmd_write: write a scmd list --------------------------------------------
#
proc scmd_write {scmdlist} {
@@ -179,7 +198,7 @@ namespace eval tst_sram {
variable nscmd
if {$tout == 0} {set tout $tst_sram::tout}
if {$nscmd == 0} {error "no or empty scmd list loaded"}
set sm [rutil::com16 [regbld tst_sram::SSTAT wide]]
set sm [rutil::com16 [regbld tst_sram::SSTAT {awidth -1}]]
rlc exec -init 0 1
rlc exec -wreg sr.sstat [regbld tst_sram::SSTAT xord xora veri] \
-wreg sr.mdih $mdih \
@@ -214,7 +233,7 @@ namespace eval tst_sram {
variable nscmd
if {$tout == 0} {set tout $tst_sram::tout}
if {$nscmd == 0} {error "no or empty scmd list loaded"}
set sm [rutil::com16 [regbld tst_sram::SSTAT wide]]
set sm [rutil::com16 [regbld tst_sram::SSTAT {awidth -1}]]
set sstat [regbldkv tst_sram::SSTAT wswap $wide wloop $wide loop 1 \
xord 1 xora 1 veri 1]
rlc exec -init 0 1