add forgotten file for Arty S7 with MIG

2026-03-05 19:20:07 +00:00 · 2019-02-08 19:48:57 +01:00
parent f613babe57
commit 51c2cf328c
1 changed files with 143 additions and 0 deletions
--- a/rtl/bplib/artys7/mig_a.prj
+++ b/rtl/bplib/artys7/mig_a.prj
@@ -0,0 +1,143 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
+<Project NoOfControllers="1">
+
+  <ModuleName>migui_artys7</ModuleName>
+
+  <dci_inouts_inputs>1</dci_inouts_inputs>
+
+  <dci_inputs>1</dci_inputs>
+
+  <Debug_En>OFF</Debug_En>
+
+  <DataDepth_En>1024</DataDepth_En>
+
+  <LowPower_En>ON</LowPower_En>
+
+  <XADC_En>Disabled</XADC_En>
+
+  <TargetFPGA>xc7s50-csga324/-1</TargetFPGA>
+
+  <Version>4.2</Version>
+
+  <SystemClock>No Buffer</SystemClock>
+
+  <ReferenceClock>No Buffer</ReferenceClock>
+
+  <SysResetPolarity>ACTIVE HIGH</SysResetPolarity>
+
+  <BankSelectionFlag>FALSE</BankSelectionFlag>
+
+  <InternalVref>1</InternalVref>
+
+  <dci_hr_inouts_inputs>50 Ohms</dci_hr_inouts_inputs>
+
+  <dci_cascade>0</dci_cascade>
+
+  <Controller number="0">
+    <MemoryDevice>DDR3_SDRAM/Components/MT41K128M16XX-15E</MemoryDevice>
+    <TimePeriod>3125</TimePeriod>
+    <VccAuxIO>1.8V</VccAuxIO>
+    <PHYRatio>4:1</PHYRatio>
+    <InputClkFreq>160</InputClkFreq>
+    <UIExtraClocks>0</UIExtraClocks>
+    <MMCM_VCO>640</MMCM_VCO>
+    <MMCMClkOut0> 1.000</MMCMClkOut0>
+    <MMCMClkOut1>1</MMCMClkOut1>
+    <MMCMClkOut2>1</MMCMClkOut2>
+    <MMCMClkOut3>1</MMCMClkOut3>
+    <MMCMClkOut4>1</MMCMClkOut4>
+    <DataWidth>16</DataWidth>
+    <DeepMemory>1</DeepMemory>
+    <DataMask>1</DataMask>
+    <ECC>Disabled</ECC>
+    <Ordering>Strict</Ordering>
+    <BankMachineCnt>2</BankMachineCnt>
+    <CustomPart>FALSE</CustomPart>
+    <NewPartName></NewPartName>
+    <RowAddress>14</RowAddress>
+    <ColAddress>10</ColAddress>
+    <BankAddress>3</BankAddress>
+    <MemoryVoltage>1.35V</MemoryVoltage>
+    <UserMemoryAddressMap>ROW_BANK_COLUMN</UserMemoryAddressMap>
+    <PinSelection>
+      <Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="U2" SLEW="" VCCAUX_IO="" name="ddr3_addr[0]"/>
+      <Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="P6" SLEW="" VCCAUX_IO="" name="ddr3_addr[10]"/>
+      <Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="T5" SLEW="" VCCAUX_IO="" name="ddr3_addr[11]"/>
+      <Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="R6" SLEW="" VCCAUX_IO="" name="ddr3_addr[12]"/>
+      <Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="U6" SLEW="" VCCAUX_IO="" name="ddr3_addr[13]"/>
+      <Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="R4" SLEW="" VCCAUX_IO="" name="ddr3_addr[1]"/>
+      <Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="V2" SLEW="" VCCAUX_IO="" name="ddr3_addr[2]"/>
+      <Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="V4" SLEW="" VCCAUX_IO="" name="ddr3_addr[3]"/>
+      <Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="T3" SLEW="" VCCAUX_IO="" name="ddr3_addr[4]"/>
+      <Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="R7" SLEW="" VCCAUX_IO="" name="ddr3_addr[5]"/>
+      <Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="V6" SLEW="" VCCAUX_IO="" name="ddr3_addr[6]"/>
+      <Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="T6" SLEW="" VCCAUX_IO="" name="ddr3_addr[7]"/>
+      <Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="U7" SLEW="" VCCAUX_IO="" name="ddr3_addr[8]"/>
+      <Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="V7" SLEW="" VCCAUX_IO="" name="ddr3_addr[9]"/>
+      <Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="V5" SLEW="" VCCAUX_IO="" name="ddr3_ba[0]"/>
+      <Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="T1" SLEW="" VCCAUX_IO="" name="ddr3_ba[1]"/>
+      <Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="U3" SLEW="" VCCAUX_IO="" name="ddr3_ba[2]"/>
+      <Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="V3" SLEW="" VCCAUX_IO="" name="ddr3_cas_n"/>
+      <Pin IN_TERM="" IOSTANDARD="DIFF_SSTL135" PADName="T4" SLEW="" VCCAUX_IO="" name="ddr3_ck_n[0]"/>
+      <Pin IN_TERM="" IOSTANDARD="DIFF_SSTL135" PADName="R5" SLEW="" VCCAUX_IO="" name="ddr3_ck_p[0]"/>
+      <Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="T2" SLEW="" VCCAUX_IO="" name="ddr3_cke[0]"/>
+      <Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="R3" SLEW="" VCCAUX_IO="" name="ddr3_cs_n[0]"/>
+      <Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="K4" SLEW="" VCCAUX_IO="" name="ddr3_dm[0]"/>
+      <Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="M3" SLEW="" VCCAUX_IO="" name="ddr3_dm[1]"/>
+      <Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="K2" SLEW="" VCCAUX_IO="" name="ddr3_dq[0]"/>
+      <Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="N1" SLEW="" VCCAUX_IO="" name="ddr3_dq[10]"/>
+      <Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="N5" SLEW="" VCCAUX_IO="" name="ddr3_dq[11]"/>
+      <Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="M2" SLEW="" VCCAUX_IO="" name="ddr3_dq[12]"/>
+      <Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="P1" SLEW="" VCCAUX_IO="" name="ddr3_dq[13]"/>
+      <Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="M1" SLEW="" VCCAUX_IO="" name="ddr3_dq[14]"/>
+      <Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="P2" SLEW="" VCCAUX_IO="" name="ddr3_dq[15]"/>
+      <Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="K3" SLEW="" VCCAUX_IO="" name="ddr3_dq[1]"/>
+      <Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="L4" SLEW="" VCCAUX_IO="" name="ddr3_dq[2]"/>
+      <Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="M6" SLEW="" VCCAUX_IO="" name="ddr3_dq[3]"/>
+      <Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="K6" SLEW="" VCCAUX_IO="" name="ddr3_dq[4]"/>
+      <Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="M4" SLEW="" VCCAUX_IO="" name="ddr3_dq[5]"/>
+      <Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="L5" SLEW="" VCCAUX_IO="" name="ddr3_dq[6]"/>
+      <Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="L6" SLEW="" VCCAUX_IO="" name="ddr3_dq[7]"/>
+      <Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="N4" SLEW="" VCCAUX_IO="" name="ddr3_dq[8]"/>
+      <Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="R1" SLEW="" VCCAUX_IO="" name="ddr3_dq[9]"/>
+      <Pin IN_TERM="" IOSTANDARD="DIFF_SSTL135" PADName="L1" SLEW="" VCCAUX_IO="" name="ddr3_dqs_n[0]"/>
+      <Pin IN_TERM="" IOSTANDARD="DIFF_SSTL135" PADName="N2" SLEW="" VCCAUX_IO="" name="ddr3_dqs_n[1]"/>
+      <Pin IN_TERM="" IOSTANDARD="DIFF_SSTL135" PADName="K1" SLEW="" VCCAUX_IO="" name="ddr3_dqs_p[0]"/>
+      <Pin IN_TERM="" IOSTANDARD="DIFF_SSTL135" PADName="N3" SLEW="" VCCAUX_IO="" name="ddr3_dqs_p[1]"/>
+      <Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="P5" SLEW="" VCCAUX_IO="" name="ddr3_odt[0]"/>
+      <Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="U1" SLEW="" VCCAUX_IO="" name="ddr3_ras_n"/>
+      <Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="J6" SLEW="" VCCAUX_IO="" name="ddr3_reset_n"/>
+      <Pin IN_TERM="" IOSTANDARD="SSTL135" PADName="P7" SLEW="" VCCAUX_IO="" name="ddr3_we_n"/>
+    </PinSelection>
+    <System_Control>
+      <Pin Bank="Select Bank" PADName="No connect" name="sys_rst"/>
+      <Pin Bank="Select Bank" PADName="No connect" name="init_calib_complete"/>
+      <Pin Bank="Select Bank" PADName="No connect" name="tg_compare_error"/>
+    </System_Control>
+    <TimingParameters>
+      <Parameters tcke="5.625" tfaw="45" tras="36" trcd="13.5" trefi="7.8" trfc="160" trp="13.5" trrd="7.5" trtp="7.5" twtr="7.5"/>
+    </TimingParameters>
+    <mrBurstLength name="Burst Length">8 - Fixed</mrBurstLength>
+    <mrBurstType name="Read Burst Type and Length">Sequential</mrBurstType>
+    <mrCasLatency name="CAS Latency">5</mrCasLatency>
+    <mrMode name="Mode">Normal</mrMode>
+    <mrDllReset name="DLL Reset">No</mrDllReset>
+    <mrPdMode name="DLL control for precharge PD">Slow Exit</mrPdMode>
+    <emrDllEnable name="DLL Enable">Enable</emrDllEnable>
+    <emrOutputDriveStrength name="Output Driver Impedance Control">RZQ/6</emrOutputDriveStrength>
+    <emrMirrorSelection name="Address Mirroring">Disable</emrMirrorSelection>
+    <emrCSSelection name="Controller Chip Select Pin">Enable</emrCSSelection>
+    <emrRTT name="RTT (nominal) - On Die Termination (ODT)">RZQ/6</emrRTT>
+    <emrPosted name="Additive Latency (AL)">0</emrPosted>
+    <emrOCD name="Write Leveling Enable">Disabled</emrOCD>
+    <emrDQS name="TDQS enable">Enabled</emrDQS>
+    <emrRDQS name="Qoff">Output Buffer Enabled</emrRDQS>
+    <mr2PartialArraySelfRefresh name="Partial-Array Self Refresh">Full Array</mr2PartialArraySelfRefresh>
+    <mr2CasWriteLatency name="CAS write latency">5</mr2CasWriteLatency>
+    <mr2AutoSelfRefresh name="Auto Self Refresh">Enabled</mr2AutoSelfRefresh>
+    <mr2SelfRefreshTempRange name="High Temparature Self Refresh Rate">Normal</mr2SelfRefreshTempRange>
+    <mr2RTTWR name="RTT_WR - Dynamic On Die Termination (ODT)">Dynamic ODT off</mr2RTTWR>
+    <PortInterface>NATIVE</PortInterface>
+  </Controller>
+
+</Project>