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mirror of https://github.com/wfjm/w11.git synced 2026-04-15 01:13:44 +00:00

cpu_mmu.mac BUGFIX; minor changes

- tools/make/generic_asm11.mk: fix ldart target rule
- tools/tcode/Makefile: add header line for %.te11 target
- tools/tcode/cpu_mmu.mac
  - C2.6: add e11 handling (w11 and e11 mmr1 difference)
  - D2.1: BUGFIX: use mmr0 page mode for PSW PM if ico=1
  - D2.1: add e11 handling (no PC inc on fetch abort)
This commit is contained in:
wfjm
2023-03-20 09:35:27 +01:00
parent 0e03584e5a
commit 5990a8fe0a
20 changed files with 103 additions and 53 deletions

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@@ -30,12 +30,13 @@ The full set of tests is only run for tagged releases.
### Summary
- revamp tap and bridge handling
- support e11 as additional emulator for most systems
- support E11 as additional emulator for most systems
### New features
- new tools
- tools/e11: added configuration files for e11
- oskit/\*/: added startup files for e11 where possible
- tools/e11: added configuration files for E11
- tools/(tcode|xxdp): added startup files for E11
- oskit/\*/: added startup files for E11 where feasible
### Changes
- tools changes
@@ -51,6 +52,8 @@ The full set of tests is only run for tagged releases.
### Bug Fixes
- tools/bin/asm-11
- BUGFIX: fix directly nested .if behavior
- tools/tcode
- BUGFIX: use mmr0 page mode for PSW PM if ico=1
- src/librtools
- RtimerFd.cpp: BUGFIX: SetRelative(): correct is-positive check

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@@ -16,10 +16,10 @@ acceptable implementation difference. An instruction re-execution after
an MMU abort relies always on `MMR2`. Only error messages that give a _"PC at
abort"_ might differ.
SimH implements the 11/70 behavior, the `PC` is incremented after the
SimH and E11 implement the 11/70 behavior, the `PC` is incremented after the
successful load of the instruction register.
However, test and verification codes might be sensitive to this behavior.
A [tcode](../tools/tcode/README.md) verifies this saved `PS` and
distinguished between w11 and SimH
(see [cpu_mmu](../tools/tcode/cpu_mmu.mac) tests B4.1).
distinguishes between w11, SimH, and E11.
(see [cpu_mmu](../tools/tcode/cpu_mmu.mac) tests B4.1 and D2.1).

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@@ -0,0 +1,20 @@
## Known differences between w11a and KB11-C (11/70)
### `SP` decremented only once after 1st vector push abort
The 11/70 calculates in a vector flow the target addresses for 1st and 2nd
vector push before the 1st memory access is done. State `SVC.50` decrements
`SP` by two. State `SVC.60` decrements `SP` again by two, starts the 1st
push, and checks for check limit. Therefore, the `SP` is decremented twice
when a 1st stack push fails. `MMR1` consequently shows two `SP` decrements
in that case.
The w11 handles the two vector push separately, `SP` is decremented and the
stack limit is checked before each push. Therefore, the `SP` is decremented
only once when the 1st push fails, and `MMR1` consequently shows one `SP`
decrement.
However, test and verification codes might be sensitive to this behavior.
A [tcode](../tools/tcode/README.md) verifies `MMR1` after a vector push
abort and distinguishes between w11 and SimH and e11
(see [cpu_mmu](../tools/tcode/cpu_mmu.mac) tests C2.6).

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@@ -5,19 +5,19 @@ The "Ersatz-11" or `e11` a PDP-11 software emulator available from
source, but can be used with some limitations free of charge for
non-commercial applications.
The device emulation concept of e11 is quite different compared to SimH.
The device emulation concept of E11 is quite different compared to SimH.
The operation and behavior of the two emulators differs therefore
- the console DL11 is always connected to the session window for e11.
- the console DL11 is always connected to the session window for E11.
It is not possible to connect it to a telnet session as done for SimH.
- it is not possible to set the 2nd DL11 into 7-bit mode
- device controllers are only activated when at least one unit is mounted.
All disk and tape controllers have therefore a `NULL` mount point active
for the highest supported unit.
- the Ethernet emulation in e11 is currently not supported, the DEUNA device
- the Ethernet emulation in E11 is currently not supported, the DEUNA device
is therefore not active.
Under [tools/e11](../tools/e11) two setup files are provided which
configure e11 to reflect the w11a setup as closely as possible:
configure E11 to reflect the w11a setup as closely as possible:
- [setup_w11a_min.ecmd](../tools/e11/setup_w11a_min.ecmd)
Minimal configuration for low memory boards (as on s3board or Basys3)
- processor: 11/70, no FPP, 1 Mbyte
@@ -27,7 +27,7 @@ configure e11 to reflect the w11a setup as closely as possible:
- processor: 4 Mbyte memory (as on Nexys and Arty type boards)
- periphery: in addition DZ11, RL11/RL02, RM70/RP06, TM11/TU10
**Note**: tested with e11 V7.4, might not work with V7.3 and earlier.
**Note**: tested with E11 V7.4, might not work with V7.3 and earlier.
Startup scripts are provided for some oskits. They usually call the `w11a_max`
configuration and are used with

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@@ -9,11 +9,13 @@ The issues of the w11 CPU and systems are listed in a separate document
- [Instruction fetch after `SPL`](w11a_diff_70_spl_bug.md)
- [`CLR` and `SXT` do a write](w11a_diff_70_clr_sxt_write.md)
- [State of N and Z and registers after a `DIV` abort with `V=1`](w11a_diff_70_div_after_v1.md)
- instruction abort handling
- [`PC` is incremented before an instruction fetch abort](w11a_diff_70_fetch_abort.md)
- vector flow abort handling
- [`SP` decremented only once after 1st vector push abort](w11a_diff_70_vecflow_abort_sp.md)
- stack limit and stack error behavior
- [Stack limit checks done independent of register set](w11a_diff_70_stklim_rset.md)
- [No unconditional instruction fetch after stack error abort](w11a_diff_70_ser_forced_fetch.md)
- instruction abort handling
- [`PC` is incremented before an instruction fetch abort](w11a_diff_70_fetch_abort.md)
- memory management behavior
- [`MMR0` instruction complete implementation differences](w11a_diff_70_instruction_complete.md)
- [MMU traps not suppressed when MMU register accessed](w11a_diff_70_mmu_trap_suppression.md)

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@@ -5,7 +5,7 @@ For general system setup see notes on
- [FPGA Board setup](w11a_board_connection.md)
- [Rlink and Backend Server setup](w11a_backend_setup.md)
- [SimH simulator setup](w11a_simh_setup.md)
- [e11 simulator setup](w11a_e11_setup.md)
- [E11 simulator setup](w11a_e11_setup.md)
Ready to be used 'oskits' are provided under
[tools/oskit](../tools/oskit/README.md).

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@@ -7,7 +7,7 @@ This directory tree contains **many tools** and is organized in
| [bin_xilinx_wrapper](bin_xilinx_wrapper) | wrappers for Xilinx environments |
| [dasm-11](dasm-11) | environment for the `dasm-11` disassembler |
| [dox](dox) | configuration files for Doxygen |
| [e11](e11) | configuration files for `e11` |
| [e11](e11) | configuration files for E11 emulator |
| [exptest](exptest) | configuration files for `ostest` and other expect based tests |
| [fx2](fx2) | firmware for Cypress FX2 USB interface |
| [gwstart](gwstart) | environment for the `gwstart` command |
@@ -15,7 +15,7 @@ This directory tree contains **many tools** and is organized in
| [man](man) | man pages |
| [mcode](mcode) | miscellaneous stand-alone codes for system tests |
| [oskit](oskit) | support files for OS disk/tape image kits |
| [simh](simh) | configuration files for `SimH pdp11` |
| [simh](simh) | configuration files for `SimH pdp11` emulator |
| [src](src) | C++ sources for rlink backend |
| [sys](sys) | udev rules for USB device handling |
| [tbench](tbench) | w11 test bench |

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@@ -1,9 +1,10 @@
# $Id: generic_asm11.mk 1275 2022-08-10 08:10:40Z mueller $
# $Id: generic_asm11.mk 1382 2023-03-18 21:02:11Z mueller $
# SPDX-License-Identifier: GPL-3.0-or-later
# Copyright 2013-2022 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
# Copyright 2013-2023 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
#
# Revision History:
# Date Rev Version Comment
# 2023-03-14 1382 1.1.1 fix ldart target rule
# 2022-08-08 1275 1.1 add auto-dependency rule
# 2013-04-06 503 1.0.1 use --hostinc for mac2lda
# 2013-03-22 496 1.0 Initial version
@@ -36,7 +37,7 @@ endif
%.lsterr : %.mac
$(ASM11) --olst=%.lsterr $< || true
#
%.lstrt %ldart : %.mac
%.lstrt %.ldart : %.mac
$(MAC2LDA) --hostinc --suff=rt $*
#
# Expect rules

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@@ -6,7 +6,7 @@ See notes on
- [FPGA Board setup](../../../doc/w11a_board_connection.md)
- [Rlink and Backend Server setup](../../../doc/w11a_backend_setup.md)
- [SimH simulator setup](../../../doc/w11a_simh_setup.md)
- [e11 simulator setup](../../../doc/w11a_e11_setup.md)
- [E11 simulator setup](../../../doc/w11a_e11_setup.md)
- [Legal terms](../../../doc/w11a_os_guide.md)
### System properties and intended usage

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@@ -6,7 +6,7 @@ See notes on
- [FPGA Board setup](../../../doc/w11a_board_connection.md)
- [Rlink and Backend Server setup](../../../doc/w11a_backend_setup.md)
- [SimH simulator setup](../../../doc/w11a_simh_setup.md)
- [e11 simulator setup](../../../doc/w11a_e11_setup.md)
- [E11 simulator setup](../../../doc/w11a_e11_setup.md)
- [Legal terms](../../../doc/w11a_os_guide.md)
### System properties and intended usage

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@@ -6,7 +6,7 @@ See notes on
- [FPGA Board setup](../../../doc/w11a_board_connection.md)
- [Rlink and Backend Server setup](../../../doc/w11a_backend_setup.md)
- [SimH simulator setup](../../../doc/w11a_simh_setup.md)
- [e11 simulator setup](../../../doc/w11a_e11_setup.md)
- [E11 simulator setup](../../../doc/w11a_e11_setup.md)
- [Legal terms](../../../doc/w11a_os_guide.md)
### System properties and intended usage

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@@ -6,7 +6,7 @@ See notes on
- [FPGA Board setup](../../../doc/w11a_board_connection.md)
- [Rlink and Backend Server setup](../../../doc/w11a_backend_setup.md)
- [SimH simulator setup](../../../doc/w11a_simh_setup.md)
- [e11 simulator setup](../../../doc/w11a_e11_setup.md)
- [E11 simulator setup](../../../doc/w11a_e11_setup.md)
- [Legal terms](../../../doc/w11a_os_guide.md)
- **and read [README_license.txt](README_license.txt) !!**

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@@ -4,7 +4,7 @@ See notes on
- [FPGA Board setup](../../../doc/w11a_board_connection.md)
- [Rlink and Backend Server setup](../../../doc/w11a_backend_setup.md)
- [SimH simulator setup](../../../doc/w11a_simh_setup.md)
- [e11 simulator setup](../../../doc/w11a_e11_setup.md)
- [E11 simulator setup](../../../doc/w11a_e11_setup.md)
- [Legal terms](../../../doc/w11a_os_guide.md)
- **and read [README_license.txt](README_license.txt) !!**

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@@ -6,7 +6,7 @@ See notes on
- [FPGA Board setup](../../../doc/w11a_board_connection.md)
- [Rlink and Backend Server setup](../../../doc/w11a_backend_setup.md)
- [SimH simulator setup](../../../doc/w11a_simh_setup.md)
- [e11 simulator setup](../../../doc/w11a_e11_setup.md)
- [E11 simulator setup](../../../doc/w11a_e11_setup.md)
- [Legal terms](../../../doc/w11a_os_guide.md)
- **and read [README_license.txt](README_license.txt) !!**

View File

@@ -6,7 +6,7 @@ See notes on
- [FPGA Board setup](../../../doc/w11a_board_connection.md)
- [Rlink and Backend Server setup](../../../doc/w11a_backend_setup.md)
- [SimH simulator setup](../../../doc/w11a_simh_setup.md)
- [e11 simulator setup](../../../doc/w11a_e11_setup.md)
- [E11 simulator setup](../../../doc/w11a_e11_setup.md)
- [Legal terms](../../../doc/w11a_os_guide.md)
- **and read [README_license.txt](README_license.txt) !!**

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@@ -6,7 +6,7 @@ See notes on
- [FPGA Board setup](../../../doc/w11a_board_connection.md)
- [Rlink and Backend Server setup](../../../doc/w11a_backend_setup.md)
- [SimH simulator setup](../../../doc/w11a_simh_setup.md)
- [e11 simulator setup](../../../doc/w11a_e11_setup.md)
- [E11 simulator setup](../../../doc/w11a_e11_setup.md)
- [Legal terms](../../../doc/w11a_os_guide.md)
- **and read [README_license.txt](README_license.txt) !!**

View File

@@ -6,7 +6,7 @@ See notes on
- [FPGA Board setup](../../../doc/w11a_board_connection.md)
- [Rlink and Backend Server setup](../../../doc/w11a_backend_setup.md)
- [SimH simulator setup](../../../doc/w11a_simh_setup.md)
- [e11 simulator setup](../../../doc/w11a_e11_setup.md)
- [E11 simulator setup](../../../doc/w11a_e11_setup.md)
- [Legal terms](../../../doc/w11a_os_guide.md)
### Installation

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@@ -6,7 +6,7 @@ See notes on
- [FPGA Board setup](../../../doc/w11a_board_connection.md)
- [Rlink and Backend Server setup](../../../doc/w11a_backend_setup.md)
- [SimH simulator setup](../../../doc/w11a_simh_setup.md)
- [e11 simulator setup](../../../doc/w11a_e11_setup.md)
- [E11 simulator setup](../../../doc/w11a_e11_setup.md)
- [Legal terms](../../../doc/w11a_os_guide.md)
- **and read [README_license.md](README_license.md) !!**

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@@ -1,9 +1,10 @@
# $Id: Makefile 1275 2022-08-10 08:10:40Z mueller $
# $Id: Makefile 1383 2023-03-20 08:19:14Z mueller $
# SPDX-License-Identifier: GPL-3.0-or-later
# Copyright 2022- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
# Copyright 2022-2023 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
#
# Revision History:
# Date Rev Version Comment
# 2023-03-19 1382 1.1.1 add header line for %.te11 target
# 2022-08-08 1275 1.1 add auto-dependency rule
# 2022-07-29 1264 1.0 Initial version
#---
@@ -35,6 +36,7 @@ DEP_all = $(MAC_all:.mac=.dep)
pdp11 tcode_exec.scmd $* | grep -q "HALT instruction, PC: 002002"
# execute e11 simulation; output goes to tmp_e11_tt0.log
%.te11 : %.lda
@echo "execute $* ---------------------------------------------------"
@rm -f tmp_e11.ini
@echo "@tcode.ecmd" >> tmp_e11.ini
@echo "mount pr: $*.lda" >> tmp_e11.ini

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@@ -1,9 +1,12 @@
; $Id: cpu_mmu.mac 1374 2023-02-18 10:30:46Z mueller $
; $Id: cpu_mmu.mac 1383 2023-03-20 08:19:14Z mueller $
; SPDX-License-Identifier: GPL-3.0-or-later
; Copyright 2022-2023 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
;
; Revision History:
; Date Rev Version Comment
; 2023-03-19 1382 1.1.3 C2.6: add e11 handling (w11 and e11 mmr1 difference)
; D2.1: BUGFIX: use mmr0 page mode for PSW PM if ico=1
; D2.1: add e11 handling (no PC inc on fetch abort)
; 2023-02-17 1374 1.1.2 use push2,pushm,popm
; 2023-01-28 1360 1.1.1 remove <../100> expressions for 6 bit right shift
; 2023-01-27 1358 1.1 use .mcall and mlib; use hta??? macros
@@ -852,10 +855,9 @@ tc0101: mov #1000$,r1 ; ptr to abort bit table
;
; check @(pc)+ behavior
; w11 updates mmr1 in this case, as is also expected in ekbee1
; Simh only adds 'general purpose register updates', thus not pc
; e11 doesnt like this test either
tstb systyp ; skip test if on SimH or e11
blt 100$ ; systyp<0 --> not on w11
; Simh only adds 'general purpose register updates', thus not pc.
cmpb systyp,#sy.sih ; skip test if on SimH
beq 100$
reset
mov -(r1),@#mmr0 ; r1,-2,pc,2 00010 111 11110 001 via ale
hcmpeq (r3),#^b0001011111110001;
@@ -1517,7 +1519,7 @@ tc0206: mov kipdr0,sipdr0 ; super page 0 1-to-1
hcmpeq (sp),#100$ ; PC: return after mov
hcmpeq 2(sp),#cp.cms!cp.pr1 ; PS: should be code signature
;
; check mmr0,mmr2 instruction complete (unless on SimH)
; check mmr0,mmr1,mmr2 instruction complete (unless on SimH)
cmpb systyp,#sy.sih
beq 290$
hcmpeq #m0.anr!m0.ale!m0.ico!m0.pms!<5*m0.pno>!m0.ena,mmr0 ; check mmr0
@@ -1542,11 +1544,16 @@ tc0206: mov kipdr0,sipdr0 ; super page 0 1-to-1
hcmpeq (sp),#300$ ; PC: return after mov
hcmpeq 2(sp),#cp.cms!cp.pr2 ; PS: should be code signature
;
; check mmr0,mmr2 instruction complete (unless on SimH)
; check mmr0,mmr1,mmr2 instruction complete (unless on SimH)
; Note: w11 has one SP decrements in the case, 11/70 and e11 two.
cmpb systyp,#sy.sih
beq 490$
hcmpeq #m0.anr!m0.ale!m0.ico!m0.pms!<5*m0.pno>!m0.ena,mmr0 ; check mmr0
hcmpeq #^b0000000011110110,mmr1 ; check mmr1: one SP decrement
cmpb systyp,#sy.e11
bne 410$
mov #^b1111011011110110,420$+2 ; e11, as 11/70, has two SP decs
;
410$: hcmpeq #m0.anr!m0.ale!m0.ico!m0.pms!<5*m0.pno>!m0.ena,mmr0 ; check mmr0
420$: hcmpeq #^b0000000011110110,mmr1 ; check mmr1: one SP decrement
hcmpeq #v..pir,mmr2 ; check mmr2: failed vector
490$:
;
@@ -1648,7 +1655,7 @@ tc0209: clr kipdr6 ; kernel page 6 non-resident
; abort bits. The w11 also takes a vector 4 but will set MMR0 abort bits.
; Verify this w11 specific behavior.
;
tc0210: tstb systyp ; skip if not on w11
tc0210: tstb systyp ; skip if not on w11
blt 9999$
;
mov #<127.*md.plf>,kipdr6 ; page 6 non-resident (afc=0)
@@ -1749,7 +1756,7 @@ td0101:
jmp 9999$
;
; the MMU trap handler
; - saves all registers (starting with PC dummp)
; - saves all registers (starting with PC dump)
; - rolls back register changes seen in MMR1
; - increases the stack by one click
; - restore all registers
@@ -1823,8 +1830,8 @@ td0101:
; page 3 stack area, initially too short
; page 7 IO page, with RW traps enabled
;
td0201: tstb systyp ; skip if not on w11
bge 100$
td0201: cmpb systyp,#sy.sih ; skip on on SimH
bne 100$
jmp 9999$
;
; set up supervisor pdr/par
@@ -1872,9 +1879,16 @@ td0201: tstb systyp ; skip if not on w11
clr cp.psw ; PSW to default
hcmpeq #<127.*md.plf>!md.aia!md.aiw!md.att,sipdr7 ; check sipdr7
;
htaini 2000$,5. ; expect 5 items
; on w11 the PC is incremented after an instruction fetch abort while on an
; 11/70 and with e11 it is not. Set up PC seen in 2nd MMU call accordingly
mov #p2base+2,r0 ; PC after fault (for w11)
cmpb systyp,#sy.e11 ; e11 ?
bne 210$
sub #2,r0 ; PC before fault (for e11)
;
210$: htaini 2000$,5. ; expect 5 items
htacmp #250,#200$ ; mmu(ico=1) after movb to cp.pir+1
htacmp #250,#p2base+2 ; mmu(ico=1) after 1st instruction fetch
htacmp #250,r0 ; mmu(ico=1) PC differs for w11 and e11
htacmp #240,#200$ ; PIRQ, sees PC after movb to cp.pir+1
htacmp #250,#p2base+<vc3l1-vc3> ; mmu(trap) after clr of cp.pir
htacmp #032,#p2base+<vc3l2-vc3> ; EMT after emt 100
@@ -1898,7 +1912,7 @@ td0201: tstb systyp ; skip if not on w11
mov #250,(r5)+ ; trace
mov (sp),(r5)+
;
; dispatch call cases based in mmr0
; dispatch call cases based on mmr0
mov mmr0,r0
bit #m0.anr!m0.ale!m0.ard,r0 ; abort seen ?
beq 3300$ ; if not branch to trap handling
@@ -1908,6 +1922,7 @@ td0201: tstb systyp ; skip if not on w11
; handle abort with ico=1 ------------------------
; Expect length error for supervisor mode I space page 3.
; Actions:
; - determine target mode from mmr0 page mode and set is as previous mode.
; - roll-back previous mode SP.
; - extend previous mode stack segment.
; - move stack frame from from kernel to previous mode.
@@ -1920,7 +1935,14 @@ td0201: tstb systyp ; skip if not on w11
hcmpeq #m0.ale!m0.ent!m0.ico!m0.pms!<3*m0.pno>!m0.ena,r0 ; check mmr0
hcmpeq #240,mmr2 ; check mmr2: PIRQ vector
;
; use MMR1 to correct SM SP
; Use page mode from mmr0 as previous mode
; psw(13:12) is PM, mmr0(6:5) is page mode --> shift 7 bits left
mov r0,r1 ; copy mmr0
bic #^cm0.pmu,r1 ; get page mode bits
ash #7,r1 ; shift to PM bits position
bic #cp.pmu,cp.psw ; clear PM bits
bis r1,cp.psw ; set PM bits from mmr0
; use MMR1 to correct SP
mov mmr1,r1 ; get mmr1
mfpd sp ; get SM sp
pop r2
@@ -1970,9 +1992,9 @@ td0201: tstb systyp ; skip if not on w11
bis #md.arw,sipdr2 ; code page read-writable
mov mmr2,(sp) ; point to failed instruction
bic #m0.anr!m0.ale!m0.ard,mmr0 ; clear abort flags
rtt ; re-run instruction, use rtt to avoid a
; spurious tbit trap in case traced
; instruction
rtt ; re-run instruction, use rtt to avoid
; a spurious tbit trap in case of a
; traced instruction
;
; handle MMU trap --------------------------------
; Expect trap from cp.pir register access
@@ -1984,8 +2006,8 @@ td0201: tstb systyp ; skip if not on w11
rti ; continue
;
; EMT handler ----------------------------------------------
; The EMT handler simulates a system service that does a kernel mode RTI
; on behalf of the supervisor mode handler. This allows supervisor mode code
; The EMT handler simulates a system service that does a kernel mode RTI on
; behalf of the supervisor mode handler. This allows supervisor mode code
; to return to kernel mode code and bypasses the privileged escalation
; protection of RTI/RTT in a controlled manner.
; It simply moves the stack frame from previous mode to kernel mode and