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cpu_mmu: add C2.1 test
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wfjm
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@ -1,4 +1,4 @@
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; $Id: defs_mmu.mac 1280 2022-08-15 09:12:03Z mueller $
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; $Id: defs_mmu.mac 1289 2022-08-29 12:31:04Z mueller $
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; SPDX-License-Identifier: GPL-3.0-or-later
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; Copyright 2015-2022 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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;
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@ -1,4 +1,4 @@
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; $Id: cpu_mmu.mac 1283 2022-08-22 10:07:58Z mueller $
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; $Id: cpu_mmu.mac 1290 2022-08-30 06:20:40Z mueller $
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; SPDX-License-Identifier: GPL-3.0-or-later
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; Copyright 2022- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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;
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@ -11,8 +11,8 @@
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; Test CPU MMU: all aspects of the MMU
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; Section A: pdr,par registers
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; Section B: mmr0,mmr3 registers, mapping, instructions
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; Section C: mmr1 register and traps
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; Section D: mmr2 register and aborts
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; Section C: mmr1+mmr0 register, aborts and traps
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; Section D: mmr2+mmr1+mmr0 register, abort recovery
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;
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.include |lib/tcode_std_base.mac|
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.include |lib/defs_mmu.mac|
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@ -23,9 +23,18 @@
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udpar0 = udpar+ 0
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udpdr1 = udpdr+ 2
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udpar1 = udpar+ 2
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udpdr2 = udpdr+ 4
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udpar2 = udpar+ 4
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sipdr0 = sipdr+ 0
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sipar0 = sipar+ 0
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sipdr7 = sipdr+16
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sipar7 = sipar+16
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kipdr0 = kipdr+ 0
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kipdr6 = kipdr+14
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kipar6 = kipar+14
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kipdr7 = kipdr+16
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kipar7 = kipar+16
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;
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; Section A: pdr,par registers ===============================================
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@ -145,11 +154,8 @@ ta0102:
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mov #001200,(r0)+ ; kipar5 120000 base
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mov #001400,(r0)+ ; kipar6 140000 base
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mov #177600,(r0)+ ; kipar7 (map I/O page)
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; set up kernel D
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mov #kdpdr,r0
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mov r1,16(r0) ; kdpdr7 plf=127; ed=0(up); acf=6(w/r)
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mov #kdpar,r0
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mov #177600,16(r0) ; kdpar7 (map I/O page)
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; kernel D space is not used in tests, kernel always runs without I/D
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; D space is tested, but in supervisor or user mode
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;
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jmp 9999$
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;
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@ -526,12 +532,12 @@ tb0302:
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hcmpeq r5,#277 ; check
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hcmpeq r4,#377 ; check
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; read registers via mtpd,mtpi
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mov #477,r5
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mov #577,r4
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mfpd r5
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hcmpeq (sp)+,#477 ; check
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mfpd r4
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hcmpeq (sp)+,#577 ; check
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mov #477,r5
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mov #577,r4
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mfpd r5
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hcmpeq (sp)+,#477 ; check
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mfpd r4
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hcmpeq (sp)+,#577 ; check
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;
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; reset user mode pdr/par
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clr uipdr0
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@ -540,6 +546,7 @@ tb0302:
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clr udpar0
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;
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reset ; mmu off ;! MMU off
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clr cp.psw ; crop pm in psw
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mov #v..emt+2,v..emt ; restore emt catcher
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clr v..emt+2
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jmp 9999$
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@ -558,7 +565,7 @@ tb0302:
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;
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9999$: iot ; end of test B3.2
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;
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; Section C: mmr1 register and traps =========================================
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; Section C: mmr1+mmr0 register, aborts and traps ============================
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;
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; Test C1: ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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;
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@ -634,7 +641,253 @@ tc0101: mov #1000$,r1 ; ptr to abort bit table
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;
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9999$: iot ; end of test C1.1
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;
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; Section D: mmr2 register and aborts ========================================
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; Test C2: ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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; Verify MMU abort response in mmr0 and mmr1
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;
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; Test C2.1 -- test unary/binary instructions ++++++++++++++++++++++++
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; Excercise access to kernel page 6 and inspect mmr0 and mmr1
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;
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tc0201: mov #vhemmu,v..mmu
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clr v..mmu+2 ; pr0 kernel
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reset
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mov #m0.ena,mmr0 ; enable mmu ;! MMU 18
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;
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; part 1: unary instructions; test acf to mmr0(15:13) mapping --------
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; Summary:
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; 1000$: tst (r2)+ ; r ; dst anr 1 ; pdr= 0.,0,000
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; 1100$: tst (r3)+ ; r ; dst ale 1 ; pdr= 0.,0,arw
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; 1200$: tst -(r4) ; r ; dst ale 1 ; pdr=127.,1,arw
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; 1300$: clrb -(r2) ; w ; dst ard 1 ; pdr= 0.,0,aro
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; 1400$: inc (r2)+ ; m ; dst ard 1 ; pdr= 0.,0,aro
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; 1500$: tstb (r2)+ ; r ; dst anr 1 ; pdr= 0.,0,011
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; 1600$: tstb -(r2) ; r ; dst anr 1 ; pdr= 0.,0,111
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;
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; non-resident abort (only)
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1000$: clr kipdr6 ; plf= 0.;ed=0;acf=nres
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mov #1010$,vhvmmu
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mov #140000,r2
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tst (r2)+ ; will fail
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halt
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1010$: .word m0.anr!<6*m0.pno>!m0.ena ; mmr0
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; dddddrrrdddddrrr
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.word ^b0000000000010010 ; mmr1 +2,2
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;
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; length abort, up direction; length 1 click
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1100$: mov #<0.*md.plf>!md.arw,kipdr6 ; plf= 0.;ed=0;acf=w/r
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mov #1110$,vhvmmu
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mov #140102,r3
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tst (r3)+ ; will fail
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halt
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1110$: .word m0.ale!<6*m0.pno>!m0.ena ; mmr0
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; dddddrrrdddddrrr
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.word ^b0000000000010011 ; mmr1 +2,3
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;
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; length abort, down direction; length 1 click
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1200$: mov #<127.*md.plf>!md.dwn!md.arw,kipdr6 ; plf=127.;ed=1;acf=w/r
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mov #1210$,vhvmmu
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mov #157700,r4
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tst -(r4) ; will fail
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halt
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1210$: .word m0.ale!<6*m0.pno>!m0.ena ; mmr0
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; dddddrrrdddddrrr
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.word ^b0000000011110100 ; mmr1 -2,4
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;
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; write abort in mapped area (write access)
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1300$: mov #<0.*md.plf>!md.aro,kipdr6 ; plf= 0.;ed=0;acf=r
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mov #140002,r2
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tstb (r2)+ ; read ok
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mov #1310$,vhvmmu
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clrb -(r2) ; write will fail
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halt
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1310$: .word m0.ard!<6*m0.pno>!m0.ena ; mmr0
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; dddddrrrdddddrrr
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.word ^b0000000011111010 ; mmr1 -1,2
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;
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; write abort in mapped area (wmw access)
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1400$: mov #1410$,vhvmmu
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inc (r2)+ ; rmw will fail
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halt
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1410$: .word m0.ard!<6*m0.pno>!m0.ena ; mmr0
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; dddddrrrdddddrrr
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.word ^b0000000000010010 ; mmr1 +2,2
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;
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; acf=011: reserved, abort all -> handled as non-resident
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1500$: mov #^b011,kipdr6 ; plf= 0.;ed=0;acf=011
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mov #1510$,vhvmmu
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tstb (r2)+ ; will fail
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halt
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1510$: .word m0.anr!<6*m0.pno>!m0.ena ; mmr0
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; dddddrrrdddddrrr
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.word ^b0000000000001010 ; mmr1 +1,2
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;
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; acf=111: reserved, abort all -> handled as non-resident
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1600$: mov #^b111,kipdr6 ; plf= 0.;ed=0;acf=111
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mov #1610$,vhvmmu
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tstb -(r2) ; will fail
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halt
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1610$: .word m0.anr!<6*m0.pno>!m0.ena ; mmr0
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; dddddrrrdddddrrr
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.word ^b0000000011111010 ; mmr1 -1,2
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;
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; part 2: unary instructions; fail in second access ------------------
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; Summary:
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; 2000$: tst @(r2)+ ; r ; dst ale 2 ; pdr= 0.,0,arw
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; 2100$: tst @-(r2) ; r ; dst ale 2 ; pdr= 0.,0,arw
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;
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2000$: mov #<0.*md.plf>!md.arw,kipdr6 ; plf= 0.;ed=0;acf=r/w
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mov #2010$,vhvmmu
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mov #2001$,r2
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tst @(r2)+ ; will fail
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halt
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2001$: .word 140102 ; probed address
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2010$: .word m0.ale!<6*m0.pno>!m0.ena ; mmr0
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; dddddrrrdddddrrr
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.word ^b0000000000010010 ; mmr1 +2,2
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;
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2100$: mov #2110$,vhvmmu
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tst @-(r2) ; will fail
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halt
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2110$: .word m0.ale!<6*m0.pno>!m0.ena ; mmr0
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; dddddrrrdddddrrr
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.word ^b0000000011110010 ; mmr1 -2,2
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;
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; part 3: binary instructions; fail in src field ---------------------
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; Summary:
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; 3000$: mov (r2)+,(r3)+ ; r w ; src ale 1 ; pdr= 0.,0,arw
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; 3100$: mov -(r2),(r3)+ ; r w ; src ale 1 ; pdr= 0.,0,arw
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; 3200$: mov @(r4)+,(r3)+ ; r w ; src ale 2 ; pdr= 0.,0,arw
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; 3300$: mov @-(r4),(r3)+ ; r w ; src ale 2 ; pdr= 0.,0,arw
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;
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3000$: mov #<0.*md.plf>!md.arw,kipdr6 ; plf= 0.;ed=0;acf=r/w
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mov #3010$,vhvmmu
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mov #140102,r2
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mov #1,r3 ; not used
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mov (r2)+,(r3)+ ; will fail
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halt
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3010$: .word m0.ale!<6*m0.pno>!m0.ena ; mmr0
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; dddddrrrdddddrrr
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.word ^b0000000000010010 ; mmr1 +2,2
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;
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3100$: mov #3110$,vhvmmu
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mov -(r2),(r3)+ ; will fail
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halt
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3110$: .word m0.ale!<6*m0.pno>!m0.ena ; mmr0
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; dddddrrrdddddrrr
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.word ^b0000000011110010 ; mmr1 -2,2
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;
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3200$: mov #3210$,vhvmmu
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mov #3201$,r4
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mov @(r4)+,(r3)+ ; will fail
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halt
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3201$: .word 140102 ; probed address
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3210$: .word m0.ale!<6*m0.pno>!m0.ena ; mmr0
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; dddddrrrdddddrrr
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.word ^b0000000000010100 ; mmr1 +2,4
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;
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3300$: mov #3310$,vhvmmu
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movb @-(r4),(r3)+ ; will fail
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halt
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3310$: .word m0.ale!<6*m0.pno>!m0.ena ; mmr0
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; dddddrrrdddddrrr
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.word ^b0000000011110100 ; mmr1 -2,4
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;
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; part 4: binary instructions; fail in dst field ---------------------
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; Summary:
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; 4000$: mov (r2)+,-(r3) ; r w ; dst ale 1 ; pdr= 0.,0,arw
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; 4100$: mov -(r2),(r3)+ ; r w ; dst ale 1 ; pdr= 0.,0,arw
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; 4200$: cmp (r2)+,@(r5)+ ; r r ; dst ale 2 ; pdr= 0.,0,arw
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; 4300$: bis -(r2),(r4)+ ; r m ; dst ard 1 ; pdr= 0.,0,aro
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; 4400$: bis (r2),-(r4) ; r m ; dst ard 1 ; pdr= 0.,0,aro
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;
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4000$: mov #<0.*md.plf>!md.arw,kipdr6 ; plf= 0.;ed=0;acf=r/w
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mov #4010$,vhvmmu
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mov #4001$,r2
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mov #140104,r3
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mov (r2)+,-(r3) ; will fail
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halt
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4001$: .word 123456
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4010$: .word m0.ale!<6*m0.pno>!m0.ena ; mmr0
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; dddddrrrdddddrrr
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.word ^b1111001100010010 ; mmr1 -2,3; +2,2
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;
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4100$: mov #4110$,vhvmmu
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mov -(r2),(r3)+ ; will fail
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halt
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4110$: .word m0.ale!<6*m0.pno>!m0.ena ; mmr0
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; dddddrrrdddddrrr
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.word ^b0001001111110010 ; mmr1 +2,3; -2,2
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;
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4200$: mov #4210$,vhvmmu
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mov 4201$,r5
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cmp (r2)+,@(r5)+ ; will fail
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halt
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4201$: .word 140102 ; probed address
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4210$: .word m0.ale!<6*m0.pno>!m0.ena ; mmr0
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; dddddrrrdddddrrr
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.word ^b0001010100010010 ; mmr1 +2,5; +2,2
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;
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4300$: mov #<0.*md.plf>!md.aro,kipdr6 ; plf= 0.;ed=0;acf=r
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mov #4310$,vhvmmu
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mov #140010,r4
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bis -(r2),(r4)+ ; will fail
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halt
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4310$: .word m0.ard!<6*m0.pno>!m0.ena ; mmr0
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; dddddrrrdddddrrr
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.word ^b0001010011110010 ; mmr1 +2,4; -2,2
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;
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; no inc/dec for src
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4400$: mov #4410$,vhvmmu
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bis (r2),-(r4) ; will fail
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halt
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4410$: .word m0.ard!<6*m0.pno>!m0.ena ; mmr0
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; dddddrrrdddddrrr
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.word ^b0000000011110100 ; mmr1 -2,4;
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;
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; part 5: multiple abort flags ---------------------------------------
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; possible: anr + ale (non-resident + length)
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; ard + ale (read-only + length)
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; Summary:
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; 5000$: tst (r2)+ ; r ; dst anr+ale 1 ; pdr= 0.,0,000
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; 5100$: clr (r3)+ ; w ; dst anr 1 ; pdr= 0.,0,000
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; 5200$: com (r4)+ ; m ; dst ale+ard 1 ; pdr= 0.,0,aro
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;
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; non-resident + length abort
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5000$: clr kipdr6 ; plf= 0.;ed=0;acf=nres
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mov #5010$,vhvmmu
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mov #140102,r2
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tst (r2)+ ; will fail
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halt
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5010$: .word m0.anr!m0.ale!<6*m0.pno>!m0.ena ; mmr0
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; dddddrrrdddddrrr
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.word ^b0000000000010010 ; mmr1 +2,2
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;
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; non-resident abort + write --> nres only
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5100$: mov #5110$,vhvmmu
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mov #140002,r3
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clr (r3)+ ; will fail
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halt
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5110$: .word m0.anr!<6*m0.pno>!m0.ena ; mmr0
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; dddddrrrdddddrrr
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.word ^b0000000000010011 ; mmr1 +2,3
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;
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; length + read-only abort
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5200$: mov #<0.*md.plf>!md.aro,kipdr6 ; plf= 0.;ed=0;acf=r
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mov #5210$,vhvmmu
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mov #140102,r4
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com (r4)+ ; will fail
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halt
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5210$: .word m0.ale!m0.ard!<6*m0.pno>!m0.ena ; mmr0
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; dddddrrrdddddrrr
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.word ^b0000000000010100 ; mmr1 +2,4
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;
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9000$: reset ; mmu off ;! MMU off
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clr cp.psw
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mov #<127.*md.plf>!md.arw,kipdr6 ; restore kernel mapping
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mov #v..mmu+2,v..mmu ; restore mmu catcher
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clr v..mmu+2
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9999$: iot ; end of test C2.1
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;
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; Section D: mmr2+mmr1+mmr0 register, abort recovery =========================
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;
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; Test D1: ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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;
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@ -771,21 +1024,43 @@ td0101:
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; END OF ALL TESTS - loop closure ============================================
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;
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mov tstno,r0 ; hack, for easy monitoring ...
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hcmpeq tstno,#10. ; all tests done ?
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hcmpeq tstno,#11. ; all tests done ?
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;
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jmp loop
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;
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; kernel handlers ============================================================
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;
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; vhemmu - expected mmu abort/trap handler +++++++++++++++++++++++++++++++++++
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; used to catch expected MMU aborts or traps
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; the pointer to expected mmr0/mmr1 values must be in vhvmmu
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; code will continue after context
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; execution will clear vhvmmu
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; --> vhvmmu must be set for each execution
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; the handler uses and modifies r0,r1
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; --> tests should only use r2,...,r5
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;
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vhemmu: mov vhvmmu,r1 ; get context
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beq 1000$ ; if 0 halt
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mov mmr0,r0
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bic #m0.ico,r0 ; mask ico (for Simh compatibility)
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hcmpeq r0,(r1)+ ; check mmr0
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hcmpeq mmr1,(r1)+ ; check mmr1
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bic #m0.anr!m0.ale!m0.ard,mmr0 ; reset mmr0 abort flags
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mov r1,(sp) ; set up kernel return address
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clr vhvmmu ; reset context
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rti ; end return to continuation address
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1000$: halt
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vhvmmu: .word 0 ; context pointer
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;
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; vhuemt - emt handler, drop frame, continue in kernel mode ++++++++++++++++++
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; use to end user/supervisor mode code with an emt xxx
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; the kernel continution address must be written to vhustp
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; execution will reset vhustp to a catcher value
|
||||
; --> vhustp must be set for each execution
|
||||
;
|
||||
vhuemt: tst (sp)+ ; discard on word of vector push
|
||||
vhuemt: tst (sp)+ ; discard one word of vector push
|
||||
mov vhustp,(sp) ; set up kernel return address
|
||||
mov vhuhlt,vhustp ; reset stop address by catcher
|
||||
mov #vhuhlt,vhustp ; reset stop address by catcher
|
||||
rts pc ; end return to continuation address
|
||||
vhustp: .word vhuhlt
|
||||
vhuhlt: halt
|
||||
|
||||
Loading…
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Reference in New Issue
Block a user