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*.*pp,*.tcl: ssr->mmr rename

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wfjm 2022-08-10 08:04:19 +02:00
parent fc10cc5321
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13 changed files with 380 additions and 375 deletions
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2
doc/ECO-027-trap_mmu.md
View File

@ -11,7 +11,7 @@
The PDP-11/70 and 11/45 MMU offers a 'mmu trap' feature, which can cause
a trap when a memory location is read or written. This can be enabled with
special `ACF` values in the page descriptor registers for each segment end
globally enabled with an enable bit in `SSR0`.
globally enabled with an enable bit in `MMR0`.
Since only 11/70 and 11/45 offer this (and J11 does not) this feature is
in general not used by operations systems.

20
doc/README_known_issues.md
View File

@ -61,7 +61,7 @@ a minor deficit. Might be fixed in an upcoming release.
### V0.50-3 {[issue #27](https://github.com/wfjm/w11/issues/27)} -- CPU: no mmu trap when instruction which clears trap enable itself causes a trap
The MMU should issue an mmu trap if the instruction clearing the
'mmu trap enable' bit (bit 9 in ssr0) itself causes a trap.
'mmu trap enable' bit (bit 9 in mmr0) itself causes a trap.
The 11/70 documentation clearly describes this behavior.
This is the reason why test 063 of the `ekbee1` diagnostics currently fails.
@ -72,9 +72,9 @@ not in the J11, it is not used by common operating systems.
Therefore this is considered a to be a minor deficit. Will be fixed in an
upcoming release.
### V0.50-6 {[issue #26](https://github.com/wfjm/w11/issues/26)} -- CPU: SSR0 trap bit set when access aborted
### V0.50-6 {[issue #26](https://github.com/wfjm/w11/issues/26)} -- CPU: MMR0 trap bit set when access aborted
The MMU should set the 'trap bit' in `SSR0` only when the access is not
The MMU should set the 'trap bit' in `MMR0` only when the access is not
aborted. The current pdp11_mmu implementation sets the bit even when the
access is aborted.
@ -86,9 +86,9 @@ not in the J11, it is not used by common operating systems.
Therefore this is considered a to be a minor deficit. Will be fixed in an
upcoming release.
### V0.50-5 {[issue #25](https://github.com/wfjm/w11/issues/25)} -- CPU: The AIB bit in MMU SDR register set independant of ACF field
### V0.50-5 {[issue #25](https://github.com/wfjm/w11/issues/25)} -- CPU: The AIB bit in MMU PDR register set independant of ACF field
The MMU should set the AIB A bit in the the SDR only when _"trap condition is
The MMU should set the AIB A bit in the the PDR only when _"trap condition is
met by the Access Control Field (ACF)"_. Thus for
```
ACF=001 read-only trap on read
@ -109,13 +109,13 @@ in the J11, it is not used by common operating systems.
Therefore this is considered a to be a minor deficit. Will be fixed in an
upcoming release.
### V0.50-4 {[issue #24](https://github.com/wfjm/w11/issues/24)} -- CPU: src+dst deltas summed in ssr1 if register identical
### V0.50-4 {[issue #24](https://github.com/wfjm/w11/issues/24)} -- CPU: src+dst deltas summed in mmr1 if register identical
Test 12 of maindec `ekbee1` fails because it expects after a
```
mov #100000,@#ssr0
mov #100000,@#mmr0
```
which sets an error bit in `ssr0` and thus freezes `ssr0`, that `ssr1` contains
which sets an error bit in `mmr0` and thus freezes `mmr0`, that `mmr1` contains
```
013427 (00010 111 00010 111) (+2,r7;+2,r7)
```
@ -123,12 +123,12 @@ while w11a gives
```
000047 (00000 000 00100 111) (--,--;+4,r7)
```
The `ssr1` content is _different_ compared to the original 11/70 behavior,
The `mmr1` content is _different_ compared to the original 11/70 behavior,
but is _logically correct_, fault recovery in OS (like in 211bsd) will work
correctly. Therefore this is considered a to be a _minor deficit_.
The 11/70 documentation clearly states that there is an additional state bit
that counts the write accesses to `ssr1`. This ensures that each of the two
that counts the write accesses to `mmr1`. This ensures that each of the two
logged accesses end in separate bytes (byte 0 filled first).
The w11a only uses byte 1 when the register number differs.

290
rtl/w11a/tb/tb_pdp11core_stim.dat
View File

@ -1,6 +1,6 @@
# $Id: tb_pdp11core_stim.dat 1261 2022-07-23 16:15:03Z mueller $
# $Id: tb_pdp11core_stim.dat 1274 2022-08-08 09:21:53Z mueller $
# SPDX-License-Identifier: GPL-3.0-or-later
# Copyright 2007-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
# Copyright 2007-2022 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
#
# Revision History:
# Date Rev Version Comment
@ -13,10 +13,10 @@
# correct test 37.2: 2 V=1 cases have regs now updated
# 2010-06-20 308 2.2.1 add wibrb, ribr, wibr based tests
# 2010-06-13 305 2.2 adopt to new rri address and function semantics
# 2009-11-22 252 2.1.14 change SSR0 expects, adapt to ECO-021.
# 2009-11-22 252 2.1.14 change MMR0 expects, adapt to ECO-021.
# 2009-05-02 211 2.1.13 add nop after spl in pirq test, 11/70 spl now !!
# 2008-08-29 163 2.1.12 add wtlam to harvest attn after sto in test 13
# 2008-04-27 139 2.1.11 adapt expected ssr1 after mtpi/d after ECO-009 fix
# 2008-04-27 139 2.1.11 adapt expected mmr1 after mtpi/d after ECO-009 fix
# 2008-03-15 125 2.1.10 exclude some tests from simh ([[off/on]]
# 2008-03-09 124 2.1.9 fixed addr-mode in code 34, shifted 47+50
# 2008-03-02 121 2.1.8 add meory access error tests
@ -174,7 +174,7 @@ rr3 d=010301 -- ! r3 [[r13]]
rr4 d=010401 -- ! r4 [[r14]]
rr5 d=010501 -- ! r5 [[r15]]
#
C write IB space: MMU SAR supervisor mode (16 bit regs)
C write IB space: MMU PAR supervisor mode (16 bit regs)
# ==> now tested with cp/test_cp_ibrbasics.tcl
#
wal 172240 -- set first three SM I space address regs
@ -183,7 +183,7 @@ bwm 3
012342
012344
#
C read IB space: MMU SAR supervisor mode (16 bit regs)
C read IB space: MMU PAR supervisor mode (16 bit regs)
# ==> now tested with cp/test_cp_ibrbasics.tcl
#
wal 172240 -- ! verify first three SM I space address regs
@ -192,14 +192,14 @@ brm 3
d=012342
d=012344
#
C read IB space via ibr: MMU SAR supervisor mode (16 bit regs)
C read IB space via ibr: MMU PAR supervisor mode (16 bit regs)
# ==> now tested with cp/test_cp_ibrbasics.tcl
#
ribr 172240 d=012340
ribr 172242 d=012342
ribr 172244 d=012344
#
C byte write IB space via ibr: MMU SAR supervisor mode (16 bit regs)
C byte write IB space via ibr: MMU PAR supervisor mode (16 bit regs)
#
wmembe 101 -- write low byte (set sticky flag)
wibr 172240 177000
@ -1038,11 +1038,11 @@ bwm 4
000036 -- PC:36
000000 -- PS:0
#-----------------------------------------------------------------------------
C Setup code 16 [base 4000] (enable MMU, check ssr1, ssr2 response)
C Setup code 16 [base 4000] (enable MMU, check mmr1, mmr2 response)
#
wal 172516 -- SSR3
wal 172516 -- MMR3
wmi 000002 -- I/D enabled for sm only (to check CRESET)
wal 177572 -- SSR0
wal 177572 -- MMR0
wmi 000001 -- set enable bit
#
wal 004000 -- code (to be single stepped...)
@ -1063,61 +1063,61 @@ bwm 2
000001
000300
#
C Exec code 16 (enable MMU, check ssr1, ssr2 response)
C Exec code 16 (enable MMU, check mmr1, mmr2 response)
#
wr1 004040 -- r1=4040
wr2 004060 -- r2=4060
wsp 001400 -- sp=1400
wpc 004000 -- pc=4000
step -- step (mov (r1),r5)
wal 177572 -- check SSR0/1/2
wal 177572 -- check MMR0/1/2
brm 3
d=000001 -- ! SSR0: (ena=1)
d=000000 -- ! SSR1:
d=004000 -- ! SSR2: 4000 (eff. PC)
d=000001 -- ! MMR0: (ena=1)
d=000000 -- ! MMR1:
d=004000 -- ! MMR2: 4000 (eff. PC)
rr1 d=004040 -- ! r1
rr5 d=000001 -- ! r5
step -- step (mov (r1)+,r5)
wal 177572 -- check SSR0/1/2
wal 177572 -- check MMR0/1/2
brm 3
d=000001 -- ! SSR0: (ena=1)
d=000021 -- ! SSR1: rb none; ra=1,+2
d=004002 -- ! SSR2: 4002 (eff. PC)
d=000001 -- ! MMR0: (ena=1)
d=000021 -- ! MMR1: rb none; ra=1,+2
d=004002 -- ! MMR2: 4002 (eff. PC)
rr1 d=004042 -- ! r1
rr5 d=000001 -- ! r5
step -- step (mov -(r1),r5)
wal 177572 -- check SSR0/1/2
wal 177572 -- check MMR0/1/2
brm 3
d=000001 -- ! SSR0: (ena=1)
d=000361 -- ! SSR1: rb none; ra=1,-2
d=004004 -- ! SSR2: 4004 (eff. PC)
d=000001 -- ! MMR0: (ena=1)
d=000361 -- ! MMR1: rb none; ra=1,-2
d=004004 -- ! MMR2: 4004 (eff. PC)
rr1 d=004040 -- ! r1
rr5 d=000001 -- ! r5
step -- step (mov (r1)+,(r2)+)
wal 177572 -- check SSR0/1/2
wal 177572 -- check MMR0/1/2
brm 3
d=000001 -- ! SSR0: (ena=1)
d=011021 -- ! SSR1: rb=2,2; ra=1,2
d=004006 -- ! SSR2: 4006 (eff. PC)
d=000001 -- ! MMR0: (ena=1)
d=011021 -- ! MMR1: rb=2,2; ra=1,2
d=004006 -- ! MMR2: 4006 (eff. PC)
rr1 d=004042 -- ! r1
rr2 d=004062 -- ! r2
step -- step (movb (r1)+,r5)
wal 177572 -- check SSR0/1/2
wal 177572 -- check MMR0/1/2
brm 3
d=000001 -- ! SSR0: (ena=1)
d=000011 -- ! SSR1: rb=none; ra=1,1
d=004010 -- ! SSR2: 4010 (eff. PC)
d=000001 -- ! MMR0: (ena=1)
d=000011 -- ! MMR1: rb=none; ra=1,1
d=004010 -- ! MMR2: 4010 (eff. PC)
rr1 d=004043 -- ! r1
rr5 d=177700 -- ! r5
step -- step (movb #200,(r1)+)
wal 177572 -- check SSR0/1/2
wal 177572 -- check MMR0/1/2
brm 3
d=000001 -- ! SSR0: (ena=1)
d=004427 -- ! SSR1: rb=1,1; ra=7,2
d=004012 -- ! SSR2: 4012 (eff. PC)
d=000001 -- ! MMR0: (ena=1)
d=004427 -- ! MMR1: rb=1,1; ra=7,2
d=004012 -- ! MMR2: 4012 (eff. PC)
rr1 d=004044 -- ! r1
#
C Exec test 16.1 (check CRESET of PSW, SSR0, SSR3 after start)
C Exec test 16.1 (check CRESET of PSW, MMR0, MMR3 after start)
#
wps 000000 -- psw: set pri=0
cres
@ -1125,9 +1125,9 @@ stapc 004030 -- start @ 4030 (just HALT, testing console reset)
wtgo
rpc d=004032 -- ! pc=4032
rps d=000000 -- ! psw: reset by CRESET
wal 172516 -- SSR3
wal 172516 -- MMR3
rmi d=000000 -- ! cleared by CRESET
wal 177572 -- SSR0
wal 177572 -- MMR0
rmi d=000000 -- ! cleared by CRESET
#-----------------------------------------------------------------------------
C Setup code 17 [base 4100; use 41-46] (basic instruction and cc test)
@ -1367,9 +1367,9 @@ rm d=000000 -- ! CPUERR: 0
C Exec test 20.2 (non-existent memory abort)
wal 172354 -- kernel I space AR(6)
wm 177400 -- (map to 8 k below I/O page, never available in w11a)
wal 177572 -- SSR0
wal 177572 -- MMR0
wmi 000001 -- enable
wal 172516 -- SSR3
wal 172516 -- MMR3
wmi 000020 -- ena_22bit=1
#
wr5 140000 -- r5=140000
@ -1383,7 +1383,7 @@ rm d=000040 -- ! CPUERR: (nxm=1)
wm 000000 -- any write access will clear CPUERR
rm d=000000 -- ! CPUERR: 0
#
wal 177572 -- SSR0
wal 177572 -- MMR0
wmi 000000 -- disable
wal 172354 -- kernel I space AR(6)
wm 001400 -- 1400 140000 base (default 1-to-1 map)
@ -1444,7 +1444,7 @@ bwm 2
000252 -- PC:252
000000 -- PS:0
#
wal 177572 -- SSR0
wal 177572 -- MMR0
wmi 000001 -- enable
wal 172302 -- kernel I space DR segment 1 (base 20000)
wmi 077400 -- slf=127; ed=0(up); acf=0 (non-resident)
@ -1459,13 +1459,13 @@ rr1 d=020002 -- ! r1=20002 (inc done before trap (here dstw))
rr3 d=000014 -- ! r3=16 (dec done before trap)
rpc d=000252 -- ! pc=252 (trap 250 catch)
rsp d=001374 -- ! sp=1374
wal 177572 -- check SSR0/1/2
wal 177572 -- check MMR0/1/2
brm 3
d=100003 -- ! SSR0: (abo_nonres=1,seg=1,ena=1)
d=010763 -- ! SSR1: rb=1,2; ra=3,-2
d=004714 -- ! SSR2: 4714 (eff. PC)
d=100003 -- ! MMR0: (abo_nonres=1,seg=1,ena=1)
d=010763 -- ! MMR1: rb=1,2; ra=3,-2
d=004714 -- ! MMR2: 4714 (eff. PC)
#
wal 177572 -- SSR0
wal 177572 -- MMR0
wmi 000001 -- enable and clear error bits
#----------
C Exec test 20.8 (segment length violation abort)
@ -1481,13 +1481,13 @@ rr1 d=020402 -- ! r1=20402 (inc done before trap (here dstr))
rr3 d=000014 -- ! r3=16 (dec done before trap)
rpc d=000252 -- ! pc=252 (trap 250 catch)
rsp d=001374 -- ! sp=1374
wal 177572 -- check SSR0/1/2
wal 177572 -- check MMR0/1/2
brm 3
d=040003 -- ! SSR0: (abo_length=1,seg=1,ena=1)
d=010763 -- ! SSR1: rb=1,2; ra=3,-2
d=004716 -- ! SSR2: 4716 (eff. PC)
d=040003 -- ! MMR0: (abo_length=1,seg=1,ena=1)
d=010763 -- ! MMR1: rb=1,2; ra=3,-2
d=004716 -- ! MMR2: 4716 (eff. PC)
#
wal 177572 -- SSR0
wal 177572 -- MMR0
wmi 000001 -- enable and clear error bits
#----------
C Exec test 20.9 (read-only abort)
@ -1503,22 +1503,22 @@ rr1 d=020002 -- ! r1=20000 (inc done before trap (here dstm))
rr3 d=000014 -- ! r3=16 (dec done before trap)
rpc d=000252 -- ! pc=252 (trap 250 catch)
rsp d=001374 -- ! sp=1374
wal 177572 -- check SSR0/1/2
wal 177572 -- check MMR0/1/2
brm 3
d=020003 -- ! SSR0: (abo_rdonly=1,seg=1,ena=1)
d=010763 -- ! SSR1: rb=1,2; ra=3,-2
d=004720 -- ! SSR2: 4720 (eff. PC)
d=020003 -- ! MMR0: (abo_rdonly=1,seg=1,ena=1)
d=010763 -- ! MMR1: rb=1,2; ra=3,-2
d=004720 -- ! MMR2: 4720 (eff. PC)
#
# mmu back to default setup, disable
wal 172302 -- kernel I space DR segment 1 (base 20000)
wmi 077406 -- slf=127; ed=0(up); acf=6 (r/w)
wal 177572 -- SSR0
wal 177572 -- MMR0
wmi 000000 -- disable
#----------
#
# test mmu trap
#
wal 177572 -- SSR0
wal 177572 -- MMR0
wmi 001001 -- enable, trap enable
wal 172302 -- kernel I space DR segment 1 (base 20000)
wmi 077404 -- slf=127; ed=0(up); acf=4 (r/w, trap on r/w)
@ -1536,11 +1536,11 @@ rsp d=001374 -- ! sp=1374
wal 020000 -- check target area
rm d=000016 -- ! mem(20000)=16
wm 000000 -- clean tainted memory
wal 177572 -- check SSR0
wal 177572 -- check MMR0
brm 3
d=011001 -- ! SSR0: (trap_mmu=1,ena_trap=1,seg=0,ena=1)
d=010763 -- ! SSR1: rb=1,2; ra=3,-2
d=004714 -- ! SSR2: 4714 (eff. PC)
d=011001 -- ! MMR0: (trap_mmu=1,ena_trap=1,seg=0,ena=1)
d=010763 -- ! MMR1: rb=1,2; ra=3,-2
d=004714 -- ! MMR2: 4714 (eff. PC)
#----------
C Exec test 20.11 (2nd write, should not trap again)
wr1 020002 -- r1=20002
@ -1555,16 +1555,16 @@ rsp d=001400 -- ! sp=1374
wal 020002 -- check target area
rm d=000016 -- ! mem(20002)=16
wm 000000 -- clean tainted memory
wal 177572 -- check SSR0
wal 177572 -- check MMR0
brm 3
d=011003 -- ! SSR0: (trap_mmu=1,ena_trap=1,seg=1,ena=1)
d=010763 -- ! SSR1: rb=1,2; ra=3,-2
d=004714 -- ! SSR2: 4714 (eff. PC)
d=011003 -- ! MMR0: (trap_mmu=1,ena_trap=1,seg=1,ena=1)
d=010763 -- ! MMR1: rb=1,2; ra=3,-2
d=004714 -- ! MMR2: 4714 (eff. PC)
#
# mmu back to default setup, disable
wal 172302 -- kernel I space DR segment 1 (base 20000)
wmi 077406 -- slf=127; ed=0(up); acf=6 (r/w)
wal 177572 -- SSR0
wal 177572 -- MMR0
wmi 000000 -- disable
#----------
#
@ -1660,9 +1660,9 @@ wm 000000 -- clear CPUERR
C Exec test 20.17 (red stack escalation: abort kernel stack in non-mem)
wal 172354 -- kernel I space AR(6)
wm 177400 -- (map to 8 k below I/O page, never available in w11a)
wal 177572 -- SSR0
wal 177572 -- MMR0
wmi 000001 -- enable
wal 172516 -- SSR3
wal 172516 -- MMR3
wmi 000020 -- ena_22bit=1
#
wr0 123456 -- r0=123456
@ -1679,7 +1679,7 @@ wal 177766 -- check CPUERR
rm d=000044 -- ! CPUERR: (rsv=1,nxm=1)
wm 000000 -- clear CPUERR
#
wal 177572 -- SSR0
wal 177572 -- MMR0
wmi 000000 -- disable
wal 172354 -- kernel I space AR(6)
wm 001400 -- 1400 140000 base (default 1-to-1 map)
@ -1701,7 +1701,7 @@ wm 000000 -- clear CPUERR
#----------
C Exec test 20.19 (red stack escalation: abort kernel stack mmu abort;sp=020004)
#
wal 177572 -- SSR0
wal 177572 -- MMR0
wmi 000001 -- enable
wal 172302 -- kernel I space DR segment 1 (base 20000)
wmi 077400 -- slf=127; ed=0(up); acf=0 (non-resident)
@ -1724,9 +1724,9 @@ wm 000000 -- clear CPUERR
# mmu back to default setup
wal 172302 -- kernel I space DR segment 1 (base 20000)
wmi 077406 -- slf=127; ed=0(up); acf=6 (r/w)
wal 177572 -- SSR0
wal 177572 -- MMR0
wmi 000000 -- disable
wal 172516 -- SSR3
wal 172516 -- MMR3
wmi 000000 -- disable
#
#[[on]]
@ -1742,9 +1742,9 @@ wal 177640 -- user I space AR
wmi 000053 -- 53 -> maps 0 -> 5300
wal 177660 -- user D space AR
wmi 000055 -- 55 -> maps 0 -> 5500
wal 177572 -- SSR0
wal 177572 -- MMR0
wmi 000001 -- set enable bit
wal 172516 -- SSR3
wal 172516 -- MMR3
wmi 000001 -- enable D space for user mode
#
wal 004740 -- code (to be single stepped...)
@ -1828,9 +1828,9 @@ wal 177640 -- user I space AR
wmi 000053 -- 53 -> maps 0 -> 5300
wal 177660 -- user D space AR
wmi 000055 -- 55 -> maps 0 -> 5500
wal 177572 -- SSR0
wal 177572 -- MMR0
wmi 000001 -- set enable bit
wal 172516 -- SSR3
wal 172516 -- MMR3
wmi 000001 -- enable D space for user mode
#
wal 005000 -- code (kernel):
@ -1864,7 +1864,7 @@ bwm 68
005256
001001 -- bne .+2
000000 -- halt
013700 -- mov ssr0,r0
013700 -- mov mmr0,r0
177572
042700 -- bic #177741,r0 ; clear all but id+asn fields
177741
@ -1877,7 +1877,7 @@ bwm 68
000001
010025 -- mov r0,(r5)+
012025 -- mov (r0),(r5)+
013700 -- mov ssr1,r0
013700 -- mov mmr1,r0
177574
#5100
010025 -- mov r0,(r5)+
@ -1928,11 +1928,11 @@ bwm 68
042737 -- bic #004000,psw
004000
177776
013700 -- mov ssr2,r0
013700 -- mov mmr2,r0
177576
010025 -- mov r0,(r5)+
010016 -- mov r0,(sp)
042737 -- bic #160000,ssr0 ; clear abort bits
042737 -- bic #160000,mmr0 ; clear abort bits
#5240
160000
177572
@ -1993,12 +1993,12 @@ brm 9
d=000001 -- ! mem(5256) (mmu 3 - trap count)
d=177620 -- ! mem(5260) (1st trap: address fixed DR)
d=000406 -- ! mem(5262) (1st trap: new content of DR)
d=010420 -- ! mem(5264) (1st trap: ssr1: ra=0,2;rb=1,2)
d=000076 -- ! mem(5266) (1st trap: ssr2: pc)
d=010420 -- ! mem(5264) (1st trap: mmr1: ra=0,2;rb=1,2)
d=000076 -- ! mem(5266) (1st trap: mmr2: pc)
d=177600 -- ! mem(5270) (2nd trap: address fixed DR)
d=000402 -- ! mem(5272) (2nd trap: new content of DR)
d=000000 -- ! mem(5274) (2nd trap: ssr1: none)
d=000100 -- ! mem(5276) (2nd trap: ssr2: pc)
d=000000 -- ! mem(5274) (2nd trap: mmr1: none)
d=000100 -- ! mem(5276) (2nd trap: mmr2: pc)
#
wal 005574
brm 4
@ -5418,7 +5418,7 @@ wmi 077400 -- slf=127; ed=0(up); acf=0 (non resident)
C test 44.28: If PC->bad memory, PC incremented {others} / not inc'ed {35,40}
#
cres
wal 177572 -- SSR0
wal 177572 -- MMR0
wmi 000001 -- set enable bit
wr4 100000 -- r4=100000
wsp 001400 -- sp=1400
@ -5439,7 +5439,7 @@ cres -- console reset (to clear CPUERR reg)
C test 44.29/30a: If R->bad in mode 2, R inc'ed {others} / or not {4,34,44}
C test for dstw chain (mov r0,(r1)+)
#
wal 177572 -- SSR0
wal 177572 -- MMR0
wmi 000001 -- set enable bit
wr1 100000 -- r1=100000
wsp 001400 -- sp=1400
@ -5448,16 +5448,16 @@ step -- step (mov r0,(r1)+) [[s:2]]
rpc d=000252 -- ! pc=252 ; trap 250 [[s:254]]
rsp d=001374 -- ! sp=1374
rr1 d=100002 -- ! r1=100002
wal 177572 -- check SSR0/1
wal 177572 -- check MMR0/1
brm 2
d=100011 -- ! SSR0: (abo_nonres=1,seg=4,ena=1) see note [[s:100211]]
d=000021 -- ! SSR1: ra=1,2
d=100011 -- ! MMR0: (abo_nonres=1,seg=4,ena=1) see note [[s:100211]]
d=000021 -- ! MMR1: ra=1,2
cres -- console reset (to clear CPUERR reg)
#
C test 44.29/30b: If R->bad in mode 2, R inc'ed {others} / or not {4,34,44}
C test for srcr chain (mov (r1)+,r0)
#
wal 177572 -- SSR0
wal 177572 -- MMR0
wmi 000001 -- set enable bit
wr1 100000 -- r1=100000
wsp 001400 -- sp=1400
@ -5466,16 +5466,16 @@ step -- step ((mov (r1)+,r0) [[s:2]]
rpc d=000252 -- ! pc=252 ; trap 250 [[s:254]]
rsp d=001374 -- ! sp=1374
rr1 d=100002 -- ! r1=100002
wal 177572 -- check SSR0/1
wal 177572 -- check MMR0/1
brm 2
d=100011 -- ! SSR0: (abo_nonres=1,seg=4,ena=1) see note [[s:100211]]
d=000021 -- ! SSR1: ra=1,2
d=100011 -- ! MMR0: (abo_nonres=1,seg=4,ena=1) see note [[s:100211]]
d=000021 -- ! MMR1: ra=1,2
cres -- console reset (to clear CPUERR reg)
#
C test 44.29/30c: If R->bad in mode 2, R inc'ed {others} / or not {4,34,44}
C test for dstr chain (inc (r1)+)
#
wal 177572 -- SSR0
wal 177572 -- MMR0
wmi 000001 -- set enable bit
wr1 100000 -- r1=100000
wsp 001400 -- sp=1400
@ -5484,15 +5484,15 @@ step -- step (inc (r1)+) [[s:2]]
rpc d=000252 -- ! pc=252 ; trap 250 [[s:254]]
rsp d=001374 -- ! sp=1374
rr1 d=100002 -- ! r1=100002
wal 177572 -- check SSR0/1
wal 177572 -- check MMR0/1
brm 2
d=100011 -- ! SSR0: (abo_nonres=1,seg=4,ena=1) see note [[s:100211]]
d=000021 -- ! SSR1: ra=1,2
d=100011 -- ! MMR0: (abo_nonres=1,seg=4,ena=1) see note [[s:100211]]
d=000021 -- ! MMR1: ra=1,2
cres -- console reset (to clear CPUERR reg)
C test 44.29/30d: If R->bad in mode 2, R inc'ed {others} / or not {4,34,44}
C test for dsta chain (mtpd (r1)+)
#
wal 177572 -- SSR0
wal 177572 -- MMR0
wmi 000001 -- set enable bit
wr1 100000 -- r1=100000
wsp 001376 -- sp=1376
@ -5503,14 +5503,14 @@ step -- step (mtpd (r1)+) [[s:2]]
rpc d=000252 -- ! pc=252 ; trap 250 [[s:254]]
rsp d=001374 -- ! sp=1374
rr1 d=100002 -- ! r1=100002
wal 177572 -- check SSR0/1
wal 177572 -- check MMR0/1
brm 2
d=100011 -- ! SSR0: (abo_nonres=1,seg=4,ena=1) see note [[s:100211]]
d=010426 -- ! SSR1: rb=1,2; ra=6,2
d=100011 -- ! MMR0: (abo_nonres=1,seg=4,ena=1) see note [[s:100211]]
d=010426 -- ! MMR1: rb=1,2; ra=6,2
cres -- console reset (to clear CPUERR reg)
#
# simh notes:
# 1. simh first pops, than writes to destination, reversing ra,rb in SSR1
# 1. simh first pops, than writes to destination, reversing ra,rb in MMR1
#
# now reset MMU to default
#
@ -5519,7 +5519,7 @@ wmi 077406 -- slf=127; ed=0(up); acf=6 (r/w)
#
C test 44.39: cmode=10 will cause abort {70,J11}, treated as kmode {23,24}
#
wal 177572 -- SSR0
wal 177572 -- MMR0
wmi 000001 -- set enable bit
wr1 001400 -- r1=1400
wsp 001400 -- sp=1400
@ -5529,11 +5529,11 @@ step -- step (inc (r1)+) [[s:2]]
rpc d=000252 -- ! pc=252 ; trap 250; as expected for 11/70 [[s:254]]
rsp d=001374 -- ! sp=1374
rr1 d=001400 -- ! r1=1400
wal 177572 -- check SSR0/1
wal 177572 -- check MMR0/1
brm 3
d=140101 -- ! SSR0: (abo_nr=1,abo_l=1,m=10,seg=0,ena=1) [[s:140301]]
d=000000 -- ! SSR1: ra=none
d=013042 -- ! SSR2: PC of failed instruction
d=140101 -- ! MMR0: (abo_nr=1,abo_l=1,m=10,seg=0,ena=1) [[s:140301]]
d=000000 -- ! MMR1: ra=none
d=013042 -- ! MMR2: PC of failed instruction
wal 001374 -- check stack
brm 2
d=013044 -- ! PC after failed instruction [[s:013042]]
@ -5578,7 +5578,7 @@ wal 172300 -- check kernel I space DR, segment 0 and 1
brm 2
d=077404 -- !
d=077404 -- !
wal 177572 -- SSR0
wal 177572 -- MMR0
wmi 000001 -- set enable bit
wr0 123456 -- r0=123456
wr1 030000 -- r1=30000
@ -5609,54 +5609,54 @@ wm 001000 -- restore: 1000 100000 base
#
C test 44.47: MMR0<9>(mmu trap) implemented {70} or not {others}
#
wal 177572 -- SSR0
wal 177572 -- MMR0
wm 001000 -- set trap enable
rm d=001000 -- ! check; works as expected for 11/70
wm 000000 -- restore
#
C test 44.48: MMR3<2:0>(D space) implemented {44,70,J11} or not {others}
#
wal 172516 -- SSR3
wal 172516 -- MMR3
wm 000007 -- set D space bis
rm d=000007 -- ! check; works as expected for 11/70
wm 000000 -- restore
#
C test 44.49: MMR3<5:4>(UMAP, 22 bit) implemented {44,70,J11} or not {others}
#
wal 172516 -- SSR3
wal 172516 -- MMR3
wm 000060 -- set D space bits
rm d=000060 -- ! check; available, as expected for 11/70
wm 000000 -- restore
#
C test 44.50: MMR3<3>(CSM enable) implemented {44,J11} or not {others}
#
wal 172516 -- SSR3
wal 172516 -- MMR3
wm 000010 -- set D space bit
rm d=000000 -- ! check; not available, as expected for 11/70
wm 000000 -- restore
#
C test 44.51: MMR2 tracks fetches {70} or instructions only {others}
C here W11 behaves like {others}, fetches are not tracked in SSR2
C Also: instruction complete flag set in SSR0 after bpt.
C here W11 behaves like {others}, fetches are not tracked in MMR2
C Also: instruction complete flag set in MMR0 after bpt.
#
wal 177572 -- SSR0
wal 177572 -- MMR0
wmi 000001 -- set enable bit
wsp 001400 -- sp=1400
wpc 013052 -- pc=13052
step -- step (bpt)
rpc d=000016 -- ! pc=16; trap 14 see note [[s:13054]]
wal 177572 -- check SSR0/1/2
wal 177572 -- check MMR0/1/2
brm 3
d=000001 -- ! SSR0: (ena=1)
d=000000 -- ! SSR1: ra=none
d=013052 -- ! SSR2: PC of bpt
d=000001 -- ! MMR0: (ena=1)
d=000000 -- ! MMR1: ra=none
d=013052 -- ! MMR2: PC of bpt
step -- step (halt)
rpc d=000020 -- ! pc=20 (after halt)
wal 177572 -- check SSR0/1/2
wal 177572 -- check MMR0/1/2
brm 3
d=000001 -- ! SSR0: (ena=1)
d=000000 -- ! SSR1: ra=none
d=000016 -- ! SSR2: PC of halt
d=000001 -- ! MMR0: (ena=1)
d=000000 -- ! MMR1: ra=none
d=000016 -- ! MMR2: PC of halt
cres -- console reset (to clear CPUERR reg, PSW)
#
# simh notes:
@ -5757,7 +5757,7 @@ C Exec code 45 (mmr1 and instructions with implicit stack push/pop)
C test 45.1: mtpd (r1)+
#
cres
wal 177572 -- SSR0
wal 177572 -- MMR0
wmi 000001 -- set enable bit
wal 001376 -- setup stack with value for mtpd
wmi 123456 --
@ -5768,18 +5768,18 @@ step -- step (mtpd (r1)+)
rpc d=013102 -- ! pc=next
rsp d=001400 -- ! sp=1400
rr1 d=030002 -- ! r1=30002
wal 177572 -- check SSR0/1/2
wal 177572 -- check MMR0/1/2
brm 3
d=000003 -- ! SSR0: (seg=1,ena=1)
d=010426 -- ! SSR1: rb=1,2; ra=6,2
d=013100 -- ! SSR2: PC of mtpd
d=000003 -- ! MMR0: (seg=1,ena=1)
d=010426 -- ! MMR1: rb=1,2; ra=6,2
d=013100 -- ! MMR2: PC of mtpd
wal 030000 -- check target memory
rm d=123456 -- !
cres -- console reset
#
C test 45.2: mfpd (r1)+
#
wal 177572 -- SSR0
wal 177572 -- MMR0
wmi 000001 -- set enable bit
wr1 030000 -- r1=30000
wsp 001400 -- sp=1400
@ -5788,11 +5788,11 @@ step -- step (mfpd (r1)+)
rpc d=013104 -- ! pc=next
rsp d=001376 -- ! sp=1376
rr1 d=030002 -- ! r1=30002
wal 177572 -- check SSR0/1/2
wal 177572 -- check MMR0/1/2
brm 3
d=000001 -- ! SSR0: (seg=0,ena=1)
d=173021 -- ! SSR1: rb=6,-2; ra=1,2
d=013102 -- ! SSR2: PC of mtpd
d=000001 -- ! MMR0: (seg=0,ena=1)
d=173021 -- ! MMR1: rb=6,-2; ra=1,2
d=013102 -- ! MMR2: PC of mtpd
wal 001376 -- check stack
rmi d=123456 -- !
wal 030000 -- clear tainted target memory
@ -5801,7 +5801,7 @@ cres -- console reset
#
C test 45.3: jsr pc,(r1)+ and rts pc
#
wal 177572 -- SSR0
wal 177572 -- MMR0
wmi 000001 -- set enable bit
wr1 013110 -- r1=13110
wsp 001400 -- sp=1400
@ -5810,26 +5810,26 @@ step -- step (jsr pc,(r1)+)
rpc d=013110 -- ! pc=target
rsp d=001376 -- ! sp=1376
rr1 d=013112 -- ! r1=13112
wal 177572 -- check SSR0/1/2
wal 177572 -- check MMR0/1/2
brm 3
d=000001 -- ! SSR0: (seg=0,ena=1)
d=173021 -- ! SSR1: rb=6,-2; ra=1,2
d=013104 -- ! SSR2: PC of jsr
d=000001 -- ! MMR0: (seg=0,ena=1)
d=173021 -- ! MMR1: rb=6,-2; ra=1,2
d=013104 -- ! MMR2: PC of jsr
wal 001376 -- check stack
rmi d=013106 -- ! PC after jsr
step -- step (rts pc)
rpc d=013106 -- ! pc=target
rsp d=001400 -- ! sp=1400
wal 177572 -- check SSR0/1/2
wal 177572 -- check MMR0/1/2
brm 3
d=000001 -- ! SSR0: (seg=0,ena=1)
d=000026 -- ! SSR1: ra=6,2 [[s:0]]
d=013110 -- ! SSR2: PC of rts
d=000001 -- ! MMR0: (seg=0,ena=1)
d=000026 -- ! MMR1: ra=6,2 [[s:0]]
d=013110 -- ! MMR2: PC of rts
cres -- console reset
#
# simh notes:
# 1. simh reads stack and incremets sp later. In case of an MMU abort on
# stack read, simh SSR1 will be 0, while W11 shows the sp increment
# stack read, simh MMR1 will be 0, while W11 shows the sp increment
#
#-----------------------------------------------------------------------------
C Setup code 46 [base 13200] (systematic result+cc test of 1+2op instructions)

9
rtl/w11a/tb/tb_pdp11core_ubmap.dat
View File

@ -1,9 +1,10 @@
# $Id: tb_pdp11core_ubmap.dat 1191 2019-07-13 17:21:02Z mueller $
# $Id: tb_pdp11core_ubmap.dat 1274 2022-08-08 09:21:53Z mueller $
# SPDX-License-Identifier: GPL-3.0-or-later
# Copyright 2008-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
# Copyright 2008-2022 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
#
# Revision History:
# Date Rev Version Comment
# 2022-08-08 1274 1.5.1 ssr->mmr rename
# 2015-05-03 674 1.5 start/stop/suspend overhaul
# 2008-03-02 121 1.0 extracted from sys/tb/tb_s3board_pdp11core_mem70
#
@ -187,7 +188,7 @@ brm 4
#
C Test 2.2 write/read with ubmap on in MMU
#
wal 172516 -- SSR3
wal 172516 -- MMR3
wm 000040 -- set ubmap=1
wal 020000 -- Page 1
wah 000200 -- ubmap=1
@ -255,7 +256,7 @@ wr0 000000 -- 0 for looping
wr1 002100 -- a mem addr
wr2 172256 -- a ubus addr: MMU SM mode AR page 7 (is a 16bit r/w reg)
wpc 002000
sta -- 'start' does no reset (keeps SSR3.ubmap=1)
sta -- 'start' does no reset (keeps MMR3.ubmap=1)
#
wal 020200 -- Page 1
wah 000200 -- ubmap=1

7
rtl/w11a/tb/tb_rlink_tba_pdp11core_stim.dat
View File

@ -1,9 +1,10 @@
# $Id: tb_rlink_tba_pdp11core_stim.dat 1191 2019-07-13 17:21:02Z mueller $
# $Id: tb_rlink_tba_pdp11core_stim.dat 1274 2022-08-08 09:21:53Z mueller $
# SPDX-License-Identifier: GPL-3.0-or-later
# Copyright 2007-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
# Copyright 2007-2022 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
#
# Revision History:
# Date Rev Version Comment
# 2022-08-08 1274 1.5.1 ssr->mmr rename
# 2015-05-08 675 1.5 start/stop/suspend overhaul
# 2014-12-26 621 1.4 adopt wmembe,ribr,wibr testing to new 4k window
# 2014-12-20 614 1.6 now for rlink v4 iface
@ -193,7 +194,7 @@ rreg .r5 d=o"010501" -- ! r5
#
wreg .psw o"000000" -- psw=000000;
C ----------------------------------------------------------------------------
C write,read IB space: : MMU SAR supervisor mode (16 bit regs)
C write,read IB space: : MMU PAR supervisor mode (16 bit regs)
#
wreg .al o"172240" -- addr=172240; SM I addr reg
wreg .memi o"012340" -- set 012340

61
tools/src/librw11/Rw11Cpu.cpp
View File

@ -1,9 +1,10 @@
// $Id: Rw11Cpu.cpp 1175 2019-06-30 06:13:17Z mueller $
// $Id: Rw11Cpu.cpp 1274 2022-08-08 09:21:53Z mueller $
// SPDX-License-Identifier: GPL-3.0-or-later
// Copyright 2013-2019 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
// Copyright 2013-2022 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
//
// Revision History:
// Date Rev Version Comment
// 2022-08-08 1274 1.2.21 ssr->mmr rename
// 2019-06-29 1175 1.2.20 MemWriteByte(): use membe
// 2019-04-30 1143 1.2.19 add m9312 setup and HasM9312()
// 2019-04-19 1133 1.2.18 add ExecWibr(),ExecRibr(); LoadAbs(): better trace
@ -153,16 +154,16 @@ const uint16_t Rw11Cpu::kMEMSYSERR;
const uint16_t Rw11Cpu::kMEMHIADDR;
const uint16_t Rw11Cpu::kMEMLOADDR;
const uint16_t Rw11Cpu::kMMUSSR3;
const uint16_t Rw11Cpu::kMMUSSR2;
const uint16_t Rw11Cpu::kMMUSSR1;
const uint16_t Rw11Cpu::kMMUSSR0;
const uint16_t Rw11Cpu::kMMUSDRK;
const uint16_t Rw11Cpu::kMMUSARK;
const uint16_t Rw11Cpu::kMMUSDRS;
const uint16_t Rw11Cpu::kMMUSARS;
const uint16_t Rw11Cpu::kMMUSDRU;
const uint16_t Rw11Cpu::kMMUSARU;
const uint16_t Rw11Cpu::kMMUMMR3;
const uint16_t Rw11Cpu::kMMUMMR2;
const uint16_t Rw11Cpu::kMMUMMR1;
const uint16_t Rw11Cpu::kMMUMMR0;
const uint16_t Rw11Cpu::kMMUPDRK;
const uint16_t Rw11Cpu::kMMUPARK;
const uint16_t Rw11Cpu::kMMUPDRS;
const uint16_t Rw11Cpu::kMMUPARS;
const uint16_t Rw11Cpu::kMMUPDRU;
const uint16_t Rw11Cpu::kMMUPARU;
const uint16_t Rw11Cpu::kSCBASE;
const uint16_t Rw11Cpu::kSCCNTL;
@ -1020,28 +1021,28 @@ void Rw11Cpu::SetupStd()
AllIAddrMapInsert("hiaddr" , kMEMHIADDR);
AllIAddrMapInsert("loaddr" , kMEMLOADDR);
AllIAddrMapInsert("ssr3" , kMMUSSR3);
AllIAddrMapInsert("ssr2" , kMMUSSR2);
AllIAddrMapInsert("ssr1" , kMMUSSR1);
AllIAddrMapInsert("ssr0" , kMMUSSR0);
AllIAddrMapInsert("mmr3" , kMMUMMR3);
AllIAddrMapInsert("mmr2" , kMMUMMR2);
AllIAddrMapInsert("mmr1" , kMMUMMR1);
AllIAddrMapInsert("mmr0" , kMMUMMR0);
// add mmu segment register files
string sdr = "sdr";
string sar = "sar";
string pdr = "pdr";
string par = "par";
for (char i=0; i<8; i++) {
char ichar = '0'+i;
AllIAddrMapInsert(sdr+"ki."+ichar, kMMUSDRK+000+2*i);
AllIAddrMapInsert(sdr+"kd."+ichar, kMMUSDRK+020+2*i);
AllIAddrMapInsert(sar+"ki."+ichar, kMMUSARK+000+2*i);
AllIAddrMapInsert(sar+"kd."+ichar, kMMUSARK+020+2*i);
AllIAddrMapInsert(sdr+"si."+ichar, kMMUSDRS+000+2*i);
AllIAddrMapInsert(sdr+"sd."+ichar, kMMUSDRS+020+2*i);
AllIAddrMapInsert(sar+"si."+ichar, kMMUSARS+000+2*i);
AllIAddrMapInsert(sar+"sd."+ichar, kMMUSARS+020+2*i);
AllIAddrMapInsert(sdr+"ui."+ichar, kMMUSDRU+000+2*i);
AllIAddrMapInsert(sdr+"ud."+ichar, kMMUSDRU+020+2*i);
AllIAddrMapInsert(sar+"ui."+ichar, kMMUSARU+000+2*i);
AllIAddrMapInsert(sar+"ud."+ichar, kMMUSARU+020+2*i);
AllIAddrMapInsert(pdr+"ki."+ichar, kMMUPDRK+000+2*i);
AllIAddrMapInsert(pdr+"kd."+ichar, kMMUPDRK+020+2*i);
AllIAddrMapInsert(par+"ki."+ichar, kMMUPARK+000+2*i);
AllIAddrMapInsert(par+"kd."+ichar, kMMUPARK+020+2*i);
AllIAddrMapInsert(pdr+"si."+ichar, kMMUPDRS+000+2*i);
AllIAddrMapInsert(pdr+"sd."+ichar, kMMUPDRS+020+2*i);
AllIAddrMapInsert(par+"si."+ichar, kMMUPARS+000+2*i);
AllIAddrMapInsert(par+"sd."+ichar, kMMUPARS+020+2*i);
AllIAddrMapInsert(pdr+"ui."+ichar, kMMUPDRU+000+2*i);
AllIAddrMapInsert(pdr+"ud."+ichar, kMMUPDRU+020+2*i);
AllIAddrMapInsert(par+"ui."+ichar, kMMUPARU+000+2*i);
AllIAddrMapInsert(par+"ud."+ichar, kMMUPARU+020+2*i);
}
return;

25
tools/src/librw11/Rw11Cpu.hpp
View File

@ -1,9 +1,10 @@
// $Id: Rw11Cpu.hpp 1186 2019-07-12 17:49:59Z mueller $
// $Id: Rw11Cpu.hpp 1274 2022-08-08 09:21:53Z mueller $
// SPDX-License-Identifier: GPL-3.0-or-later
// Copyright 2013-2019 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
// Copyright 2013-2022 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
//
// Revision History:
// Date Rev Version Comment
// 2022-08-08 1274 1.2.21 ssr->mmr rename
// 2019-06-07 1160 1.2.20 Stats() not longer const
// 2019-04-30 1143 1.2.19 add HasM9312()
// 2019-04-19 1133 1.2.18 add ExecWibr(),ExecRibr()
@ -255,17 +256,17 @@ namespace Retro {
static const uint16_t kMEMHIADDR = 0177742; //!< MEM HIADDR address
static const uint16_t kMEMLOADDR = 0177740; //!< MEM LOADDR address
static const uint16_t kMMUSSR3 = 0172516; //!< MMU SSR3 address
static const uint16_t kMMUSSR2 = 0177576; //!< MMU SSR2 address
static const uint16_t kMMUSSR1 = 0177574; //!< MMU SSR1 address
static const uint16_t kMMUSSR0 = 0177572; //!< MMU SSR0 address
static const uint16_t kMMUMMR3 = 0172516; //!< MMU MMR3 address
static const uint16_t kMMUMMR2 = 0177576; //!< MMU MMR2 address
static const uint16_t kMMUMMR1 = 0177574; //!< MMU MMR1 address
static const uint16_t kMMUMMR0 = 0177572; //!< MMU MMR0 address
static const uint16_t kMMUSDRK = 0172300; //!< MMU SDRK address
static const uint16_t kMMUSARK = 0172340; //!< MMU SARK address
static const uint16_t kMMUSDRS = 0172200; //!< MMU SDRS address
static const uint16_t kMMUSARS = 0172240; //!< MMU SARS address
static const uint16_t kMMUSDRU = 0177600; //!< MMU SDRU address
static const uint16_t kMMUSARU = 0177640; //!< MMU SARU address
static const uint16_t kMMUPDRK = 0172300; //!< MMU PDRK address
static const uint16_t kMMUPARK = 0172340; //!< MMU PARK address
static const uint16_t kMMUPDRS = 0172200; //!< MMU PDRS address
static const uint16_t kMMUPARS = 0172240; //!< MMU PARS address
static const uint16_t kMMUPDRU = 0177600; //!< MMU PDRU address
static const uint16_t kMMUPARU = 0177640; //!< MMU PARU address
// defs for optional w11 cpu components
static const uint16_t kSCBASE = 0x0040; //!< DMSCNT reg base offset

99
tools/tbench/cp/test_cp_ibrbasics.tcl
View File

@ -1,102 +1,103 @@
# $Id: test_cp_ibrbasics.tcl 1178 2019-06-30 12:39:40Z mueller $
# $Id: test_cp_ibrbasics.tcl 1274 2022-08-08 09:21:53Z mueller $
# SPDX-License-Identifier: GPL-3.0-or-later
# Copyright 2014-2019 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
# Copyright 2014-2022 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
#
# Revision History:
# Date Rev Version Comment
# 2022-08-08 1274 1.1.2 ssr->mmr rename
# 2019-03-01 1116 1.1.1 use imap addresses for test area
# 2014-12-26 621 1.1 test membe
# 2014-03-02 552 1.0 Initial version
#
# Test ibus window gymnastics
# 1. write/read IB space via bwm/brm (use MMU SAR SM I regs)
# 2. write/read IB space via wibr/ribr (use MMU SAR SM I regs)
# 1. write/read IB space via bwm/brm (use MMU PAR SM I regs)
# 2. write/read IB space via wibr/ribr (use MMU PAR SM I regs)
# 3. test membe (byte write) via wibr/ribr
#
# ----------------------------------------------------------------------------
rlc log "test_cp_ibrbasics: Test very basic ibus interface gymnastics --------"
set sarsi0 [$cpu imap sarsi.0]
set sarsi1 [$cpu imap sarsi.1]
set sarsi2 [$cpu imap sarsi.2]
set parsi0 [$cpu imap parsi.0]
set parsi1 [$cpu imap parsi.1]
set parsi2 [$cpu imap parsi.2]
rlc log " write/read ibus space (MMU SAR SM I regs) via bwm/brm"
$cpu cp -wal $sarsi0 \
rlc log " write/read ibus space (MMU PAR SM I regs) via bwm/brm"
$cpu cp -wal $parsi0 \
-bwm {012340 012342 012344}
$cpu cp -wal $sarsi0 \
$cpu cp -wal $parsi0 \
-brm 3 -edata {012340 012342 012344}
rlc log " write/read ibus space (MMU SAR SM I regs) via wibr/ribr"
$cpu cp -ribr $sarsi0 -edata 012340 \
-ribr $sarsi1 -edata 012342 \
-ribr $sarsi2 -edata 012344
$cpu cp -wibr $sarsi0 022340 \
-wibr $sarsi1 022342 \
-wibr $sarsi2 022344
$cpu cp -ribr $sarsi0 -edata 022340 \
-ribr $sarsi1 -edata 022342 \
-ribr $sarsi2 -edata 022344
rlc log " write/read ibus space (MMU PAR SM I regs) via wibr/ribr"
$cpu cp -ribr $parsi0 -edata 012340 \
-ribr $parsi1 -edata 012342 \
-ribr $parsi2 -edata 012344
$cpu cp -wibr $parsi0 022340 \
-wibr $parsi1 022342 \
-wibr $parsi2 022344
$cpu cp -ribr $parsi0 -edata 022340 \
-ribr $parsi1 -edata 022342 \
-ribr $parsi2 -edata 022344
rlc log " membe with wibr (non sticky)"
$cpu cp -wibr $sarsi0 0x0100 \
-wibr $sarsi1 0x0302 \
-wibr $sarsi2 0x0504
$cpu cp -wibr $parsi0 0x0100 \
-wibr $parsi1 0x0302 \
-wibr $parsi2 0x0504
rlc log " membe = 0 (no byte selected)"
$cpu cp -wmembe 0 \
-wibr $sarsi1 0xffff \
-wibr $parsi1 0xffff \
-rmembe -edata 0x03 \
-ribr $sarsi1 -edata 0x0302
-ribr $parsi1 -edata 0x0302
rlc log " membe = 1 (lsb selected)"
$cpu cp -wmembe 0x01 \
-wibr $sarsi1 0xffaa \
-wibr $parsi1 0xffaa \
-rmembe -edata 0x03 \
-ribr $sarsi1 -edata 0x03aa
-ribr $parsi1 -edata 0x03aa
rlc log " membe = 2 (msb selected)"
$cpu cp -wmembe 0x02 \
-wibr $sarsi1 0xbbff \
-wibr $parsi1 0xbbff \
-rmembe -edata 0x03 \
-ribr $sarsi1 -edata 0xbbaa
-ribr $parsi1 -edata 0xbbaa
$cpu cp -ribr $sarsi0 -edata 0x0100 \
-ribr $sarsi1 -edata 0xbbaa \
-ribr $sarsi2 -edata 0x0504
$cpu cp -ribr $parsi0 -edata 0x0100 \
-ribr $parsi1 -edata 0xbbaa \
-ribr $parsi2 -edata 0x0504
rlc log " membe with wibr (sticky)"
$cpu cp -wibr $sarsi0 0x1110 \
-wibr $sarsi1 0x1312 \
-wibr $sarsi2 0x1514
$cpu cp -wibr $parsi0 0x1110 \
-wibr $parsi1 0x1312 \
-wibr $parsi2 0x1514
rlc log " membe = 0 + stick (no byte selected)"
$cpu cp -wmembe 0 -stick \
-wibr $sarsi1 0xffff \
-wibr $parsi1 0xffff \
-rmembe -edata 0x04 \
-ribr $sarsi1 -edata 0x1312
-ribr $parsi1 -edata 0x1312
rlc log " membe = 1 + stick (lsb selected)"
$cpu cp -wmembe 1 -stick \
-wibr $sarsi0 0xffaa \
-wibr $parsi0 0xffaa \
-rmembe -edata 0x05 \
-wibr $sarsi1 0xffbb \
-wibr $parsi1 0xffbb \
-rmembe -edata 0x05 \
-wibr $sarsi2 0xffcc \
-wibr $parsi2 0xffcc \
-rmembe -edata 0x05
$cpu cp -ribr $sarsi0 -edata 0x11aa \
-ribr $sarsi1 -edata 0x13bb \
-ribr $sarsi2 -edata 0x15cc
$cpu cp -ribr $parsi0 -edata 0x11aa \
-ribr $parsi1 -edata 0x13bb \
-ribr $parsi2 -edata 0x15cc
rlc log " membe = 2 + stick (msb selected)"
$cpu cp -wmembe 2 -stick \
-wibr $sarsi0 0xccff \
-wibr $parsi0 0xccff \
-rmembe -edata 0x06 \
-wibr $sarsi1 0xbbff \
-wibr $parsi1 0xbbff \
-rmembe -edata 0x06 \
-wibr $sarsi2 0xaaff \
-wibr $parsi2 0xaaff \
-rmembe -edata 0x06
$cpu cp -ribr $sarsi0 -edata 0xccaa \
-ribr $sarsi1 -edata 0xbbbb \
-ribr $sarsi2 -edata 0xaacc
$cpu cp -ribr $parsi0 -edata 0xccaa \
-ribr $parsi1 -edata 0xbbbb \
-ribr $parsi2 -edata 0xaacc
rlc log " membe = 3 again"
$cpu cp -wmembe 3 \
-rmembe -edata 0x03

161
tools/tbench/w11a_ibmon/test_ibmon_cpu.tcl
View File

@ -1,15 +1,16 @@
# $Id: test_ibmon_cpu.tcl 1178 2019-06-30 12:39:40Z mueller $
# $Id: test_ibmon_cpu.tcl 1274 2022-08-08 09:21:53Z mueller $
# SPDX-License-Identifier: GPL-3.0-or-later
# Copyright 2019- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
# Copyright 2019-2022 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
#
# Revision History:
# Date Rev Version Comment
# 2022-08-08 1274 1.0.1 ssr->mmr rename
# 2019-03-05 1118 1.0 Initial version
# 2019-02-24 1115 0.1 First draft
#
# Test register response
# 1. write/read IB space via bwm/brm (use MMU SAR SM I regs)
# 2. write/read IB space via wibr/ribr (use MMU SAR SM I regs)
# 1. write/read IB space via bwm/brm (use MMU PAR SM I regs)
# 2. write/read IB space via wibr/ribr (use MMU PAR SM I regs)
# 3. test membe (byte write) via wibr/ribr
# ----------------------------------------------------------------------------
@ -30,18 +31,18 @@ rlc log " A1: capture write/read rem and loc -----------------"
set cntlstastd [regbld ibd_ibmon::CNTL conena remena locena {func "STA"}]
set cntlsto [regbld ibd_ibmon::CNTL {func "STO"}]
set statmsk [regbld ibd_ibmon::STAT wrap susp run]
set sarsi0 [$cpu imap sarsi.0]
set sarsi1 [$cpu imap sarsi.1]
set sarsi2 [$cpu imap sarsi.2]
set parsi0 [$cpu imap parsi.0]
set parsi1 [$cpu imap parsi.1]
set parsi2 [$cpu imap parsi.2]
$cpu cp \
-wreg im.hilim 0177776 \
-wreg im.lolim 0160000 \
-wreg im.cntl $cntlstastd \
-rreg im.stat -edata [regbld ibd_ibmon::STAT run] $statmsk \
-wibr sarsi.0 0xdead \
-ribr sarsi.0 -edata 0xdead \
-wal $sarsi0 \
-wibr parsi.0 0xdead \
-ribr parsi.0 -edata 0xdead \
-wal $parsi0 \
-wm 0xbeef \
-rm -edata 0xbeef \
-wreg im.cntl $cntlsto \
@ -52,10 +53,10 @@ if {$print} {puts [ibd_ibmon::print $cpu]}
# build expect list: list of {eflag eaddr edata enbusy} sublists
ibd_ibmon::raw_edata edat emsk \
[list [regbld ibd_ibmon::FLAGS ack ca ra be1 be0 we] $sarsi0 0xdead 0] \
[list [regbld ibd_ibmon::FLAGS ack ca ra be1 be0 ] $sarsi0 0xdead 0] \
[list [regbld ibd_ibmon::FLAGS ack ca be1 be0 we] $sarsi0 0xbeef 0] \
[list [regbld ibd_ibmon::FLAGS ack ca be1 be0 ] $sarsi0 0xbeef 0]
[list [regbld ibd_ibmon::FLAGS ack ca ra be1 be0 we] $parsi0 0xdead 0] \
[list [regbld ibd_ibmon::FLAGS ack ca ra be1 be0 ] $parsi0 0xdead 0] \
[list [regbld ibd_ibmon::FLAGS ack ca be1 be0 we] $parsi0 0xbeef 0] \
[list [regbld ibd_ibmon::FLAGS ack ca be1 be0 ] $parsi0 0xbeef 0]
rlc log " A1.1: read all in one rblk -------------------------"
$cpu cp \
@ -87,23 +88,23 @@ rlc log " B test rreg,wreg capture: ack,we,be* flags ----------------"
rlc log " B1.1: test byte racc access (via wibr/ribr) --------"
# word write/read already tested in section A; now go for byte writes
ibd_ibmon::raw_edata edat emsk \
[list [regbld ibd_ibmon::FLAGS ack ca ra be0 we] $sarsi0 0x00aa 0] \
[list [regbld ibd_ibmon::FLAGS ack ca ra be1 be0 ] $sarsi0 0xbeaa 0] \
[list [regbld ibd_ibmon::FLAGS ack ca ra be1 we] $sarsi0 0x5500 0] \
[list [regbld ibd_ibmon::FLAGS ack ca ra be1 be0 ] $sarsi0 0x55aa 0] \
[list [regbld ibd_ibmon::FLAGS ack ca ra we] $sarsi0 0xfade 0] \
[list [regbld ibd_ibmon::FLAGS ack ca ra be1 be0 ] $sarsi0 0x55aa 0]
[list [regbld ibd_ibmon::FLAGS ack ca ra be0 we] $parsi0 0x00aa 0] \
[list [regbld ibd_ibmon::FLAGS ack ca ra be1 be0 ] $parsi0 0xbeaa 0] \
[list [regbld ibd_ibmon::FLAGS ack ca ra be1 we] $parsi0 0x5500 0] \
[list [regbld ibd_ibmon::FLAGS ack ca ra be1 be0 ] $parsi0 0x55aa 0] \
[list [regbld ibd_ibmon::FLAGS ack ca ra we] $parsi0 0xfade 0] \
[list [regbld ibd_ibmon::FLAGS ack ca ra be1 be0 ] $parsi0 0x55aa 0]
ibd_ibmon::start $cpu
$cpu cp \
-wmembe 1 \
-wibr sarsi.0 0x00aa \
-ribr sarsi.0 -edata 0xbeaa \
-wibr parsi.0 0x00aa \
-ribr parsi.0 -edata 0xbeaa \
-wmembe 2 \
-wibr sarsi.0 0x5500 \
-ribr sarsi.0 -edata 0x55aa \
-wibr parsi.0 0x5500 \
-ribr parsi.0 -edata 0x55aa \
-wmembe 0 \
-wibr sarsi.0 0xfade \
-ribr sarsi.0 -edata 0x55aa
-wibr parsi.0 0xfade \
-ribr parsi.0 -edata 0x55aa
ibd_ibmon::stop $cpu
if {$print} {puts [ibd_ibmon::print $cpu]}
@ -111,15 +112,15 @@ ibd_ibmon::raw_check $cpu $edat $emsk
rlc log " B1.2: test byte cacc access (via wm/rm) ------------"
ibd_ibmon::raw_edata edat emsk \
[list [regbld ibd_ibmon::FLAGS ack ca be0 we] $sarsi0 0xff34 0] \
[list [regbld ibd_ibmon::FLAGS ack ca be1 be0 ] $sarsi0 0x5534 0] \
[list [regbld ibd_ibmon::FLAGS ack ca be1 we] $sarsi0 0x12ff 0] \
[list [regbld ibd_ibmon::FLAGS ack ca be1 be0 ] $sarsi0 0x1234 0] \
[list [regbld ibd_ibmon::FLAGS ack ca we] $sarsi0 0xfade 0] \
[list [regbld ibd_ibmon::FLAGS ack ca be1 be0 ] $sarsi0 0x1234 0]
[list [regbld ibd_ibmon::FLAGS ack ca be0 we] $parsi0 0xff34 0] \
[list [regbld ibd_ibmon::FLAGS ack ca be1 be0 ] $parsi0 0x5534 0] \
[list [regbld ibd_ibmon::FLAGS ack ca be1 we] $parsi0 0x12ff 0] \
[list [regbld ibd_ibmon::FLAGS ack ca be1 be0 ] $parsi0 0x1234 0] \
[list [regbld ibd_ibmon::FLAGS ack ca we] $parsi0 0xfade 0] \
[list [regbld ibd_ibmon::FLAGS ack ca be1 be0 ] $parsi0 0x1234 0]
ibd_ibmon::start $cpu
$cpu cp \
-wal $sarsi0 \
-wal $parsi0 \
-wmembe 1 \
-wm 0xff34 \
-rm -edata 0x5534 \
@ -137,16 +138,16 @@ ibd_ibmon::raw_check $cpu $edat $emsk
rlc log " B1.3: test loc access (via cpu code) --------------"
# check that burst flag is seen for write of rmw
ibd_ibmon::raw_edata edat emsk \
[list [regbld ibd_ibmon::FLAGS ack be1 be0 we] $sarsi0 0xffff 0] \
[list [regbld ibd_ibmon::FLAGS ack rmw be1 be0 ] $sarsi0 0xffff 0] \
[list [regbld ibd_ibmon::FLAGS bu ack rmw be1 be0 we] $sarsi0 0x0000 0] \
[list [regbld ibd_ibmon::FLAGS ack be1 be0 ] $sarsi0 0x0000 0] \
[list [regbld ibd_ibmon::FLAGS ack rmw be0 ] $sarsi0 0x0000 0] \
[list [regbld ibd_ibmon::FLAGS bu ack rmw be0 we] $sarsi0 0xffff 0] \
[list [regbld ibd_ibmon::FLAGS ack be1 be0 ] $sarsi0 0x00ff 0] \
[list [regbld ibd_ibmon::FLAGS ack rmw be1 ] $sarsi0 0x00ff 0] \
[list [regbld ibd_ibmon::FLAGS bu ack rmw be1 we] $sarsi0 0x0101 0] \
[list [regbld ibd_ibmon::FLAGS ack be1 be0 ] $sarsi0 0x01ff 0]
[list [regbld ibd_ibmon::FLAGS ack be1 be0 we] $parsi0 0xffff 0] \
[list [regbld ibd_ibmon::FLAGS ack rmw be1 be0 ] $parsi0 0xffff 0] \
[list [regbld ibd_ibmon::FLAGS bu ack rmw be1 be0 we] $parsi0 0x0000 0] \
[list [regbld ibd_ibmon::FLAGS ack be1 be0 ] $parsi0 0x0000 0] \
[list [regbld ibd_ibmon::FLAGS ack rmw be0 ] $parsi0 0x0000 0] \
[list [regbld ibd_ibmon::FLAGS bu ack rmw be0 we] $parsi0 0xffff 0] \
[list [regbld ibd_ibmon::FLAGS ack be1 be0 ] $parsi0 0x00ff 0] \
[list [regbld ibd_ibmon::FLAGS ack rmw be1 ] $parsi0 0x00ff 0] \
[list [regbld ibd_ibmon::FLAGS bu ack rmw be1 we] $parsi0 0x0101 0] \
[list [regbld ibd_ibmon::FLAGS ack be1 be0 ] $parsi0 0x01ff 0]
$cpu ldasm -lst lst -sym sym {
. = 1000
@ -163,7 +164,7 @@ stop:
}
ibd_ibmon::start $cpu
rw11::asmrun $cpu sym r0 $sarsi0
rw11::asmrun $cpu sym r0 $parsi0
rw11::asmwait $cpu sym
rw11::asmtreg $cpu r1 0x0000 \
r2 0x00ff \
@ -184,26 +185,26 @@ stop:
rlc log " C1.1: test conena ----------------------------------"
# note that ibr access set cacc and racc flags
ibd_ibmon::raw_edata edat emsk \
[list [regbld ibd_ibmon::FLAGS ack ca ra be1 be0 we] $sarsi0 0x0100 0] \
[list [regbld ibd_ibmon::FLAGS ack ca be1 be0 we] $sarsi1 0x0101 0] \
[list [regbld ibd_ibmon::FLAGS ack ca ra be1 be0 ] $sarsi0 0x0100 0] \
[list [regbld ibd_ibmon::FLAGS ack ca be1 be0 ] $sarsi1 0x0101 0] \
[list [regbld ibd_ibmon::FLAGS ack ca ra be1 be0 ] $sarsi2 0x0102 0]
[list [regbld ibd_ibmon::FLAGS ack ca ra be1 be0 we] $parsi0 0x0100 0] \
[list [regbld ibd_ibmon::FLAGS ack ca be1 be0 we] $parsi1 0x0101 0] \
[list [regbld ibd_ibmon::FLAGS ack ca ra be1 be0 ] $parsi0 0x0100 0] \
[list [regbld ibd_ibmon::FLAGS ack ca be1 be0 ] $parsi1 0x0101 0] \
[list [regbld ibd_ibmon::FLAGS ack ca ra be1 be0 ] $parsi2 0x0102 0]
ibd_ibmon::start $cpu conena 1 remena 0 locena 0
$cpu cp \
-wibr sarsi.0 0x0100 \
-wal $sarsi1 \
-wibr parsi.0 0x0100 \
-wal $parsi1 \
-wm 0x0101 \
-wr0 $sarsi2 \
-wr0 $parsi2 \
-wr1 0x0102 \
-wpc $sym(start) \
-step \
-rpc -edata $sym(stop) \
-ribr sarsi.0 -edata 0x0100 \
-wal $sarsi1 \
-ribr parsi.0 -edata 0x0100 \
-wal $parsi1 \
-rm -edata 0x0101 \
-ribr sarsi.2 -edata 0x0102
-ribr parsi.2 -edata 0x0102
ibd_ibmon::stop $cpu
if {$print} {puts [ibd_ibmon::print $cpu]}
ibd_ibmon::raw_check $cpu $edat $emsk
@ -211,21 +212,21 @@ ibd_ibmon::raw_check $cpu $edat $emsk
rlc log " C1.2: test remena ----------------------------------"
# Note: use -wal and -wr0 setup above, skip -rpc also
ibd_ibmon::raw_edata edat emsk \
[list [regbld ibd_ibmon::FLAGS ack ca ra be1 be0 we] $sarsi0 0x0200 0] \
[list [regbld ibd_ibmon::FLAGS ack ca ra be1 be0 ] $sarsi0 0x0200 0] \
[list [regbld ibd_ibmon::FLAGS ack ca ra be1 be0 ] $sarsi2 0x0202 0]
[list [regbld ibd_ibmon::FLAGS ack ca ra be1 be0 we] $parsi0 0x0200 0] \
[list [regbld ibd_ibmon::FLAGS ack ca ra be1 be0 ] $parsi0 0x0200 0] \
[list [regbld ibd_ibmon::FLAGS ack ca ra be1 be0 ] $parsi2 0x0202 0]
ibd_ibmon::start $cpu conena 0 remena 1 locena 0
$cpu cp \
-wibr sarsi.0 0x0200 \
-wibr parsi.0 0x0200 \
-wm 0x0201 \
-wr1 0x0202 \
-wpc $sym(start) \
-step \
-ribr sarsi.0 -edata 0x0200 \
-wal $sarsi1 \
-ribr parsi.0 -edata 0x0200 \
-wal $parsi1 \
-rm -edata 0x0201 \
-ribr sarsi.2 -edata 0x0202
-ribr parsi.2 -edata 0x0202
ibd_ibmon::stop $cpu
if {$print} {puts [ibd_ibmon::print $cpu]}
ibd_ibmon::raw_check $cpu $edat $emsk
@ -233,42 +234,42 @@ ibd_ibmon::raw_check $cpu $edat $emsk
rlc log " C1.3: test locena ----------------------------------"
# Note: again reuse -wal and -wr0 setup above, skip -rpc also
ibd_ibmon::raw_edata edat emsk \
[list [regbld ibd_ibmon::FLAGS ack be1 be0 we] $sarsi2 0x0302 0] \
[list [regbld ibd_ibmon::FLAGS ack be1 be0 we] $parsi2 0x0302 0] \
ibd_ibmon::start $cpu conena 0 remena 0 locena 1
$cpu cp \
-wibr sarsi.0 0x0300 \
-wibr parsi.0 0x0300 \
-wm 0x0301 \
-wr1 0x0302 \
-wpc $sym(start) \
-step \
-ribr sarsi.0 -edata 0x0300 \
-wal $sarsi1 \
-ribr parsi.0 -edata 0x0300 \
-wal $parsi1 \
-rm -edata 0x0301 \
-ribr sarsi.2 -edata 0x0302
-ribr parsi.2 -edata 0x0302
ibd_ibmon::stop $cpu
if {$print} {puts [ibd_ibmon::print $cpu]}
ibd_ibmon::raw_check $cpu $edat $emsk
# -- Section D ---------------------------------------------------------------
rlc log " D test hilim,lolim ----------------------------------------"
# allow sarsi0,sarsi1, block sarsi2
# allow parsi0,parsi1, block parsi2
ibd_ibmon::raw_edata edat emsk \
[list [regbld ibd_ibmon::FLAGS ack ca ra be1 be0 we] $sarsi0 0x1100 0] \
[list [regbld ibd_ibmon::FLAGS ack ca ra be1 be0 we] $sarsi1 0x1101 0] \
[list [regbld ibd_ibmon::FLAGS ack ca ra be1 be0 ] $sarsi0 0x1100 0] \
[list [regbld ibd_ibmon::FLAGS ack ca ra be1 be0 ] $sarsi1 0x1101 0]
[list [regbld ibd_ibmon::FLAGS ack ca ra be1 be0 we] $parsi0 0x1100 0] \
[list [regbld ibd_ibmon::FLAGS ack ca ra be1 be0 we] $parsi1 0x1101 0] \
[list [regbld ibd_ibmon::FLAGS ack ca ra be1 be0 ] $parsi0 0x1100 0] \
[list [regbld ibd_ibmon::FLAGS ack ca ra be1 be0 ] $parsi1 0x1101 0]
ibd_ibmon::start $cpu
$cpu cp \
-wreg im.hilim $sarsi1 \
-wreg im.lolim $sarsi0 \
-wibr sarsi.0 0x1100 \
-wibr sarsi.1 0x1101 \
-wibr sarsi.2 0x1102 \
-ribr sarsi.0 -edata 0x1100 \
-ribr sarsi.1 -edata 0x1101 \
-ribr sarsi.2 -edata 0x1102 \
-wreg im.hilim $parsi1 \
-wreg im.lolim $parsi0 \
-wibr parsi.0 0x1100 \
-wibr parsi.1 0x1101 \
-wibr parsi.2 0x1102 \
-ribr parsi.0 -edata 0x1100 \
-ribr parsi.1 -edata 0x1101 \
-ribr parsi.2 -edata 0x1102 \
-wreg im.hilim 0177777 \
-wreg im.lolim 0160000

8
tools/tbench/w11a_ibmon/test_ibmon_ibtst.tcl
View File

@ -1,16 +1,12 @@
# $Id: test_ibmon_ibtst.tcl 1178 2019-06-30 12:39:40Z mueller $
# $Id: test_ibmon_ibtst.tcl 1274 2022-08-08 09:21:53Z mueller $
# SPDX-License-Identifier: GPL-3.0-or-later
# Copyright 2019- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
# Copyright 2019-2022 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
#
# Revision History:
# Date Rev Version Comment
# 2019-03-09 1120 1.0.1 use -brm,-bwf
# 2019-03-05 1118 1.0 Initial version
#
# Test register response
# 1. write/read IB space via bwm/brm (use MMU SAR SM I regs)
# 2. write/read IB space via wibr/ribr (use MMU SAR SM I regs)
# 3. test membe (byte write) via wibr/ribr
# ----------------------------------------------------------------------------
rlc log "test_ibmon_ibtest: tests with ibd_ibtst as target -------------------"

9
tools/tbench/w11a_pcnt/test_pcnt_codes.tcl
View File

@ -1,9 +1,10 @@
# $Id: test_pcnt_codes.tcl 1178 2019-06-30 12:39:40Z mueller $
# $Id: test_pcnt_codes.tcl 1273 2022-08-07 18:40:56Z mueller $
# SPDX-License-Identifier: GPL-3.0-or-later
# Copyright 2018- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
# Copyright 2018-2022 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
#
# Revision History:
# Date Rev Version Comment
# 2022-08-07 1273 1.0.1 ssr->mmr rename
# 2018-10-13 1055 1.0 Initial version
# 2018-10-06 1053 0.1 First draft
#
@ -126,7 +127,7 @@ $cpu cp -creset
$cpu cp \
-wreg pc.cntl [regbld rw11::PC_CNTL {func "CLR"}] \
-wreg pc.cntl [regbld rw11::PC_CNTL {func "STA"}] \
-wal $rw11::A_SAR_UM \
-wal $rw11::A_PAR_UM \
-bwm {0200 0201 0202 0203 0204 0205 0206 0207
0210 0211 0212 0213 0214 0215 0216 0217} \
-wreg pc.cntl [regbld rw11::PC_CNTL {func "STO"}]
@ -143,7 +144,7 @@ rlc log " A4: ibus via rbus read -----------------------------"
$cpu cp \
-wreg pc.cntl [regbld rw11::PC_CNTL {func "CLR"}] \
-wreg pc.cntl [regbld rw11::PC_CNTL {func "STA"}] \
-wal $rw11::A_SAR_UM \
-wal $rw11::A_PAR_UM \
-brm 16 -edata {0200 0201 0202 0203 0204 0205 0206 0207
0210 0211 0212 0213 0214 0215 0216 0217} \
-wreg pc.cntl [regbld rw11::PC_CNTL {func "STO"}]

53
tools/tcl/rw11/defs.tcl
View File

@ -1,14 +1,15 @@
# $Id: defs.tcl 1177 2019-06-30 12:34:07Z mueller $
# $Id: defs.tcl 1274 2022-08-08 09:21:53Z mueller $
# SPDX-License-Identifier: GPL-3.0-or-later
# Copyright 2014-2019 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
# Copyright 2014-2022 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
#
# Revision History:
# Date Rev Version Comment
# 2022-08-07 1273 1.0.9 ssr->mmr rename
# 2019-04-24 1138 1.0.8 add RCSR defs for KW11-L and KW11-P
# 2019-03-10 1121 1.0.7 define INIT bits; define ANUM
# 2018-09-09 1044 1.0.6 update defs kw11p, literals for KW11P_CSR(rate)
# 2017-02-17 851 1.0.5 defs for auxilliary devices (kw11l,kw11p,iist)
# 2016-12-30 834 1.0.4 fix typo in regmap_add for SDR's
# 2016-12-30 834 1.0.4 fix typo in regmap_add for PDR's
# 2016-01-02 724 1.0.3 add s: defs for CP_STAT(rust)
# 2015-12-26 719 1.0.2 add regmap_add defs; add CNTRL def
# 2015-09-06 710 1.0.1 regdsc PSW: add silent n,z,v,c; *mode syms; fix tflag
@ -55,31 +56,31 @@ namespace eval rw11 {
{rset 11} {pri 7 3 "d"} {tflag 4} {cc 3 4} \
{n 3 1 "-"} {z 2 1 "-"} {v 1 1 "-"} {c 0 1 "-"}
#
# SSR0 - MMU Segment Status Register #0 ----------------------------
set A_SSR0 0177572
regdsc SSR0 {abo_nonres 15} {abo_len 14} {abo_rd 13} \
# MMR0 - MMU Page Status Register #0 -------------------------------
set A_MMR0 0177572
regdsc MMR0 {abo_nonres 15} {abo_len 14} {abo_rd 13} \
{trap_mmu 12} {ena_trap 9} {inst_compl 7} \
{mode 6 2} {dspace 4} {num 3 3} {ena 0}
#
# SSR1 - MMU Segment Status Register #1 ----------------------------
set A_SSR1 0177574
regdsc SSR1 {delta1 15 5} {rnum1 10 3} {delta0 7 5} {rnum0 2 3}
# MMR1 - MMU Page Status Register #1 -------------------------------
set A_MMR1 0177574
regdsc MMR1 {delta1 15 5} {rnum1 10 3} {delta0 7 5} {rnum0 2 3}
#
# SSR2 - MMU Segment Status Register #2 ----------------------------
set A_SSR2 0177576
# MMR2 - MMU Page Status Register #2 -------------------------------
set A_MMR2 0177576
#
# SSR3 - MMU Segment Status Register #3 ----------------------------
set A_SSR3 0172516
regdsc SSR3 {ena_ubm 5} {ena_22bit 4} {d_km 2} {d_sm 1} {d_um 0}
# MMR3 - MMU Page Status Register #3 -------------------------------
set A_MMR3 0172516
regdsc MMR3 {ena_ubm 5} {ena_22bit 4} {d_km 2} {d_sm 1} {d_um 0}
#
# SAR/SDR - MMU Address/Segment Descriptor Register ----------------
set A_SDR_KM 0172300
set A_SAR_KM 0172340
set A_SDR_SM 0172200
set A_SAR_SM 0172240
set A_SDR_UM 0177600
set A_SAR_UM 0177640
regdsc SDR {slf 14 7} {aia 7} {aiw 6} {ed 3} {acf 2 3}
# PAR/PDR - MMU Page Descriptor/Address Register -----------------
set A_PDR_KM 0172300
set A_PAR_KM 0172340
set A_PDR_SM 0172200
set A_PAR_SM 0172240
set A_PDR_UM 0177600
set A_PAR_UM 0177640
regdsc PDR {slf 14 7} {aia 7} {aiw 6} {ed 3} {acf 2 3}
#
# PIRQ - Program Interrupt Requests -------------------------------
set A_PIRQ 0177772
@ -96,10 +97,10 @@ namespace eval rw11 {
# setup regmap
#
rw11util::regmap_add rw11 psw {?? PSW}
rw11util::regmap_add rw11 ssr0 {?? SSR0}
rw11util::regmap_add rw11 ssr1 {?? SSR1}
rw11util::regmap_add rw11 ssr3 {?? SSR3}
rw11util::regmap_add rw11 sdr??.? {?? SDR}
rw11util::regmap_add rw11 mmr0 {?? MMR0}
rw11util::regmap_add rw11 mmr1 {?? MMR1}
rw11util::regmap_add rw11 mmr3 {?? MMR3}
rw11util::regmap_add rw11 pdr??.? {?? PDR}
rw11util::regmap_add rw11 pirq {?? PIRQ}
rw11util::regmap_add rw11 cpuerr {?? CPUERR}
#

11
tools/tcl/rw11/shell_egd.tcl
View File

@ -1,9 +1,10 @@
# $Id: shell_egd.tcl 1177 2019-06-30 12:34:07Z mueller $
# $Id: shell_egd.tcl 1274 2022-08-08 09:21:53Z mueller $
# SPDX-License-Identifier: GPL-3.0-or-later
# Copyright 2015-2019 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
# Copyright 2015-2022 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
#
# Revision History:
# Date Rev Version Comment
# 2022-08-08 1274 1.1.3 ssr->mmr rename
# 2019-04-21 1134 1.1.2 shell_aspec_parse: allow 8,9 in numeric address
# 2017-06-09 910 1.1.1 BUGFIX: shell_pspec_map: fix mapping for addr>20000
# 2017-03-10 859 1.1 .egd: add /u option (memory access via ubmap)
@ -165,9 +166,9 @@ namespace eval rw11 {
set am0 [string range "ksxu" $xmode $xmode]
}
set segnum [expr {$addr>>13}]
set sarname "sar${am0}${am1}.${segnum}"
$shell_cpu cp -rreg $sarname sarval
set addr [expr {($addr & 017777) + 64 * $sarval}]
set parname "par${am0}${am1}.${segnum}"
$shell_cpu cp -rreg $parname parval
set addr [expr {($addr & 017777) + 64 * $parval}]
set am "e"
}
return [list "mem" $am $addr $cnt $fmt ]