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*.mac: ssr->mmr rename
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@ -1,13 +1,13 @@
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; $Id: defs_mmu.mac 1261 2022-07-23 16:15:03Z mueller $
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; $Id: defs_mmu.mac 1272 2022-08-07 17:37:51Z mueller $
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; SPDX-License-Identifier: GPL-3.0-or-later
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; Copyright 2015-2018 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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; Copyright 2015-2022 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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;
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; definitions for mmu registers (as in defs_mmu.das)
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;
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ssr0 = 177572
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ssr1 = 177574
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ssr2 = 177576
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ssr3 = 172516
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mmr0 = 177572
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mmr1 = 177574
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mmr2 = 177576
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mmr3 = 172516
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;
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uipdr = 177600 ; usr i page dsc base
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udpdr = 177620 ; usr d page dsc base
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@ -22,7 +22,7 @@
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kipar = 172340 ; ker i page addr base
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kdpar = 172360 ; ker d page addr base
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;
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; symbol definitions for ssr0
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; symbol definitions for mmr0
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;
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m0.anr = 100000 ; abort non-resident
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m0.ale = 040000 ; abort segment length
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@ -34,7 +34,7 @@
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m0.dsp = 000020 ; enable i/d space
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m0.ena = 000001 ; enable mmu
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;
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; symbol definitions for ssr3
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; symbol definitions for mmr3
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;
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m3.eub = 000040 ; enable unibus map
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m3.e22 = 000020 ; enable 22bit addressing
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@ -1,9 +1,10 @@
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# $Id: test_w11a_cpuerr.tcl 1254 2022-07-13 06:16:19Z mueller $
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# $Id: test_w11a_cpuerr.tcl 1272 2022-08-07 17:37:51Z mueller $
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# SPDX-License-Identifier: GPL-3.0-or-later
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# Copyright 2016- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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# Copyright 2016-2022 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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#
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# Revision History:
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# Date Rev Version Comment
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# 2022-08-06 1272 1.0.1 ssr->mmr rename
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# 2016-12-27 831 1.0 Initial version
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#
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# Test cpuerr register
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@ -57,15 +58,15 @@ t.002:
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;
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jsr pc, mminki ; init MMU, kernel I space only
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mov #177400,@#kipar+014 ; kipar(6): to page below I/O page
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mov #m3.e22,@#ssr3 ; enable 22bit
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mov #m0.ena,@#ssr0 ; enable MMU
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mov #m3.e22,@#mmr3 ; enable 22bit
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mov #m0.ena,@#mmr0 ; enable MMU
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;
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mov #t.004,r4 ; setup continuation address
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mov #140000,r0 ; r0 points to non-existent memory
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tst (r0) ; access
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; !! will trap to 004 and set 000040 !!
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halt ; blocker
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t.004: clr @#ssr0 ; disable MMU
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t.004: clr @#mmr0 ; disable MMU
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;
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; test 005: I/O bus timeout abort; will set bit cp.ito -----------------------
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;
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@ -1,9 +1,10 @@
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# $Id: test_cmon_logs.tcl 1178 2019-06-30 12:39:40Z mueller $
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# $Id: test_cmon_logs.tcl 1272 2022-08-07 17:37:51Z mueller $
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# SPDX-License-Identifier: GPL-3.0-or-later
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# Copyright 2015-2017 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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# Copyright 2015-2022 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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#
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# Revision History:
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# Date Rev Version Comment
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# 2022-08-06 1272 2.0.1 ssr->mmr rename
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# 2017-04-23 885 2.0 adopt to revised interface
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# 2015-08-02 707 1.0 Initial version
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#
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@ -578,19 +579,19 @@ start: mov #<77400+md.arw>,@#<kipdr+00> ; s0: slf=127; ed=0; acf=rw
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mov #<77400+md.arw>,@#<kipdr+16> ; s7: slf=127; ed=0; acf=rw
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mov #177600,@#<kipar+16> ; to io page (22 bit)
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mov #234,vtst
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mov #m3.e22,@#ssr3 ; enable 22bit mode
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mov #<m0.ent+m0.ena>,@#ssr0 ; enable mmu, enable traps
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mov #m3.e22,@#mmr3 ; enable 22bit mode
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mov #<m0.ent+m0.ena>,@#mmr0 ; enable mmu, enable traps
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;
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mov vtst,r0 ; no trap (is read)
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inc r0
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mov r0,vtst ; should trap (is write)
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inc vtst ; should trap (is read-mod-write)
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;
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clr @#ssr0
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clr @#mmr0
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halt
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stop:
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;
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vh.mmu: mov #<m0.ent+m0.ena>,@#ssr0 ; clear error flags, keep enables
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vh.mmu: mov #<m0.ent+m0.ena>,@#mmr0 ; clear error flags, keep enables
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rti
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;
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vh.xxx: halt
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@ -776,8 +777,8 @@ start: mov #<77400+md.arw>,@#<kipdr+00> ; s0: slf=127; ed=0; acf=rw
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mov #077400,@#<kipdr+02> ; s1: slf=127; ed=0; acf=abo
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mov #<77400+md.arw>,@#<kipdr+16> ; s7: slf=127; ed=0; acf=rw
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mov #177600,@#<kipar+16> ; to io page (22 bit)
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mov #m3.e22,@#ssr3 ; enable 22bit mode
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mov #m0.ena,@#ssr0 ; enable mmu
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mov #m3.e22,@#mmr3 ; enable 22bit mode
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mov #m0.ena,@#mmr0 ; enable mmu
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;
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mov #bad,r5 ; to blocker
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mov vok,a ; should be ok
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@ -787,7 +788,7 @@ start: mov #<77400+md.arw>,@#<kipdr+00> ; s0: slf=127; ed=0; acf=rw
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ok: mov #bad,r5 ; to blocker
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mov vok,a ; should be ok again
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;
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clr @#ssr0
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clr @#mmr0
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halt
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stop:
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bad: halt
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@ -795,10 +796,10 @@ bad: halt
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a: .word 0
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b: .word 0
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;
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vh.mmu: mov @#ssr0,r0 ; check ssr0
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mov @#ssr1,r1 ; check ssr1
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mov @#ssr2,r2 ; check ssr2
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mov #m0.ena,@#ssr0 ; clear error flags, keep enable
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vh.mmu: mov @#mmr0,r0 ; check mmr0
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mov @#mmr1,r1 ; check mmr1
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mov @#mmr2,r2 ; check mmr2
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mov #m0.ena,@#mmr0 ; clear error flags, keep enable
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mov r5,(sp) ; use recovery address
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rti
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;
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@ -1,17 +1,18 @@
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; $Id: cpu_mmu.mac 1264 2022-07-30 07:42:17Z mueller $
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; $Id: cpu_mmu.mac 1272 2022-08-07 17:37:51Z mueller $
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; SPDX-License-Identifier: GPL-3.0-or-later
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; Copyright 2022- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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;
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; Revision History:
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; Date Rev Version Comment
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; 2022-08-06 1272 1.0.1 ssr->mmr rename
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; 2022-07-28 1264 1.0 Initial version
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; 2022-07-24 1262 0.1 First draft
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;
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; Test CPU MMU: all aspects of the MMU
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; Section A: pdr,par registers
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; Section B: ssr0,ssr3 registers, mapping, instructions
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; Section C: ssr1 register and traps
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; Section D: ssr2 register and aborts
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; Section B: mmr0,mmr3 registers, mapping, instructions
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; Section C: mmr1 register and traps
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; Section D: mmr2 register and aborts
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;
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.include |lib/tcode_std_base.mac|
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.include |lib/defs_mmu.mac|
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@ -156,34 +157,34 @@ ta0102:
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;
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9999$: iot ; end of test A1.2
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;
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; Section B: ssr0,ssr3 registers, mapping, instructions ======================
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; Section B: mmr0,mmr3 registers, mapping, instructions ======================
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; Test whether address mapping works (traps and aborts avoided)
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;
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; Test B1: ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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; Test ssr0, ssr3 write/read and clear by RESET
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; Test mmr0, mmr3 write/read and clear by RESET
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;
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; This test verifies
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; x xxx xxx xxx xxx xxx NZVC Instruction / Remark
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; 0 000 000 000 000 101 ---- RESET (clear ssr0,ssr3)
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; 0 000 000 000 000 101 ---- RESET (clear mmr0,mmr3)
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;
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; Test B1.1 -- test ssr0 write/read ++++++++++++++++++++++++++++++++++
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; Test B1.1 -- test mmr0 write/read ++++++++++++++++++++++++++++++++++
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; Test all writable bits except m0.ena
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;
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tb0101: mov #ssr0,r0 ; ptr to ssr0
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tb0101: mov #mmr0,r0 ; ptr to mmr0
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mov #m0.ico,r1 ; instruction complete flag
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mov #1010$,r4 ; ptr to data
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mov #1011$,r3 ; ptr to data end
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100$: mov (r4),(r0) ; write ssr0
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mov (r0),r5 ; read ssr0
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100$: mov (r4),(r0) ; write mmr0
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mov (r0),r5 ; read mmr0
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bic r1,r5 ; mask instruction complete
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hcmpeq r5,(r4)+ ; check
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cmp r4,r3 ; more to do ?
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blo 100$
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;
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reset ; ssr0 has 5 bits set, check clear
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mov (r0),r5 ; read ssr0
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reset ; mmr0 has 5 bits set, check clear
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mov (r0),r5 ; read mmr0
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bic r1,r5 ; mask instruction complete
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htsteq r5 ; check ssr0 cleared
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htsteq r5 ; check mmr0 cleared
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jmp 9999$
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;
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1010$: .word m0.anr ; abort flags
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@ -196,19 +197,19 @@ tb0101: mov #ssr0,r0 ; ptr to ssr0
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;
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9999$: iot ; end of test B1.1
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;
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; Test B1.2 -- test ssr3 write/read ++++++++++++++++++++++++++++++++++
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; Test B1.2 -- test mmr3 write/read ++++++++++++++++++++++++++++++++++
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; Test all writable bits; mmu is off, and unibus map not used
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;
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tb0102: mov #ssr3,r0 ; ptr to ssr3
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tb0102: mov #mmr3,r0 ; ptr to mmr3
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mov #1010$,r4 ; ptr to data
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mov #1011$,r3 ; ptr to data end
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100$: mov (r4),(r0) ; write ssr3
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100$: mov (r4),(r0) ; write mmr3
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hcmpeq (r0),(r4)+ ; check
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cmp r4,r3 ; more to do ?
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blo 100$
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;
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reset ; ssr3 has 5 bits set, check clear
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htsteq (r0) ; check ssr3 cleared
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reset ; mmr3 has 5 bits set, check clear
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htsteq (r0) ; check mmr3 cleared
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jmp 9999$
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;
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1010$: .word m3.eub
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@ -227,13 +228,13 @@ tb0102: mov #ssr3,r0 ; ptr to ssr3
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; Test B2.1 -- test 1-to-1 kernel mode mapping +++++++++++++++++++++++
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; simply enable MMU, shouldnt make a difference
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; test that 18bit mode extends I/O page addressing
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; test that RESET clears ssr0 and ssr3
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; test that RESET clears mmr0 and mmr3
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;
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tb0201: mov #123456,1000$
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; enable mmu in 18bit mode
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clr ssr3 ; no d dspace, no 22bit
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mov #m0.ena,ssr0 ; enable mmu
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hbitne #m0.ena,ssr0 ; test bit ;! MMU 18
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clr mmr3 ; no d dspace, no 22bit
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mov #m0.ena,mmr0 ; enable mmu
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hbitne #m0.ena,mmr0 ; test bit ;! MMU 18
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hcmpeq 1000$,#123456 ; check marker
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; verify I/O page mapping in 18bit mode (007600 must be OK)
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mov #kipar7,r0 ; ptr to kipar7
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@ -241,13 +242,13 @@ tb0201: mov #123456,1000$
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hcmpeq (r0),#007600 ; kipar7 still seen ???
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bis #170000,(r0) ; restore kipar7
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hcmpeq (r0),#177600
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; enable mmu in 22bit mode; check that ssr3 still seen
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mov #m3.e22,ssr3
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hcmpeq ssr3,#m3.e22 ; test ssr3 stll seen ??? ;! MMU 22
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; enable mmu in 22bit mode; check that mmr3 still seen
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mov #m3.e22,mmr3
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hcmpeq mmr3,#m3.e22 ; test mmr3 stll seen ??? ;! MMU 22
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; test RESET
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reset ; should clear ssr0 and ssr3
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htsteq ssr0 ; check ssr0 cleared ;! MMU off
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htsteq ssr3 ; check ssr3 cleared
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reset ; should clear mmr0 and mmr3
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htsteq mmr0 ; check mmr0 cleared ;! MMU off
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htsteq mmr3 ; check mmr3 cleared
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jmp 9999$
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;
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1000$: .word 0
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@ -265,8 +266,8 @@ tb0202: mov #kipar6,r0 ; ptr to kipar6
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mov #140100,100(r5) ; init markers
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clr 102(r5)
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;
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clr ssr3 ; no d dspace, no 22bit
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mov #m0.ena,ssr0 ; enable mmu ;! MMU 18
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clr mmr3 ; no d dspace, no 22bit
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mov #m0.ena,mmr0 ; enable mmu ;! MMU 18
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; check in 1-to-1 mapping
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hcmpeq (r5),#140000
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htsteq 2(r5)
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@ -306,8 +307,8 @@ tb0301:
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mov #vhuemt,v..emt
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clr v..emt+2 ; pr0 kernel
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; enable mmu
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clr ssr3 ; no d dspace, no 22bit
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mov #m0.ena,ssr0 ; enable mmu ;! MMU 18
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clr mmr3 ; no d dspace, no 22bit
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mov #m0.ena,mmr0 ; enable mmu ;! MMU 18
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;
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; run code vc0 in user mode --------------------------------
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;
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@ -383,8 +384,8 @@ tb0302:
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mov #vhuemt,v..emt
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clr v..emt+2 ; pr0 kernel
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; enable mmu
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mov #m3.dum,ssr3 ; user d dspace, no 22bit
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mov #m0.ena,ssr0 ; enable mmu ;! MMU 18
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mov #m3.dum,mmr3 ; user d dspace, no 22bit
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mov #m0.ena,mmr0 ; enable mmu ;! MMU 18
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;
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; run code vc1 in user mode --------------------------------
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;
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@ -526,20 +527,20 @@ tb0302:
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;
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9999$: iot ; end of test B3.2
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;
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; Section C: ssr1 register and traps =========================================
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; Section C: mmr1 register and traps =========================================
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;
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; Test C1: ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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;
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; Test C1.1 -- test ssr1 response via set abort in ssr0 trick ++++++++
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; Test C1.1 -- test mmr1 response via set abort in mmr0 trick ++++++++
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; Test method (concept seen in ekbee1)
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; - start with ssr1 cleared, ssr1 will track
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; - write one of the 3 abort bits in ssr1 (all three are tested)
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; - that will freeze ssr1
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; - start with mmr1 cleared, mmr1 will track
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; - write one of the 3 abort bits in mmr1 (all three are tested)
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; - that will freeze mmr1
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; - the register signature of the write can be inspected
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;
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tc0101: mov #1000$,r1 ; ptr to abort bit table
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mov #ssr0,r2 ; ptr to ssr0
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mov #ssr1,r3 ; ptr to ssr3
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mov #mmr0,r2 ; ptr to mmr0
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mov #mmr1,r3 ; ptr to mmr3
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;
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reset
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mov (r1),(r2) ; no regs changed !
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@ -574,7 +575,7 @@ tc0101: mov #1000$,r1 ; ptr to abort bit table
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mov (r1)+,(r2)+ ; r1,2,r2,2 00010 010 00010 001 via ale
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hcmpeq (r3),#^b0001001000010001;
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;
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; check that index reads are not accounted in ssr1
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; check that index reads are not accounted in mmr1
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reset
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tst (r1)+ ; bump ptr beyond ard
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mov -(r1),-2(r2) ; r1,-1 00000 000 11110 001 via ard
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@ -582,10 +583,10 @@ tc0101: mov #1000$,r1 ; ptr to abort bit table
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;
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; check @(pc)+ behavior
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; Simh only adds 'general purpose register updates, thus not pc
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; w11 updates ssr1 in this case, as is also expected in ekbee1
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; w11 updates mmr1 in this case, as is also expected in ekbee1
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; case commented out to ensure that cpu_mmu.mac runs on both
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;; reset
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;; mov -(r1),@#ssr0 ; r1,-2,pc,2 00010 111 11110 001 via ale
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;; mov -(r1),@#mmr0 ; r1,-2,pc,2 00010 111 11110 001 via ale
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;; hcmpeq (r3),#^b0001011111110001;
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;
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reset
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