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minor cleanups; update vmfset and imfset

Browse Source 
- Makefile: drop ISE targets except for w11a
- rtl/sys_gen/**/*.*mfset: accomodate recent changes
- rtl/w11a
  - pdp11_dpath.vhd: remove PCOUT port
  - pdp11_sequencer.vhd: remove PC port
This commit is contained in:
wfjm
2022-12-27 13:32:12 +01:00
parent c9d447f2be
commit 67437bf140
23 changed files with 153 additions and 139 deletions
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53
Makefile
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@@ -1,4 +1,4 @@
# $Id: Makefile 1244 2022-06-03 14:06:30Z mueller $
# $Id: Makefile 1339 2022-12-27 12:11:34Z mueller $
# SPDX-License-Identifier: GPL-3.0-or-later
# Copyright 2011-2022 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
#
@@ -8,6 +8,7 @@
#
# Revision History:
# Date Rev Version Comment
# 2022-12-27 1388 1.2.14 drop ISE targets except for w11a
# 2022-06-03 1244 1.2.13 use 3G memory for njobihtm in vivado targets
# 2019-08-07 1201 1.2.12 drop nexys4, add nexys4d
# 2019-01-10 1111 1.2.11 drop w11a/arty_bram
@@ -38,31 +39,31 @@
# ISE based targets, by board type -----------------------
# S3board ------------------------------------
SYN_ise += rtl/sys_gen/tst_rlink/s3board
SYN_ise += rtl/sys_gen/tst_serloop/s3board
SYN_ise += rtl/sys_gen/tst_snhumanio/s3board
SYN_ise += rtl/sys_gen/tst_sram/s3board
#SYN_ise += rtl/sys_gen/tst_rlink/s3board
#SYN_ise += rtl/sys_gen/tst_serloop/s3board
#SYN_ise += rtl/sys_gen/tst_snhumanio/s3board
#SYN_ise += rtl/sys_gen/tst_sram/s3board
SYN_ise += rtl/sys_gen/w11a/s3board
# Nexys2 -------------------------------------
#SYN_ise += rtl/sys_gen/tst_fx2loop/nexys2/ic
#SYN_ise += rtl/sys_gen/tst_fx2loop/nexys2/ic3
SYN_ise += rtl/sys_gen/tst_rlink/nexys2
SYN_ise += rtl/sys_gen/tst_rlink_cuff/nexys2/ic
#SYN_ise += rtl/sys_gen/tst_rlink/nexys2
#SYN_ise += rtl/sys_gen/tst_rlink_cuff/nexys2/ic
#SYN_ise += rtl/sys_gen/tst_rlink_cuff/nexys2/ic3
SYN_ise += rtl/sys_gen/tst_serloop/nexys2
SYN_ise += rtl/sys_gen/tst_snhumanio/nexys2
SYN_ise += rtl/sys_gen/tst_sram/nexys2
#SYN_ise += rtl/sys_gen/tst_serloop/nexys2
#SYN_ise += rtl/sys_gen/tst_snhumanio/nexys2
#SYN_ise += rtl/sys_gen/tst_sram/nexys2
SYN_ise += rtl/sys_gen/w11a/nexys2
# Nexys3 -------------------------------------
#SYN_ise += rtl/sys_gen/tst_fx2loop/nexys3/ic
#SYN_ise += rtl/sys_gen/tst_fx2loop/nexys3/ic3
SYN_ise += rtl/sys_gen/tst_rlink/nexys3
SYN_ise += rtl/sys_gen/tst_rlink_cuff/nexys3/ic
SYN_ise += rtl/sys_gen/tst_serloop/nexys3
SYN_ise += rtl/sys_gen/tst_snhumanio/nexys3
SYN_ise += rtl/sys_gen/tst_sram/nexys3
#SYN_ise += rtl/sys_gen/tst_rlink/nexys3
#SYN_ise += rtl/sys_gen/tst_rlink_cuff/nexys3/ic
#SYN_ise += rtl/sys_gen/tst_serloop/nexys3
#SYN_ise += rtl/sys_gen/tst_snhumanio/nexys3
#SYN_ise += rtl/sys_gen/tst_sram/nexys3
SYN_ise += rtl/sys_gen/w11a/nexys3
# Vivado based targets, by board type --------------------
@@ -97,23 +98,23 @@ SYN_viv += rtl/sys_gen/w11a/cmoda7
# Component tests ----------------------------
# S3board ------------------------------------
SIM_ise += rtl/sys_gen/tst_rlink/s3board/tb
SIM_ise += rtl/sys_gen/tst_serloop/s3board/tb
SIM_ise += rtl/sys_gen/tst_sram/s3board/tb
#SIM_ise += rtl/sys_gen/tst_rlink/s3board/tb
#SIM_ise += rtl/sys_gen/tst_serloop/s3board/tb
#SIM_ise += rtl/sys_gen/tst_sram/s3board/tb
SIM_ise += rtl/sys_gen/w11a/s3board/tb
# Nexys2 -------------------------------------
SIM_ise += rtl/sys_gen/tst_rlink/nexys2/tb
SIM_ise += rtl/sys_gen/tst_rlink_cuff/nexys2/ic/tb
SIM_ise += rtl/sys_gen/tst_serloop/nexys2/tb
SIM_ise += rtl/sys_gen/tst_sram/nexys2/tb
#SIM_ise += rtl/sys_gen/tst_rlink/nexys2/tb
#SIM_ise += rtl/sys_gen/tst_rlink_cuff/nexys2/ic/tb
#SIM_ise += rtl/sys_gen/tst_serloop/nexys2/tb
#SIM_ise += rtl/sys_gen/tst_sram/nexys2/tb
SIM_ise += rtl/sys_gen/w11a/nexys2/tb
# Nexys3 -------------------------------------
SIM_ise += rtl/sys_gen/tst_rlink/nexys3/tb
SIM_ise += rtl/sys_gen/tst_rlink_cuff/nexys3/ic/tb
SIM_ise += rtl/sys_gen/tst_serloop/nexys3/tb
SIM_ise += rtl/sys_gen/tst_sram/nexys3/tb
#SIM_ise += rtl/sys_gen/tst_rlink/nexys3/tb
#SIM_ise += rtl/sys_gen/tst_rlink_cuff/nexys3/ic/tb
#SIM_ise += rtl/sys_gen/tst_serloop/nexys3/tb
#SIM_ise += rtl/sys_gen/tst_sram/nexys3/tb
SIM_ise += rtl/sys_gen/w11a/nexys3/tb
# Vivado flow --------------------------------------------

3
doc/simh_diff_traced-rti-rtt.md
View File

@@ -9,7 +9,8 @@ tbit=0 does not cause a tbit trap. More precisely:
The Processor Handbook documentation is misleading and at one point simply wrong.
On SimH, a traced `RTI` or `RTT` does trap. Confirmed bug, will be fixed.
On SimH, a traced `RTI` or `RTT` does trap.
Confirmed deficiency, will be fixed.
The w11 implements traced `RTI` or `RTT` correctly, the corresponding test
is skipped when executed on SimH

4
doc/simh_diff_traced-vector.md
View File

@@ -2,9 +2,11 @@
### SimH: vector flow that sets tbit does not trap
On an 11/70, a vector flow loading a new `PS` with tbit=1 ends with a tbit trap.
On an 11/70 and on a J11, a vector flow loading a new `PS` with tbit=1 ends
with a tbit trap.
On SimH, a vector flow loading a new `PS` with tbit=1 does not tbit trap.
Confirmed deficiency, will be fixed.
The w11 implements the 11/70 behavior, the corresponding tests
are skipped when executed on SimH

8
rtl/sys_gen/tst_sram/cmoda7/sys_tst_sram_c7.vmfset
View File

@@ -1,8 +1,8 @@
# $Id: sys_tst_sram_c7.vmfset 1242 2022-05-27 17:08:43Z mueller $
# $Id: sys_tst_sram_c7.vmfset 1338 2022-12-26 18:00:37Z mueller $
#
# Validated code/tool version combinations
# Date rev viv
# 2022-05-26 1242 2022.1
# 2022-12-26 1338 2022.1
# 2022-04-23 1225 2020.1
# 2019-02-02 1108 2018.3
# 2019-02-02 1108 2017.2
@@ -54,6 +54,10 @@ i [Synth 8-7129] MEM_ACK_W .* tst_sram
i [Synth 8-7129] CE_(USEC|MSEC) .* rlink_sp2c
{:}
# port driven by constant --------------------------------------
# --> RGBLED0 currently unused # OK 2022-12-26
i [Synth 8-3917] O_RGBLED0_N[\d]
# sequential element removed (2017.1 nonsense) -----------------
I [Synth 8-6014] _reg # generic

8
rtl/sys_gen/tst_sram/nexys4d/sys_tst_sram_n4d.vmfset
View File

@@ -1,8 +1,8 @@
# $Id: sys_tst_sram_n4d.vmfset 1242 2022-05-27 17:08:43Z mueller $
# $Id: sys_tst_sram_n4d.vmfset 1338 2022-12-26 18:00:37Z mueller $
#
# Validated code/tool version combinations
# Date rev viv
# 2022-05-26 1242 2022.1
# 2022-12-26 1338 2022.1
# 2022-04-23 1225 2020.1
# 2019-02-02 1108 2018.3
# 2019-02-02 1108 2017.2
@@ -54,6 +54,10 @@ i [Synth 8-7129] CE_(USEC|MSEC) .* rlink_sp2c
i [Synth 8-7129] APP_RD_DATA_END .* sramif2migui_core
{:}
# port driven by constant --------------------------------------
# --> RGBLED0 currently unused # OK 2022-12-26
i [Synth 8-3917] O_RGBLED0[\d]
# sequential element removed (2017.1 nonsense) -----------------
I [Synth 8-6014] _reg # generic

12
rtl/sys_gen/w11a/arty/sys_w11a_arty.vmfset
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@@ -1,8 +1,8 @@
# $Id: sys_w11a_arty.vmfset 1325 2022-12-07 11:52:36Z mueller $
# $Id: sys_w11a_arty.vmfset 1338 2022-12-26 18:00:37Z mueller $
#
# Validated code/tool version combinations
# Date rev viv
# 2022-05-26 1242 2022.1
# 2022-12-26 1338 2022.1
# 2022-04-23 1225 2020.1
# 2019-06-05 1159 2019.1
# 2019-02-02 1108 2018.3
@@ -45,7 +45,7 @@ i [Synth 8-3331] pdp11_lunit .* CCIN[(1|2)]
# --> some psr bits are unused # OK 2018-12-28
i [Synth 8-3331] pdp11_psr .* DIN[(8|9|10)]
# --> not all moni fields used # OK 2018-12-28
i [Synth 8-3331] pdp11_mmu_ssr12 .* MONI[(idone|trace_prev)]
i [Synth 8-3331] pdp11_mmu_mmr12 .* MONI[(vflow|trace_prev)]
# --> not all CNTL fieds used; also 6 LSBs from vaddr # OK 2018-12-28
i [Synth 8-3331] pdp11_mmu .* VADDR[(0|1|2|3|4|5)]
# --> so far no usage of usec and msec pulse # OK 2018-12-28
@@ -74,10 +74,8 @@ i [Synth 8-7129] IREG[1(1|2|3|4)] .* pdp11_sequencer
i [Synth 8-7129] CCIN[(1|2)] .* pdp11_lunit
# --> some psr bits are unused # OK 2022-05-26
i [Synth 8-7129] DIN[(8|9|10)] .* pdp11_psr
# --> not all moni fields used # OK 2022-05-26
i [Synth 8-7129] MONI[(idone|trace_prev)] .* pdp11_mmu_ssr12
# --> not all CNTL fieds used; also 6 LSBs from vaddr # OK 2022-05-26
i [Synth 8-7129] VADDR[(0|1|2|3|4|5)] .* pdp11_mmu
# --> not all moni fields used # OK 2022-12-26
i [Synth 8-7129] MONI[(vflow|trace_prev)] .* pdp11_mmu_mmr12
# --> so far no usage of usec and msec pulse # OK 2022-05-26
i [Synth 8-7129] (CE_USEC|CE_MSEC) .* rlink_sp2c
# --> msec indeed not used # OK 2022-05-26

12
rtl/sys_gen/w11a/arty_bram/sys_w11a_br_arty.vmfset
View File

@@ -1,8 +1,8 @@
# $Id: sys_w11a_br_arty.vmfset 1325 2022-12-07 11:52:36Z mueller $
# $Id: sys_w11a_br_arty.vmfset 1338 2022-12-26 18:00:37Z mueller $
#
# Validated code/tool version combinations
# Date rev viv
# 2022-05-26 1242 2022.1
# 2022-12-26 1338 2022.1
# 2019-06-05 1159 2019.1
# 2019-02-02 1108 2018.3
# 2019-02-02 1108 2017.2
@@ -44,7 +44,7 @@ i [Synth 8-3331] pdp11_lunit .* CCIN[(1|2)]
# --> some psr bits are unused # OK 2018-11-18
i [Synth 8-3331] pdp11_psr .* DIN[(8|9|10)]
# --> not all moni fields used # OK 2018-11-18
i [Synth 8-3331] pdp11_mmu_ssr12 .* MONI[(idone|trace_prev)]
i [Synth 8-3331] pdp11_mmu_mmr12 .* MONI[(vflow|trace_prev)]
# --> not all CNTL fieds used; also 6 LSBs from vaddr # OK 2018-11-18
i [Synth 8-3331] pdp11_mmu .* VADDR[(0|1|2|3|4|5)]
# --> so far no usage of usec and msec pulse # OK 2018-11-18
@@ -73,10 +73,8 @@ i [Synth 8-7129] IREG[1(1|2|3|4)] .* pdp11_sequencer
i [Synth 8-7129] CCIN[(1|2)] .* pdp11_lunit
# --> some psr bits are unused # OK 2022-05-26
i [Synth 8-7129] DIN[(8|9|10)] .* pdp11_psr
# --> not all moni fields used # OK 2022-05-26
i [Synth 8-7129] MONI[(idone|trace_prev)] .* pdp11_mmu_ssr12
# --> not all CNTL fieds used; also 6 LSBs from vaddr # OK 2022-05-26
i [Synth 8-7129] VADDR[(0|1|2|3|4|5)] .* pdp11_mmu
# --> not all moni fields used # OK 2022-12-26
i [Synth 8-7129] MONI[(vflow|trace_prev)] .* pdp11_mmu_mmr12
# --> so far no usage of usec and msec pulse # OK 2022-05-26
i [Synth 8-7129] (CE_USEC|CE_MSEC) .* rlink_sp2c
# --> only small memory available # OK 2022-05-26

12
rtl/sys_gen/w11a/artys7/sys_w11a_as7.vmfset
View File

@@ -1,8 +1,8 @@
# $Id: sys_w11a_as7.vmfset 1325 2022-12-07 11:52:36Z mueller $
# $Id: sys_w11a_as7.vmfset 1338 2022-12-26 18:00:37Z mueller $
#
# Validated code/tool version combinations
# Date rev viv
# 2022-05-26 1242 2022.1
# 2022-12-26 1338 2022.1
# 2019-02-02 1108 2018.3
#
# ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
@@ -42,7 +42,7 @@ i [Synth 8-3331] pdp11_lunit .* CCIN[(1|2)]
# --> some psr bits are unused # OK 2019-01-12
i [Synth 8-3331] pdp11_psr .* DIN[(8|9|10)]
# --> not all moni fields used # OK 2019-01-12
i [Synth 8-3331] pdp11_mmu_ssr12 .* MONI[(idone|trace_prev)]
i [Synth 8-3331] pdp11_mmu_mmr12 .* MONI[(vflow|trace_prev)]
# --> not all CNTL fieds used; also 6 LSBs from vaddr # OK 2019-01-12
i [Synth 8-3331] pdp11_mmu .* VADDR[(0|1|2|3|4|5)]
# --> so far no usage of usec and msec pulse # OK 2019-01-12
@@ -73,10 +73,8 @@ i [Synth 8-7129] IREG[1(1|2|3|4)] .* pdp11_sequencer
i [Synth 8-7129] CCIN[(1|2)] .* pdp11_lunit
# --> some psr bits are unused # OK 2022-05-26
i [Synth 8-7129] DIN[(8|9|10)] .* pdp11_psr
# --> not all moni fields used # OK 2022-05-26
i [Synth 8-7129] MONI[(idone|trace_prev)] .* pdp11_mmu_ssr12
# --> not all CNTL fieds used; also 6 LSBs from vaddr # OK 2022-05-26
i [Synth 8-7129] VADDR[(0|1|2|3|4|5)] .* pdp11_mmu
# --> not all moni fields used # OK 2022-12-26
i [Synth 8-7129] MONI[(vflow|trace_prev)] .* pdp11_mmu_mmr12
# --> pdp11_hio70_arty doesn't use MEM_ACT # OK 2022-05-26
i [Synth 8-7129] MEM_ACT_(R|W) .* pdp11_hio70_artys7
# --> so far no usage of usec and msec pulse # OK 2022-05-26

12
rtl/sys_gen/w11a/artys7_bram/sys_w11a_br_as7.vmfset
View File

@@ -1,8 +1,8 @@
# $Id: sys_w11a_br_as7.vmfset 1325 2022-12-07 11:52:36Z mueller $
# $Id: sys_w11a_br_as7.vmfset 1338 2022-12-26 18:00:37Z mueller $
#
# Validated code/tool version combinations
# Date rev viv
# 2022-05-26 1242 2022.1
# 2022-12-26 1338 2022.1
# 2019-06-05 1159 2019.1
# 2019-02-02 1108 2018.3
# 2019-02-02 1108 2017.2
@@ -44,7 +44,7 @@ i [Synth 8-3331] pdp11_lunit .* CCIN[(1|2)]
# --> some psr bits are unused # OK 2018-11-18
i [Synth 8-3331] pdp11_psr .* DIN[(8|9|10)]
# --> not all moni fields used # OK 2018-11-18
i [Synth 8-3331] pdp11_mmu_ssr12 .* MONI[(idone|trace_prev)]
i [Synth 8-3331] pdp11_mmu_mmr12 .* MONI[(vflow|trace_prev)]
# --> not all CNTL fieds used; also 6 LSBs from vaddr # OK 2018-11-18
i [Synth 8-3331] pdp11_mmu .* VADDR[(0|1|2|3|4|5)]
# --> so far no usage of usec and msec pulse # OK 2018-11-18
@@ -75,11 +75,9 @@ i [Synth 8-7129] IREG[1(1|2|3|4)] .* pdp11_sequencer
i [Synth 8-7129] CCIN[(1|2)] .* pdp11_lunit
# --> some psr bits are unused # OK 2022-05-26
i [Synth 8-7129] DIN[(8|9|10)] .* pdp11_psr
# --> not all moni fields used # OK 2022-05-26
i [Synth 8-7129] MONI[(idone|trace_prev)] .* pdp11_mmu_ssr12
# --> not all moni fields used # OK 2022-12-26
i [Synth 8-7129] MONI[(vflow|trace_prev)] .* pdp11_mmu_mmr12
# --> not all CNTL fieds used; also 6 LSBs from vaddr # OK 2022-05-26
i [Synth 8-7129] VADDR[(0|1|2|3|4|5)] .* pdp11_mmu
# --> so far no usage of usec and msec pulse # OK 2022-05-26
i [Synth 8-7129] (CE_USEC|CE_MSEC) .* rlink_sp2c
# --> pdp11_hio70_arty doesn't use MEM_ACT # OK 2022-05-26
i [Synth 8-7129] MEM_ACT_(R|W) .* pdp11_hio70_artys7

12
rtl/sys_gen/w11a/basys3/sys_w11a_b3.vmfset
View File

@@ -1,8 +1,8 @@
# $Id: sys_w11a_b3.vmfset 1325 2022-12-07 11:52:36Z mueller $
# $Id: sys_w11a_b3.vmfset 1338 2022-12-26 18:00:37Z mueller $
#
# Validated code/tool version combinations
# Date rev viv
# 2022-05-26 1242 2022.1
# 2022-12-26 1338 2022.1
# 2022-04-23 1225 2020.1
# 2019-06-05 1159 2019.1
# 2019-02-02 1108 2018.3
@@ -45,7 +45,7 @@ i [Synth 8-3331] pdp11_lunit .* CCIN[(1|2)]
# --> some psr bits are unused # OK 2018-11-18
i [Synth 8-3331] pdp11_psr .* DIN[(8|9|10)]
# --> not all moni fields used # OK 2018-11-18
i [Synth 8-3331] pdp11_mmu_ssr12 .* MONI[(idone|trace_prev)]
i [Synth 8-3331] pdp11_mmu_mmr12 .* MONI[(vflow|trace_prev)]
# --> not all CNTL fieds used; also 6 LSBs from vaddr # OK 2018-11-18
i [Synth 8-3331] pdp11_mmu .* VADDR[(0|1|2|3|4|5)]
# --> so far no usage of usec and msec pulse # OK 2018-11-18
@@ -74,10 +74,8 @@ i [Synth 8-7129] IREG[1(1|2|3|4)] .* pdp11_sequencer
i [Synth 8-7129] CCIN[(1|2)] .* pdp11_lunit
# --> some psr bits are unused # OK 2022-05-26
i [Synth 8-7129] DIN[(8|9|10)] .* pdp11_psr
# --> not all moni fields used # OK 2022-05-26
i [Synth 8-7129] MONI[(idone|trace_prev)] .* pdp11_mmu_ssr12
# --> not all CNTL fieds used; also 6 LSBs from vaddr # OK 2022-05-26
i [Synth 8-7129] VADDR[(0|1|2|3|4|5)] .* pdp11_mmu
# --> not all moni fields used # OK 2022-12-26
i [Synth 8-7129] MONI[(vflow|trace_prev)] .* pdp11_mmu_mmr12
# --> so far no usage of usec and msec pulse # OK 2022-05-26
i [Synth 8-7129] (CE_USEC|CE_MSEC) .* rlink_sp2c
# --> small memory, not all addr lines connected # OK 2022-05-26

3
rtl/sys_gen/w11a/cmoda7/sys_w11a_c7.vhd
View File

@@ -1,4 +1,4 @@
-- $Id: sys_w11a_c7.vhd 1325 2022-12-07 11:52:36Z mueller $
-- $Id: sys_w11a_c7.vhd 1339 2022-12-27 12:11:34Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2017-2022 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@@ -28,6 +28,7 @@
--
-- Synthesized:
-- Date Rev viv Target flop lutl lutm bram slic
-- 2022-12-27 1339 2022.1 xc7a35t-1 3454 6026 279 50.0 2013
-- 2022-12-06 1324 2022.1 xc7a35t-1 3447 5998 278 50.0 1992
-- 2022-07-05 1247 2022.1 xc7a35t-1 3411 6189 279 50.0 2021
-- 2019-05-19 1150 2017.2 xc7a35t-1 3369 6994 285 50.0 2099 +dz11

12
rtl/sys_gen/w11a/cmoda7/sys_w11a_c7.vmfset
View File

@@ -1,8 +1,8 @@
# $Id: sys_w11a_c7.vmfset 1325 2022-12-07 11:52:36Z mueller $
# $Id: sys_w11a_c7.vmfset 1338 2022-12-26 18:00:37Z mueller $
#
# Validated code/tool version combinations
# Date rev viv
# 2022-05-26 1242 2022.1
# 2022-12-26 1338 2022.1
# 2022-04-23 1225 2020.1
# 2019-06-05 1159 2019.1
# 2019-02-02 1108 2018.3
@@ -53,7 +53,7 @@ i [Synth 8-3331] pdp11_lunit .* CCIN[(1|2)]
# --> some psr bits are unused # OK 2018-11-18
i [Synth 8-3331] pdp11_psr .* DIN[(8|9|10)]
# --> not all moni fields used # OK 2018-11-18
i [Synth 8-3331] pdp11_mmu_ssr12 .* MONI[(idone|trace_prev)]
i [Synth 8-3331] pdp11_mmu_mmr12 .* MONI[(vflow|trace_prev)]
# --> not all CNTL fieds used; also 6 LSBs from vaddr # OK 2018-11-18
i [Synth 8-3331] pdp11_mmu .* VADDR[(0|1|2|3|4|5)]
# --> so far no usage of usec and msec pulse # OK 2018-11-18
@@ -84,10 +84,8 @@ i [Synth 8-7129] IREG[1(1|2|3|4)] .* pdp11_sequencer
i [Synth 8-7129] CCIN[(1|2)] .* pdp11_lunit
# --> some psr bits are unused # OK 2022-05-26
i [Synth 8-7129] DIN[(8|9|10)] .* pdp11_psr
# --> not all moni fields used # OK 2022-05-26
i [Synth 8-7129] MONI[(idone|trace_prev)] .* pdp11_mmu_ssr12
# --> not all CNTL fieds used; also 6 LSBs from vaddr # OK 2022-05-26
i [Synth 8-7129] VADDR[(0|1|2|3|4|5)] .* pdp11_mmu
# --> not all moni fields used # OK 2022-12-26
i [Synth 8-7129] MONI[(vflow|trace_prev)] .* pdp11_mmu_mmr12
# --> so far no usage of usec and msec pulse # OK 2022-05-26
i [Synth 8-7129] (CE_USEC|CE_MSEC) .* rlink_sp2c
# --> small memory, not all addr lines connected # OK 2022-05-26

7
rtl/sys_gen/w11a/nexys2/sys_w11a_n2.imfset
View File

@@ -1,4 +1,4 @@
# $Id: sys_w11a_n2.imfset 1150 2019-05-19 17:52:54Z mueller $
# $Id: sys_w11a_n2.imfset 1339 2022-12-27 12:11:34Z mueller $
#
# ----------------------------------------------------------------------------
[xst]
@@ -46,12 +46,10 @@ Input <RLB_MONI\..*> is never used
Input <CCIN<2:1>> is never used
Input <EI_ACK> is never used
Input <IREG<\d*:\d*>> is never used
Input <MONI.idone> is never used
Input <MONI.vflow> is never used
Input <MONI.trace_prev> is never used
Input <DIN<\d*:\d*>> is never used
Input <I_MEM_WAIT> is never used
Input <CNTL.trap_done> is never used
Input <VADDR<\d*:\d*>> is never used
Input <CE_USEC> is never used
Signal <TXSIZE_FX2> is assigned but never used
@@ -101,7 +99,6 @@ FF/Latch <SYS70/W11A/SEQ/R_STATUS.intvect_8> has a constant value of 0
FF/Latch <CRAMCTL/IOB_MEM_ADDRH/R_DO_21> has a constant value of 0
FF/Latch <CRAMCTL/IOB_MEM_ADDRH/R_DO_20> has a constant value of 0
FF/Latch <CRAMCTL/R_REGS.cntdly_2> has a constant value of 0
FF/Latch <R_SSR0.inst_compl> has a constant value of 0
FF/Latch <RLINK/CORE/RL/R_LREGS\.attn_.*> has a constant value of 0
FF/Latch <SYS70/DMPCNT.I0/R_REGS\.psig_\d*> has a constant value of 0
FF/Latch <SYS70/DMPCNT.I0/PRE\[\d*\]\.ENA.CNT/R_CNT_\d*> has a constant value

6
rtl/sys_gen/w11a/nexys3/sys_w11a_n3.imfset
View File

@@ -1,4 +1,4 @@
# $Id: sys_w11a_n3.imfset 1150 2019-05-19 17:52:54Z mueller $
# $Id: sys_w11a_n3.imfset 1339 2022-12-27 12:11:34Z mueller $
#
# ----------------------------------------------------------------------------
[xst]
@@ -55,12 +55,10 @@ Input <DM_STAT_.*> is never used
Input <CCIN<2:1>> is never used
Input <EI_ACK> is never used
Input <IREG<\d*:\d*>> is never used
Input <MONI.idone> is never used
Input <MONI.vflow> is never used
Input <MONI.trace_prev> is never used
Input <DIN<\d*:\d*>> is never used
Input <I_MEM_WAIT> is never used
Input <CNTL.trap_done> is never used
Input <VADDR<\d*:\d*>> is never used
Input <CE_USEC> is never used
FF/Latch <R_STATUS.suspext> has a constant value of 0

12
rtl/sys_gen/w11a/nexys4/sys_w11a_n4.vmfset
View File

@@ -1,8 +1,8 @@
# $Id: sys_w11a_n4.vmfset 1325 2022-12-07 11:52:36Z mueller $
# $Id: sys_w11a_n4.vmfset 1338 2022-12-26 18:00:37Z mueller $
#
# Validated code/tool version combinations
# Date rev viv
# 2022-05-26 1242 2022.1
# 2022-12-26 1338 2022.1
# 2019-06-05 1159 2019.1
# 2019-02-02 1108 2018.3
# 2019-02-02 1108 2017.2
@@ -46,7 +46,7 @@ i [Synth 8-3331] pdp11_lunit .* CCIN[(1|2)]
# --> some psr bits are unused # OK 2018-11-18
i [Synth 8-3331] pdp11_psr .* DIN[(8|9|10)]
# --> not all moni fields used # OK 2018-11-18
i [Synth 8-3331] pdp11_mmu_ssr12 .* MONI[(idone|trace_prev)]
i [Synth 8-3331] pdp11_mmu_mmr12 .* MONI[(vflow|trace_prev)]
# --> not all CNTL fieds used; also 6 LSBs from vaddr # OK 2018-11-18
i [Synth 8-3331] pdp11_mmu .* VADDR[(0|1|2|3|4|5)]
# --> so far no usage of usec and msec pulse # OK 2018-11-18
@@ -74,10 +74,8 @@ i [Synth 8-7129] IREG[1(1|2|3|4)] .* pdp11_sequencer
i [Synth 8-7129] CCIN[(1|2)] .* pdp11_lunit
# --> some psr bits are unused # OK 2022-05-26
i [Synth 8-7129] DIN[(8|9|10)] .* pdp11_psr
# --> not all moni fields used # OK 2022-05-26
i [Synth 8-7129] MONI[(idone|trace_prev)] .* pdp11_mmu_ssr12
# --> not all CNTL fieds used; also 6 LSBs from vaddr # OK 2022-05-26
i [Synth 8-7129] VADDR[(0|1|2|3|4|5)] .* pdp11_mmu
# --> not all moni fields used # OK 2022-12-26
i [Synth 8-7129] MONI[(vflow|trace_prev)] .* pdp11_mmu_mmr12
# --> so far no usage of usec and msec pulse # OK 2022-05-26
i [Synth 8-7129] (CE_USEC|CE_MSEC) .* rlink_sp2c
# --> msec indeed not used # OK 2022-05-26

12
rtl/sys_gen/w11a/nexys4d/sys_w11a_n4d.vmfset
View File

@@ -1,8 +1,8 @@
# $Id: sys_w11a_n4d.vmfset 1325 2022-12-07 11:52:36Z mueller $
# $Id: sys_w11a_n4d.vmfset 1338 2022-12-26 18:00:37Z mueller $
#
# Validated code/tool version combinations
# Date rev viv
# 2022-05-26 1242 2022.1
# 2022-12-26 1338 2022.1
# 2022-04-23 1225 2020.1
# 2019-06-05 1159 2019.1
# 2019-02-02 1108 2018.3
@@ -47,7 +47,7 @@ i [Synth 8-3331] pdp11_lunit .* CCIN[(1|2)]
# --> some psr bits are unused # OK 2019-01-02
i [Synth 8-3331] pdp11_psr .* DIN[(8|9|10)]
# --> not all moni fields used # OK 2019-01-02
i [Synth 8-3331] pdp11_mmu_ssr12 .* MONI[(idone|trace_prev)]
i [Synth 8-3331] pdp11_mmu_mmr12 .* MONI[(vflow|trace_prev)]
# --> not all CNTL fieds used; also 6 LSBs from vaddr # OK 2019-01-02
i [Synth 8-3331] pdp11_mmu .* VADDR[(0|1|2|3|4|5)]
# --> so far no usage of usec and msec pulse # OK 2019-01-02
@@ -76,10 +76,8 @@ i [Synth 8-7129] IREG[1(1|2|3|4)] .* pdp11_sequencer
i [Synth 8-7129] CCIN[(1|2)] .* pdp11_lunit
# --> some psr bits are unused # OK 2022-05-26
i [Synth 8-7129] DIN[(8|9|10)] .* pdp11_psr
# --> not all moni fields used # OK 2022-05-26
i [Synth 8-7129] MONI[(idone|trace_prev)] .* pdp11_mmu_ssr12
# --> not all CNTL fieds used; also 6 LSBs from vaddr # OK 2022-05-26
i [Synth 8-7129] VADDR[(0|1|2|3|4|5)] .* pdp11_mmu
# --> not all moni fields used # OK 2022-12-26
i [Synth 8-7129] MONI[(vflow|trace_prev)] .* pdp11_mmu_mmr12
# --> so far no usage of usec and msec pulse # OK 2022-05-26
i [Synth 8-7129] (CE_USEC|CE_MSEC) .* rlink_sp2c
# --> msec indeed not used # OK 2022-05-26

16
rtl/sys_gen/w11a/nexys4d_bram/sys_w11a_br_n4d.vmfset
View File

@@ -1,8 +1,8 @@
# $Id: sys_w11a_br_n4d.vmfset 1325 2022-12-07 11:52:36Z mueller $
# $Id: sys_w11a_br_n4d.vmfset 1338 2022-12-26 18:00:37Z mueller $
#
# Validated code/tool version combinations
# Date rev viv
# 2022-05-26 1242 2022.1
# 2022-12-26 1338 2022.1
#
# ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
[syn]
@@ -41,7 +41,7 @@ i [Synth 8-3331] pdp11_lunit .* CCIN[(1|2)]
# --> some psr bits are unused # OK 2018-11-18
i [Synth 8-3331] pdp11_psr .* DIN[(8|9|10)]
# --> not all moni fields used # OK 2018-11-18
i [Synth 8-3331] pdp11_mmu_ssr12 .* MONI[(idone|trace_prev)]
i [Synth 8-3331] pdp11_mmu_mmr12 .* MONI[(vflow|trace_prev)]
# --> not all CNTL fieds used; also 6 LSBs from vaddr # OK 2018-11-18
i [Synth 8-3331] pdp11_mmu .* VADDR[(0|1|2|3|4|5)]
# --> so far no usage of usec and msec pulse # OK 2018-11-18
@@ -70,10 +70,8 @@ i [Synth 8-7129] IREG[1(1|2|3|4)] .* pdp11_sequencer
i [Synth 8-7129] CCIN[(1|2)] .* pdp11_lunit
# --> some psr bits are unused # OK 2022-05-26
i [Synth 8-7129] DIN[(8|9|10)] .* pdp11_psr
# --> not all moni fields used # OK 2022-05-26
i [Synth 8-7129] MONI[(idone|trace_prev)] .* pdp11_mmu_ssr12
# --> not all CNTL fieds used; also 6 LSBs from vaddr # OK 2022-05-26
i [Synth 8-7129] VADDR[(0|1|2|3|4|5)] .* pdp11_mmu
# --> not all moni fields used # OK 2022-12-26
i [Synth 8-7129] MONI[(vflow|trace_prev)] .* pdp11_mmu_mmr12
# --> so far no usage of usec and msec pulse # OK 2022-05-26
i [Synth 8-7129] (CE_USEC|CE_MSEC) .* rlink_sp2c
# --> only small memory available # OK 2022-05-26
@@ -85,6 +83,10 @@ i [Synth 8-7129] EI_ACK .* ibdr_deuna
i [Synth 8-7129] EI_ACK .* ibd_iist
{:}
# port driven by constant --------------------------------------
# --> RGBLED0 currently unused # OK 2022-12-26
i [Synth 8-3917] O_RGBLED0[\d]
# sequential element removed (2017.1 nonsense) -----------------
I [Synth 8-6014] _reg # generic

22
rtl/sys_gen/w11a/s3board/sys_w11a_s3.imfset
View File

@@ -1,4 +1,4 @@
# $Id: sys_w11a_s3.imfset 1150 2019-05-19 17:52:54Z mueller $
# $Id: sys_w11a_s3.imfset 1339 2022-12-27 12:11:34Z mueller $
#
# ----------------------------------------------------------------------------
[xst]
@@ -34,13 +34,10 @@ Input <IB_MREQ\..*> is never used
Input <SER_MONI\..*> is never used
Input <CCIN<2:1>> is never used
Input <EI_ACK> is never used
Input <IREG<\d*:\d*>> is never used
Input <MONI.idone> is never used
Input <MONI.vflow> is never used
Input <MONI.trace_prev> is never used
Input <DIN<\d*:\d*>> is never used
Input <CNTL.trap_done> is never used
Input <VADDR<\d*:\d*>> is never used
Input <CE_USEC> is never used
Signal <RXFIFO_SIZE<2:0>> is assigned but never used
@@ -72,6 +69,20 @@ Signal <IB_SRES_IIST\..*> is used but never assigned
Signal <EI_REQ_IIST> is used but never assigned
Signal <EI_ACK_IIST> is assigned but never used
# signals for de-configured entities
Signal <DM_STAT_VM\..*> is assigned but never used
Signal <RB_SRES_DMCMON\..*> is used but never assigned
Signal <RB_SRES_DMHBPT\..*> is used but never assigned
Signal <IB_SRES_M9312\..*> is used but never assigned
Signal <IB_SRES_KW11P\..*> is used but never assigned
Signal <IB_SRES_DEUNA\..*> is used but never assigned
Signal <RB_LAM_DEUNA> is used but never assigned
Signal <EI_REQ_KW11P> is used but never assigned
Signal <EI_REQ_DEUNA> is used but never assigned
Signal <EI_ACK_KW11P> is assigned but never used
Signal <EI_ACK_DEUNA> is assigned but never used
Signal <HPBT> is used but never assigned
FF/Latch <R_REGS.escseen> has a constant value of 0
FF/Latch <R_REGS.escpend> has a constant value of 0
FF/Latch <R_STATUS.suspext> has a constant value of 0
@@ -79,7 +90,6 @@ FF/Latch <R_REGS.dtyp_3> has a constant value of 0
FF/Latch <SYS70/W11A/SEQ/R_IDSTAT.res_sel_2> has a constant value of 0
FF/Latch <SYS70/W11A/SEQ/R_STATUS.intvect_8> has a constant value of 0
FF/Latch <R_SSR0.inst_compl> has a constant value of 0
FF/Latch <RLINK/CORE/RL/R_LREGS\.attn_.*> has a constant value of 0
FF/Latch <SYS70/DMPCNT.I0/R_REGS\.psig_\d*> has a constant value of 0
FF/Latch <SYS70/DMPCNT.I0/PRE\[\d*\]\.ENA.CNT/R_CNT_\d*> has a constant value

5
rtl/w11a/pdp11.vhd
View File

@@ -1,4 +1,4 @@
-- $Id: pdp11.vhd 1330 2022-12-16 17:52:40Z mueller $
-- $Id: pdp11.vhd 1339 2022-12-27 12:11:34Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2006-2022 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@@ -11,6 +11,7 @@
--
-- Revision History:
-- Date Rev Version Comment
-- 2022-12-27 1339 1.5.22 _sequencer: rm PC port; _dpath: rm PCOUT port
-- 2022-12-12 1330 1.5.21 dm_stat_se_type: rename vfetch -> vstart;
-- mmu_moni_type: drop pc,idone, add vstart,vflow
-- pdp11_mmu_mmr12: add VADDR port
@@ -1022,7 +1023,6 @@ component pdp11_dpath is -- CPU datapath
CP_DIN : in slv16; -- console port data in
CP_DOUT : out slv16; -- console port data out
PSWOUT : out psw_type; -- current psw
PCOUT : out slv16; -- current pc
IREG : out slv16; -- ireg out
VM_ADDR : out slv16; -- virt. memory address
VM_DOUT : in slv16; -- virt. memory data out
@@ -1045,7 +1045,6 @@ component pdp11_sequencer is -- cpu sequencer
CLK : in slbit; -- clock
GRESET : in slbit; -- general reset
PSW : in psw_type; -- processor status
PC : in slv16; -- program counter
IREG : in slv16; -- IREG
ID_STAT : in decode_stat_type; -- instr. decoder status
DP_STAT : in dpath_stat_type; -- data path status

10
rtl/w11a/pdp11_core.vhd
View File

@@ -1,6 +1,6 @@
-- $Id: pdp11_core.vhd 1181 2019-07-08 17:00:50Z mueller $
-- $Id: pdp11_core.vhd 1339 2022-12-27 12:11:34Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2006-2018 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2006-2022 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
------------------------------------------------------------------------------
-- Module Name: pdp11_core - syn
@@ -18,9 +18,10 @@
-- tb/tb_rlink_tba_pdp11core
--
-- Target Devices: generic
-- Tool versions: ise 8.2-14.7; viv 2014.4-2018.2; ghdl 0.18-0.34
-- Tool versions: ise 8.2-14.7; viv 2014.4-2022.1; ghdl 0.18-2.0.0
-- Revision History:
-- Date Rev Version Comment
-- 2022-12-27 1339 1.4.5 _sequencer: rm PC port; _dpath: rm PCOUT port
-- 2018-10-07 1054 1.4.4 drop ITIMER, now routed via DM_STAT_SE.itimer
-- 2016-10-03 812 1.4.3 drop SNUM signal, not used anymore
-- 2015-07-19 702 1.4.2 add DM_STAT_SE port; re-arrange DM_STAT_CO usage
@@ -97,7 +98,6 @@ architecture syn of pdp11_core is
signal DP_CNTL : dpath_cntl_type := dpath_cntl_init;
signal DP_STAT : dpath_stat_type := dpath_stat_init;
signal DP_PSW : psw_type := psw_init;
signal DP_PC : slv16 := (others=>'0');
signal DP_IREG : slv16 := (others=>'0');
signal VM_DIN : slv16 := (others=>'0');
signal VM_ADDR : slv16 := (others=>'0');
@@ -150,7 +150,6 @@ begin
CP_DIN => CP_DIN,
CP_DOUT => CP_DOUT,
PSWOUT => DP_PSW,
PCOUT => DP_PC,
IREG => DP_IREG,
VM_ADDR => VM_ADDR,
VM_DOUT => VM_DOUT,
@@ -171,7 +170,6 @@ begin
CLK => CLK,
GRESET => GRESET,
PSW => DP_PSW,
PC => DP_PC,
IREG => DP_IREG,
ID_STAT => ID_STAT,
DP_STAT => DP_STAT,

5
rtl/w11a/pdp11_dpath.vhd
View File

@@ -1,4 +1,4 @@
-- $Id: pdp11_dpath.vhd 1310 2022-10-27 16:15:50Z mueller $
-- $Id: pdp11_dpath.vhd 1339 2022-12-27 12:11:34Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2006-2022 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@@ -19,6 +19,7 @@
--
-- Revision History:
-- Date Rev Version Comment
-- 2022-12-27 1339 1.2.7 remove PCOUT port
-- 2022-10-25 1309 1.2.6 rename _gpr -> _gr
-- 2015-07-19 702 1.2.5 set new DM_STAT_DP fields
-- 2014-08-10 581 1.2.4 use c_cc_f_*
@@ -58,7 +59,6 @@ entity pdp11_dpath is -- CPU datapath
CP_DIN : in slv16; -- console port data in
CP_DOUT : out slv16; -- console port data out
PSWOUT : out psw_type; -- current psw
PCOUT : out slv16; -- current pc
IREG : out slv16; -- ireg out
VM_ADDR : out slv16; -- virt. memory address
VM_DOUT : in slv16; -- virt. memory data out
@@ -317,7 +317,6 @@ begin
STAT.ccout_z <= CCOUT(c_cc_f_z); -- current Z cc flag
PSWOUT <= PSW;
PCOUT <= GR_PC;
IREG <= R_IREG;
VM_DIN <= DRES;
CP_DOUT <= R_CPDOUT;

6
rtl/w11a/pdp11_sequencer.vhd
View File

@@ -1,4 +1,4 @@
-- $Id: pdp11_sequencer.vhd 1337 2022-12-26 11:14:21Z mueller $
-- $Id: pdp11_sequencer.vhd 1338 2022-12-26 18:00:37Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2006-2022 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@@ -13,6 +13,7 @@
--
-- Revision History:
-- Date Rev Version Comment
-- 2022-12-27 1339 1.6.27 remove PC port
-- 2022-12-26 1337 1.6.26 tbit logic overhaul 2, now fully 11/70 compatible
-- 2022-12-12 1330 1.6.25 implement MMR0,MMR2 instruction complete
-- 2022-12-10 1329 1.6.24 BUGFIX: get correct PS after vector push abort
@@ -102,7 +103,6 @@ entity pdp11_sequencer is -- CPU sequencer
CLK : in slbit; -- clock
GRESET : in slbit; -- general reset
PSW : in psw_type; -- processor status
PC : in slv16; -- program counter
IREG : in slv16; -- IREG
ID_STAT : in decode_stat_type; -- instr. decoder status
DP_STAT : in dpath_stat_type; -- data path status
@@ -351,7 +351,7 @@ begin
end if;
end process proc_state;
proc_next: process (R_STATE, R_STATUS, PSW, PC, CP_CNTL,
proc_next: process (R_STATE, R_STATUS, PSW, CP_CNTL,
ID_STAT, R_IDSTAT, IREG, VM_STAT, DP_STAT,
R_CPUERR, R_VMSTAT, IB_MREQ, IBSEL_CPUERR,
INT_PRI, INT_VECT, ESUSP_I, HBPT)

40
tools/tcode/cpu_mmu.mac
View File

@@ -1,4 +1,4 @@
; $Id: cpu_mmu.mac 1337 2022-12-26 11:14:21Z mueller $
; $Id: cpu_mmu.mac 1339 2022-12-27 12:11:34Z mueller $
; SPDX-License-Identifier: GPL-3.0-or-later
; Copyright 2022- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
;
@@ -9,7 +9,7 @@
;
; Test CPU MMU: all aspects of the MMU
; Section A: pdr,par registers
; Section B: mmr0,mmr3 registers, mapping, instructions
; Section B: mmr0,mmr3 registers, mapping, instructions; MTP* and MFP*
; Section C: mmr2+mmr1+mmr0 register, aborts
; Section D: mmr2+mmr1+mmr0 register, abort recovery
; Section E: traps and pdr aia and aiw bits
@@ -231,7 +231,14 @@ ta0102:
; B2.2 test variable kernel mode mapping
; B3 user and supervisor mode
; B3.1 run code in user/supervisor mode
; B3.2 run code in user mode with D space enabled
; B3.2 run code in user mode with D space; MFP*, MTP*
; part 1: run code vc1 in user mode
; part 2: test MTPD and MFPD
; part 3: test MTPI and MFPI
; part 4: test MTPD,MFPD with @(sp)+
; part 5: test MTPI,MFPI with @(sp)+
; part 6: test MFPD,MFPI and MTPD,MTPI for sp register access
; part 7: test MFPD,MFPI and MTPD,MTPI for register r0-r5 access
; B4 invalid cpu mode 10
; B4.1 check that cmode=10 causes abort
; B4.2 check MFPI/MTPI SP response for pmode=10
@@ -460,7 +467,7 @@ tb0301:
;
9999$: iot ; end of test B3.1
;
; Test B3.2 -- run code in user mode with D space enabled ++++++++++++
; Test B3.2 -- run code in user mode with D space; mfp*, mtp* ++++++++
; code vc1 is executed in user and in supervisor mode
; the code runs in seg0 with D space enabled
;
@@ -479,7 +486,7 @@ tb0302:
mov #m3.dum,mmr3 ; user d dspace, no 22bit
mov #m0.ena,mmr0 ; enable mmu ;! MMU 18
;
; run code vc1 in user mode --------------------------------
; part 1: run code vc1 in user mode ----------------------------------
;
; set user mode pdr/par, only short page 0; I and D
mov #<8.*md.plf>!md.arw,uipdr0
@@ -506,6 +513,8 @@ tb0302:
;
; psw has now pm=user and cm=kernel; good setup to test MFPI and friends
;
; part 2: test MTPD and MFPD -----------------------------------------
;
; test MFPD (data access)
;
mov #<vc1v0-vc1dat>,r5 ; initialize data pointer
@@ -530,6 +539,8 @@ tb0302:
cmp r4,r3 ; more to do ?
blo 2000$
;
; part 3: test MTPI and MFPI -----------------------------------------
;
; test MFPI (data access)
;
mov #<vc1-vc1>,r5 ; initialize data pointer
@@ -553,9 +564,9 @@ tb0302:
cmp r4,r3 ; more to do ?
blo 3000$
;
; Test MTPD,MFPD with @(sp)+
; Note: (sp)+ is not a useful address mode for MTPD
; It will use the cm sp as address in pm.
; part 4: test MTPD,MFPD with @(sp)+ ---------------------------------
; Note: (sp) or (sp)+ are not a useful address mode for MTPD
; It will use the cm sp as address in pm, rarely what one wants
; So @(sp)+ is the only mode with sp in src worth to be tested
;
clr vc1v0
@@ -568,7 +579,7 @@ tb0302:
mfpd @(sp)+
hcmpeq (sp)+,#054322 ; check
;
; Test MTPI,MFPI with @(sp)+
; part 5: test MTPI,MFPI with @(sp)+ ---------------------------------
;
clr vc1ida
push #<vc1ida-vc1> ; I addr of vc1ida
@@ -580,7 +591,8 @@ tb0302:
mfpi @(sp)+
hcmpeq (sp)+,#012322 ; check
;
; Test MFPD,MFPI and MTPD,MTPI for sp register access
;
; part 6: test MFPD,MFPI and MTPD,MTPI for sp register access --------
; accessing sp will access user mode stack pointer (which is != kernel stack)
;
; read sp via mfpd and mfpi
@@ -604,7 +616,7 @@ tb0302:
mfpd sp ; read back user stack
hcmpeq (sp)+,r5 ; check
;
; Test MFPD,MFPI and MTPD,MTPI for register r0-r5 access
; part 7: test MFPD,MFPI and MTPD,MTPI for register r0-r5 access -----
; accessing r0-r5 simply acccesses common registers
; that is usually not used, but should work
;
@@ -736,6 +748,8 @@ tb0402: tstb systyp ; skip if not on w11
; part 1: JSR, MFPI, MFPD (push)
; part 2: RTS, MTPI, MTPD (pop)
; C2.4 mmu abort vs nxm abort
; part 1: MMU allows access to NXM memory --> NXM abort
; part 2: MMU denies access to NXM memory --> MMU abort
; C2.5 mmu abort in vector flow - kernel mode
; C2.6 mmu abort in vector flow - supervisor mode
; C2.7 mmu abort in 1st instruction after vector flow
@@ -1341,7 +1355,7 @@ tc0204: mov cp.los,kipar6 ; map begin of non-existent memory
mov #m3.e22,mmr3 ; enable 22-bit mode
mov #m0.ena,mmr0 ; enable mmu with traps ;! MMU 22
;
; part1: MMU allows access to NXM memory --> NXM abort ---------------
; part 1: MMU allows access to NXM memory --> NXM abort --------------
;
1000$: clr cp.err ; clear CPUERR
mov #1100$,v..iit ; set vector 4 handler for NXM abort
@@ -1351,7 +1365,7 @@ tc0204: mov cp.los,kipar6 ; map begin of non-existent memory
hcmpeq cp.err,#cp.nxm ; NXM error seen
mov #v..iit+2,v..iit ; restore iit handler to catcher
;
; part2: MMU denies access to NXM memory --> MMU abort ---------------
; part 2: MMU denies access to NXM memory --> MMU abort --------------
;
2000$: mov #<127.*md.plf>!md.an7,kipdr6 ; deny access via acf=7
clr cp.err ; clear CPUERR