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cpu_mmu: add C2.2 and C2.3 tests
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wfjm
@@ -1,4 +1,4 @@
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# $Id: tb_pdp11core_stim.dat 1280 2022-08-15 09:12:03Z mueller $
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# $Id: tb_pdp11core_stim.dat 1289 2022-08-29 12:31:04Z mueller $
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# SPDX-License-Identifier: GPL-3.0-or-later
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# Copyright 2007-2022 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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#
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@@ -1,4 +1,4 @@
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; $Id: defs_mmu.mac 1289 2022-08-29 12:31:04Z mueller $
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; $Id: defs_mmu.mac 1291 2022-09-03 07:00:27Z mueller $
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; SPDX-License-Identifier: GPL-3.0-or-later
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; Copyright 2015-2022 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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;
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@@ -33,7 +33,7 @@
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m0.ico = 000200 ; instruction complete flag
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m0.pmu = 000140 ; page mode user
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m0.pms = 000040 ; page mode supervisor
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m0.dsp = 000020 ; enable i/d space
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m0.dsp = 000020 ; page d space
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m0.pno = 000002 ; page number field lsb
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m0.ena = 000001 ; enable mmu
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;
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@@ -1,11 +1,10 @@
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; $Id: cpu_mmu.mac 1290 2022-08-30 06:20:40Z mueller $
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; $Id: cpu_mmu.mac 1291 2022-09-03 07:00:27Z mueller $
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; SPDX-License-Identifier: GPL-3.0-or-later
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; Copyright 2022- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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;
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; Revision History:
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; Date Rev Version Comment
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; 2022-08-06 1272 1.0.1 ssr->mmr rename
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; 2022-07-28 1264 1.0 Initial version
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; 2022-08-31 1291 1.0 Initial version
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; 2022-07-24 1262 0.1 First draft
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;
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; Test CPU MMU: all aspects of the MMU
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@@ -887,6 +886,268 @@ tc0201: mov #vhemmu,v..mmu
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clr v..mmu+2
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9999$: iot ; end of test C2.1
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;
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; Test C2.2 -- test MFPI,MFPD,MTPI,MFPD dst aborts +++++++++++++++++++
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; Environment: psw pm=user; mmr3 user I/D
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; kipdr6 1 click up acf=6 w/r
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; uipdr0 1 click up acf=2 read
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; udpdr1 1 click up acr=2 read
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; udpdr2 1 click dn acr=6 w/r
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;
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tc0202: mov #vhemmu,v..mmu
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clr v..mmu+2 ; pr0 kernel
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reset
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mov #cp.pmu,cp.psw ; pm to user
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mov #m3.dum,mmr3 ; enable user D space
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mov #<0.*md.plf>!md.arw,kipdr6 ; plf= 0.;ed=0;acf=w/r
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mov #<0.*md.plf>!md.aro,uipdr0 ; plf= 0.;ed=0;acf=r
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mov #<0.*md.plf>!md.aro,udpdr1 ; plf= 0.;ed=0;acf=r
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mov #<127.*md.plf>!md.dwn!md.arw,udpdr2 ; plf=127.;ed=1;acf=w/r
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mov #m0.ena,mmr0 ; enable mmu ;! MMU 18
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;
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; part 1: -- MFPI, MFPD ----------------------------------------------
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; Summary:
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; 1000$: mfpi (r2)+ ; r ; dst anr 1 ; pdr= 0.,0,000
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; 1100$: mfpi (r3)+ ; r ; dst ale 1 ; pdr= 0.,0,aro
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; 1200$: mfpi @(r4)+ ; r ; dst ale 1 ; pdr= 0.,0,arw
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; 1300$: mfpi @(r5)+ ; r ; dst ale 2 ; pdr= 0.,0,aro
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; 1400$: mfpd -(r3) ; r ; dst ale 1 ; pdr=127.,1,arw
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;
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; MPPI: I space page 1 non-resident
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1000$: mov #1010$,vhvmmu
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mov #020000,r2
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mfpi (r2)+ ; will fail, page 1 unmapped
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halt
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1010$: .word m0.anr!m0.pmu!<1*m0.pno>!m0.ena ; mmr0
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; dddddrrrdddddrrr
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.word ^b0000000000010010 ; mmr1 +2,2
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;
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; MFPI: I space page 0 length abort
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1100$: mov #1110$,vhvmmu
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mov #000102,r3
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mfpi (r3)+ ; will fail
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halt
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1110$: .word m0.ale!m0.pmu!<0*m0.pno>!m0.ena ; mmr0
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; dddddrrrdddddrrr
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.word ^b0000000000010011 ; mmr1 +2,3
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;
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; MFPI @(R)+: 1st access fails (in kernel space)
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1200$: mov #cp.pmu,cp.psw ; pm to user
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mov #1210$,vhvmmu
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mov #140102,r4
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mfpi @(r4)+ ; will fail
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halt
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1210$: .word m0.ale!<6*m0.pno>!m0.ena ; mmr0 -> p6 k
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; dddddrrrdddddrrr
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.word ^b0000000000010100 ; mmr1 +2,4
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;
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; MFPI @(R)+: 2nd access fails (in user space)
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1300$: mov #cp.pmu,cp.psw ; pm to user
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mov #1310$,vhvmmu
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mov #1301$,r5
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mfpi @(r5)+ ; will fail
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halt
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1301$: .word 000104 ; probed address
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1310$: .word m0.ale!m0.pmu!<0*m0.pno>!m0.ena ; mmr0 -> p0 u
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; dddddrrrdddddrrr
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.word ^b0000000000010101 ; mmr1 +2,5
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;
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; MFPD: D space page 1 length abort (has ed=1)
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1400$: mov #cp.pmu,cp.psw ; pm to user
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mov #1410$,vhvmmu
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mov #037700,r3
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mfpd -(r3) ; will fail
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halt
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1410$: .word m0.ale!m0.pmu!m0.dsp!<1*m0.pno>!m0.ena ; mmr0
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; dddddrrrdddddrrr
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.word ^b0000000011110011 ; mmr1 -2,3
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;
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; part 2: -- MTPD, MTPI ----------------------------------------------
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; Note: mmr1 lsb has stack pop
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; Summary:
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; 2000$: mtpd (r2)+ ; r ; dst anr 1 ; pdr= 0.,0,000
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; 2100$: mtpd (r3)+ ; r ; dst ard 1 ; pdr= 0.,0,aro
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; 2200$: mtpd -(r4) ; r ; dst ale 1 ; pdr=127.,1,arw
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; 2300$: mtpd @(R5)+ ; r ; dst ale 1 ; pdr= 0.,0,arw
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; 2400$: mtpd @(R3)+ ; r ; dst ale 2 ; pdr=127.,1,arw
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; 2500$: mtpi (r2)+ ; r ; dst ard 1 ; pdr= 0.,0,aro
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;
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; MTPD: D space page 3 non-resident
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2000$: mov #cp.pmu,cp.psw ; pm to user
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mov #2010$,vhvmmu
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mov #060000,r2
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push #1234
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mtpd (r2)+ ; will fail, page 3 unmapped
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halt
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2010$: .word m0.anr!m0.pmu!m0.dsp!<3*m0.pno>!m0.ena ; mmr0
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; dddddrrrdddddrrr
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.word ^b0001001000010110 ; mmr1 +2,2; +2,6
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;
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; MTPD: D space page 1 read-only
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2100$: mov #cp.pmu,cp.psw ; pm to user
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mov #2110$,vhvmmu
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mov #020002,r3
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push #1234
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mtpd (r3)+ ; will fail
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halt
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2110$: .word m0.ard!m0.pmu!m0.dsp!<1*m0.pno>!m0.ena ; mmr0
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; dddddrrrdddddrrr
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.word ^b0001001100010110 ; mmr1 +2,3; +2,6
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;
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; MTPD: D space page 2 length
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2200$: mov #2210$,vhvmmu
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mov #057700,r4
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push #1234
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mtpd -(r4) ; will fail
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halt
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2210$: .word m0.ale!m0.pmu!m0.dsp!<2*m0.pno>!m0.ena ; mmr0
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; dddddrrrdddddrrr
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.word ^b1111010000010110 ; mmr1 -2,4; +2,6
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;
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; MTPD @(R)+: 1st access fails (in kernel space)
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2300$: mov #2310$,vhvmmu
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mov #140102,r5
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push #1234
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mtpd @(r5)+ ; will fail
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halt
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2310$: .word m0.ale!<6*m0.pno>!m0.ena ; mmr0
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; dddddrrrdddddrrr
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.word ^b0001010100010110 ; mmr1 +2,5; +2,6
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;
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; MTPD @(R)+: 2nd access fails (in user space)
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2400$: mov #2410$,vhvmmu
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mov #2401$,r3
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push #1234
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mtpd @(r3)+ ; will fail
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halt
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2401$: .word 057600 ; probed address
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2410$: .word m0.ale!m0.pmu!m0.dsp!<2*m0.pno>!m0.ena ; mmr0
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; dddddrrrdddddrrr
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.word ^b0001001100010110 ; mmr1 +2,3; +2,6
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;
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; MTPI: I space page 0 read-only
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2500$: mov #cp.pmu,cp.psw ; pm to user
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mov #2510$,vhvmmu
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mov #000020,r2
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push #1234
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mtpi (r2)+ ; will fail
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halt
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2510$: .word m0.ard!m0.pmu!<0*m0.pno>!m0.ena ; mmr0
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; dddddrrrdddddrrr
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.word ^b0001001000010110 ; mmr1 +2,2; +2,6
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;
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9000$: reset ; mmu off ;! MMU off
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clr cp.psw
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mov #<127.*md.plf>!md.arw,kipdr6 ; restore kernel mapping
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clr uipdr0 ; reset user mode pdr
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clr udpdr1
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clr udpdr2
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mov #v..mmu+2,v..mmu ; restore mmu catcher
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clr v..mmu+2
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9999$: iot ; end of test C2.2
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;
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; Test C2.3 -- test aborts in implied push/pop; ++++++++++++++++++++++
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; jsr,mfp* have an implied push; rts,mft* have an implied pop
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; This must be tested in supervisor mode to separate 'stack under test'
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; from the kernel stack used in MMU 250 vector handling
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; Environment: psw cm=supervisor;pm=user
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; si.0 as 1-to-1 (easy switch between kernel and supervisor)
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; si.7 as 1-to-1 (psw access)
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; ui.0 as 1-to-1 (for read access)
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;
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tc0203: mov #vhemmu,v..mmu
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clr v..mmu+2 ; pr0 kernel
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reset
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mov kipdr0,sipdr0 ; super 0: 1-to-1
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clr sipar0
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mov kipdr7,sipdr7 ; super 7: 1-to-1
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mov kipar7,sipar7
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mov kipdr0,uipdr0 ; user 0: 1-to-1
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clr uipar0
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mov #m0.ena,mmr0 ; enable mmu ;! MMU 18
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mov #cp.cms!cp.pmu,cp.psw ; cm to supervisor, pm to user
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;
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; part 1: -- JSR, MFPI, MFPD (push) ----------------------------------
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; Execute implicit push against a non-resident page
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; Summary:
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; 1000$: jsr pc,(r2)
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; 1100$: mfpi (r2)
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; 1200$: mfpd (r2)
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;
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1000$: mov #020100,sp ; set SP into 1st click page 1, non-resident
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mov #1010$,vhvmmu
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mov #1001$,r2
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jsr pc,(r2) ; will fail
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1001$: halt
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1010$: .word m0.anr!m0.pms!<1*m0.pno>!m0.ena ; mmr0
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; dddddrrrdddddrrr
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.word ^b0000000011110110 ; mmr1 -2,6
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;
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1100$: mov #1110$,vhvmmu
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mov #swsyid,r2 ; any valid address
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mfpi (r2) ; will fail
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halt
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1110$: .word m0.anr!m0.pms!<1*m0.pno>!m0.ena ; mmr0
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; dddddrrrdddddrrr
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.word ^b0000000011110110 ; mmr1 -2,6
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;
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1200$: mov #1210$,vhvmmu
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mfpd (r2) ; will fail
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halt
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1210$: .word m0.anr!m0.pms!<1*m0.pno>!m0.ena ; mmr0
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; dddddrrrdddddrrr
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.word ^b0000000011110110 ; mmr1 -2,6
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;
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; part 2: -- RTS, MTPI, MTPD (pop) -----------------------------------
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; Execute implicit pop against a non-resident page
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; Summary:
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; 2000$: rts pc
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; 2100$: mtpi (r2)
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; 2200$: mtpd (r2)
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;
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; Simh doesnt update SP and set MMR1 on implicit pops
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; Modify expected mmr1 values in case SimH is detected
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cmpb systyp,#sy.sih
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bne 1999$
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clr 2010$+2 ; expect mmr1 = 0
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clr 2110$+2 ; expect mmr1 = 0
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clr 2210$+2 ; expect mmr1 = 0
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1999$:
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;
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2000$: mov #020040,sp ; set SP into 1st click page 1, non-resident
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mov #2010$,vhvmmu
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rts pc ; will fail
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halt
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2010$: .word m0.anr!m0.pms!<1*m0.pno>!m0.ena ; mmr0
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; dddddrrrdddddrrr
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.word ^b0000000000010110 ; mmr1 +2,6
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;
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2100$: mov #2110$,vhvmmu
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mov #1,r2 ; not used
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mtpi (r2) ; will fail
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halt
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2110$: .word m0.anr!m0.pms!<1*m0.pno>!m0.ena ; mmr0
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; dddddrrrdddddrrr
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.word ^b0000000000010110 ; mmr1 +2,6
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;
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2200$: mov #2210$,vhvmmu
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mov #1,r2 ; not used
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mtpd (r2) ; will fail
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halt
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2210$: .word m0.anr!m0.pms!<1*m0.pno>!m0.ena ; mmr0
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; dddddrrrdddddrrr
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.word ^b0000000000010110 ; mmr1 +2,6
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;
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9000$: clr cp.psw
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reset ; mmu off ;! MMU off
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clr sipdr0 ; reset super/user pdf
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clr sipdr7
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clr sipar7
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clr uipdr0
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mov #v..mmu+2,v..mmu ; restore mmu catcher
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clr v..mmu+2
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9999$: iot ; end of test C2.3
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;
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;
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; Section D: mmr2+mmr1+mmr0 register, abort recovery =========================
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;
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; Test D1: ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
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@@ -1024,7 +1285,7 @@ td0101:
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; END OF ALL TESTS - loop closure ============================================
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;
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mov tstno,r0 ; hack, for easy monitoring ...
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hcmpeq tstno,#11. ; all tests done ?
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hcmpeq tstno,#13. ; all tests done ?
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;
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jmp loop
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;
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