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add sys_tst_mig_n4d (MIG tester for Nexys4 DDR)

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wfjm
2019-01-18 19:34:15 +01:00
parent 74ad445c1e
commit 69e3fb5e68
14 changed files with 810 additions and 4 deletions
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9
doc/CHANGELOG.md
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@@ -28,9 +28,12 @@ The full set of tests is only run for tagged releases.
### New features
- new systems
- sys_tst_mig_arty: low level MIG interface test
- sys_tst_sram_arty: memory test
- sys_w11a_arty: w11a with full 3840 MB memory
- for Digilent Arty (classic and A7)
- sys_tst_mig_arty: low level MIG interface test
- sys_tst_sram_arty: memory test
- sys_w11a_arty: w11a with full 3840 MB memory
- for Digilent Nexys4 DDR
- sys_tst_mig_n4d: low level MIG interface test
- new components
- s7_cmt_sfs_2: dual-channel frequency synthesis MMCM/PLL wrapper
- s7_cmt_1ce1ce2c: clocking block for 7-Series: 2 clk+CEs + 2 clk

25
rtl/sys_gen/tst_mig/nexys4d/Makefile Normal file
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# $Id: Makefile 1099 2018-12-31 09:07:36Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2018-12-30 1099 1.0 Initial version
#
VBOM_all = sys_tst_mig_n4d.vbom
BIT_all = $(VBOM_all:.vbom=.bit)
#
include ${RETROBASE}/rtl/make_viv/viv_default_nexys4d.mk
#
.PHONY : all clean
#
all : $(BIT_all)
#
clean : viv_clean
#
#----
#
include ${RETROBASE}/rtl/make_viv/generic_vivado.mk
#
ifndef DONTINCDEP
include $(VBOM_all:.vbom=.dep_vsyn)
endif
#

60
rtl/sys_gen/tst_mig/nexys4d/sys_conf.vhd Normal file
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@@ -0,0 +1,60 @@
-- $Id: sys_conf.vhd 1099 2018-12-31 09:07:36Z mueller $
--
-- Copyright 2018- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 3, or (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for sys_tst_mig_nexys4d (for synthesis)
--
-- Dependencies: -
-- Tool versions: viv 2017.2; ghdl 0.34
-- Revision History:
-- Date Rev Version Comment
-- 2018-12-30 1099 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package sys_conf is
constant sys_conf_clksys_vcodivide : positive := 1;
constant sys_conf_clksys_vcomultiply : positive := 8; -- vco 800 MHz
constant sys_conf_clksys_outdivide : positive := 10; -- sys 80 MHz
constant sys_conf_clksys_gentype : string := "MMCM";
-- dual clock design, clkser = 120 MHz
constant sys_conf_clkser_vcodivide : positive := 1;
constant sys_conf_clkser_vcomultiply : positive := 12; -- vco 1200 MHz
constant sys_conf_clkser_outdivide : positive := 10; -- sys 120 MHz
constant sys_conf_clkser_gentype : string := "PLL";
-- configure rlink and hio interfaces --------------------------------------
constant sys_conf_ser2rri_defbaud : integer := 115200; -- default 115k baud
-- derived constants
constant sys_conf_clksys : integer :=
((100000000/sys_conf_clksys_vcodivide)*sys_conf_clksys_vcomultiply) /
sys_conf_clksys_outdivide;
constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000;
constant sys_conf_clkser : integer :=
((100000000/sys_conf_clkser_vcodivide)*sys_conf_clkser_vcomultiply) /
sys_conf_clkser_outdivide;
constant sys_conf_clkser_mhz : integer := sys_conf_clkser/1000000;
constant sys_conf_ser2rri_cdinit : integer :=
(sys_conf_clkser/sys_conf_ser2rri_defbaud)-1;
end package sys_conf;

28
rtl/sys_gen/tst_mig/nexys4d/sys_tst_mig_n4d.vbom Normal file
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# libs
../../../vlib/slvtypes.vhd
../../../vlib/cdclib/cdclib.vhd
../../../vlib/serport/serportlib.vbom
../../../vlib/rbus/rblib.vhd
../../../vlib/rbus/rbdlib.vhd
../../../vlib/rlink/rlinklib.vbom
../../../bplib/bpgen/bpgenlib.vbom
../../../bplib/sysmon/sysmonrbuslib.vbom
../../../bplib/nexys4d/miglib_nexys4d.vbom
${sys_conf := sys_conf.vhd}
@lib:unisim
# components
../../../bplib/bpgen/s7_cmt_1ce1ce2c.vbom
../../../vlib/cdclib/cdc_pulse.vbom
../../../vlib/cdclib/cdc_signal_s1_as.vbom
../../../bplib/bpgen/bp_rs232_4line_iob.vbom
../../../vlib/rlink/rlink_sp2c.vbom
../tst_mig.vbom
@tcl:../../../bplib/nexys4d/mig_nexys4d.tcl
[ghdl,vsim]../../../bplib/nexys4d/migui_nexys4d_gsim.vbom
../../../bplib/sysmon/sysmonx_rbus_base.vbom
../../../vlib/rbus/rbd_usracc.vbom
../../../vlib/rbus/rb_sres_or_3.vbom
# design
sys_tst_mig_n4d.vhd
@xdc:../../../bplib/nexys4d/nexys4d_pclk.xdc
@xdc:../../../bplib/nexys4d/nexys4d_pins.xdc

463
rtl/sys_gen/tst_mig/nexys4d/sys_tst_mig_n4d.vhd Normal file
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-- $Id: sys_tst_mig_n4d.vhd 1101 2019-01-02 21:22:37Z mueller $
--
-- Copyright 2018-2019 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 3, or (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: sys_tst_mig_n4d - syn
-- Description: test of nexyx4d ddr and its mig controller
--
-- Dependencies: bplib/bpgen/s7_cmt_1ce1ce2c
-- cdclib/cdc_signal_s1_as
-- cdclib/cdc_pulse
-- bplib/bpgen/bp_rs232_4line_iob
-- rlink/rlink_sp2c
-- tst_mig
-- bplib/nexyx4d/migui_nexyx4d (generated core)
-- bplib/sysmon/sysmonx_rbus_base
-- rbus/rbd_usracc
-- rbus/rb_sres_or_3
--
-- Test bench: tb/tb_tst_mig_n4d
--
-- Target Devices: generic
-- Tool versions: viv 2017.2; ghdl 0.34
--
-- Synthesized (viv):
-- Date Rev viv Target flop lutl lutm bram slic
-- 2019-01-02 1101 2017.2 xc7a100t-1l 4097 4310 457 1 1767
--
-- Revision History:
-- Date Rev Version Comment
-- 2018-12-30 1099 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.cdclib.all;
use work.serportlib.all;
use work.rblib.all;
use work.rbdlib.all;
use work.rlinklib.all;
use work.bpgenlib.all;
use work.sysmonrbuslib.all;
use work.miglib_nexys4d.all;
use work.sys_conf.all;
library unisim;
use unisim.vcomponents.ALL;
-- ----------------------------------------------------------------------------
entity sys_tst_mig_n4d is -- top level
-- implements nexys4d_mig_aif
port (
I_CLK100 : in slbit; -- 100 MHz clock
I_RXD : in slbit; -- receive data (board view)
O_TXD : out slbit; -- transmit data (board view)
O_RTS_N : out slbit; -- rx rts (board view; act.low)
I_CTS_N : in slbit; -- tx cts (board view; act.low)
I_SWI : in slv16; -- n4d switches
I_BTN : in slv5; -- n4d buttons
I_BTNRST_N : in slbit; -- n4d reset button
O_LED : out slv16; -- n4d leds
O_RGBLED0 : out slv3; -- n4d rgb-led 0
O_RGBLED1 : out slv3; -- n4d rgb-led 1
O_ANO_N : out slv8; -- 7 segment disp: anodes (act.low)
O_SEG_N : out slv8; -- 7 segment disp: segments (act.low)
DDR2_DQ : inout slv16; -- dram: data in/out
DDR2_DQS_P : inout slv2; -- dram: data strobe (diff-p)
DDR2_DQS_N : inout slv2; -- dram: data strobe (diff-n)
DDR2_ADDR : out slv13; -- dram: address
DDR2_BA : out slv3; -- dram: bank address
DDR2_RAS_N : out slbit; -- dram: row addr strobe (act.low)
DDR2_CAS_N : out slbit; -- dram: column addr strobe (act.low)
DDR2_WE_N : out slbit; -- dram: write enable (act.low)
DDR2_CK_P : out slv1; -- dram: clock (diff-p)
DDR2_CK_N : out slv1; -- dram: clock (diff-n)
DDR2_CKE : out slv1; -- dram: clock enable
DDR2_CS_N : out slv1; -- dram: chip select (act.low)
DDR2_DM : out slv2; -- dram: data input mask
DDR2_ODT : out slv1 -- dram: on-die termination
);
end sys_tst_mig_n4d;
architecture syn of sys_tst_mig_n4d is
signal CLK100_BUF : slbit := '0';
signal XX_CLK : slbit := '0'; -- kept to keep clock setup similar
signal XX_CE_USEC : slbit := '0'; -- to w11a or other 'normal' systems
signal XX_CE_MSEC : slbit := '0'; --
signal CLK : slbit := '0';
signal CE_USEC : slbit := '0';
signal CE_MSEC : slbit := '0';
signal CLKS : slbit := '0';
signal CES_MSEC : slbit := '0';
signal CLKMIG : slbit := '0';
signal CLKREF : slbit := '0';
signal LOCKED : slbit := '0'; -- raw LOCKED
signal LOCKED_CLKMIG : slbit := '0'; -- sync'ed to CLKMIG
signal RXD : slbit := '1';
signal TXD : slbit := '0';
signal RTS_N : slbit := '0';
signal CTS_N : slbit := '0';
signal SWI : slv16 := (others=>'0');
signal BTN : slv5 := (others=>'0');
signal LED : slv16 := (others=>'0');
signal DSP_DAT : slv32 := (others=>'0');
signal DSP_DP : slv8 := (others=>'0');
signal RB_MREQ : rb_mreq_type := rb_mreq_init;
signal RB_SRES : rb_sres_type := rb_sres_init;
signal RB_LAM : slv16 := (others=>'0');
signal RB_STAT : slv4 := (others=>'0');
signal SER_MONI : serport_moni_type := serport_moni_init;
signal RB_SRES_TST : rb_sres_type := rb_sres_init;
signal RB_SRES_SYSMON : rb_sres_type := rb_sres_init;
signal RB_SRES_USRACC : rb_sres_type := rb_sres_init;
signal RB_LAM_TST : slbit := '0';
signal APP_ADDR : slv(mig_mawidth-1 downto 0) := (others=>'0');
signal APP_CMD : slv3 := (others=>'0');
signal APP_EN : slbit := '0';
signal APP_WDF_DATA : slv(mig_dwidth-1 downto 0) := (others=>'0');
signal APP_WDF_END : slbit := '0';
signal APP_WDF_MASK : slv(mig_mwidth-1 downto 0) := (others=>'0');
signal APP_WDF_WREN : slbit := '0';
signal APP_RD_DATA : slv(mig_dwidth-1 downto 0) := (others=>'0');
signal APP_RD_DATA_END : slbit := '0';
signal APP_RD_DATA_VALID : slbit := '0';
signal APP_RDY : slbit := '0';
signal APP_WDF_RDY : slbit := '0';
signal APP_SR_REQ : slbit := '0';
signal APP_REF_REQ : slbit := '0';
signal APP_ZQ_REQ : slbit := '0';
signal APP_SR_ACTIVE : slbit := '0';
signal APP_REF_ACK : slbit := '0';
signal APP_ZQ_ACK : slbit := '0';
signal MIG_UI_CLK : slbit := '0';
signal MIG_UI_CLK_SYNC_RST : slbit := '0';
signal MIG_INIT_CALIB_COMPLETE : slbit := '0';
signal MIG_SYS_RST : slbit := '0';
signal XADC_TEMP : slv12 := (others=>'0'); -- xadc die temp; on CLK
signal R_DIMCNT : slv2 := (others=>'0');
signal R_DIMFLG : slbit := '0';
constant rbaddr_rbmon : slv16 := x"ffe8"; -- ffe8/0008: 1111 1111 1110 1xxx
constant rbaddr_sysmon: slv16 := x"fb00"; -- fb00/0080: 1111 1011 0xxx xxxx
constant sysid_proj : slv16 := x"0105"; -- tst_mig
constant sysid_board : slv8 := x"08"; -- nexys4d
constant sysid_vers : slv8 := x"00";
begin
CLK100_BUFG: bufg
port map (
I => I_CLK100,
O => CLK100_BUF
);
GEN_CLKALL : s7_cmt_1ce1ce2c -- clock generator system ------------
generic map (
CLKIN_PERIOD => 10.0,
CLKIN_JITTER => 0.01,
STARTUP_WAIT => false,
CLK0_VCODIV => sys_conf_clksys_vcodivide,
CLK0_VCOMUL => sys_conf_clksys_vcomultiply,
CLK0_OUTDIV => sys_conf_clksys_outdivide,
CLK0_GENTYPE => sys_conf_clksys_gentype,
CLK0_CDUWIDTH => 7,
CLK0_USECDIV => sys_conf_clksys_mhz,
CLK0_MSECDIV => 1000,
CLK1_VCODIV => sys_conf_clkser_vcodivide,
CLK1_VCOMUL => sys_conf_clkser_vcomultiply,
CLK1_OUTDIV => sys_conf_clkser_outdivide,
CLK1_GENTYPE => sys_conf_clkser_gentype,
CLK1_CDUWIDTH => 7,
CLK1_USECDIV => sys_conf_clkser_mhz,
CLK1_MSECDIV => 1000,
CLK23_VCODIV => 1,
CLK23_VCOMUL => 12, -- vco 1200 MHz
CLK2_OUTDIV => 8, -- mig sys 150.0 MHz
CLK3_OUTDIV => 6, -- mig ref 200.0 MHz
CLK23_GENTYPE => "PLL")
port map (
CLKIN => CLK100_BUF,
CLK0 => XX_CLK,
CE0_USEC => XX_CE_USEC,
CE0_MSEC => XX_CE_MSEC,
CLK1 => CLKS,
CE1_USEC => open,
CE1_MSEC => CES_MSEC,
CLK2 => CLKMIG,
CLK3 => CLKREF,
LOCKED => LOCKED
);
-- Note: CLK0 is generated as in 'normal' systems to keep PPL/MMCM setup
-- as similar as possible. The CE_USEC and CE_MSEC pulses are forwarded
-- from the 80 MHz CLK0 domain to the 75.000 MHz MIG UI_CLK domain
CDC_CEUSEC : cdc_pulse -- provide CLK side CE_USEC
generic map (
POUT_SINGLE => true,
BUSY_WACK => false)
port map (
CLKM => XX_CLK,
RESET => '0',
CLKS => CLK,
PIN => XX_CE_USEC,
BUSY => open,
POUT => CE_USEC
);
CDC_CEMSEC : cdc_pulse -- provide CLK side CE_MSEC
generic map (
POUT_SINGLE => true,
BUSY_WACK => false)
port map (
CLKM => XX_CLK,
RESET => '0',
CLKS => CLK,
PIN => XX_CE_MSEC,
BUSY => open,
POUT => CE_MSEC
);
CDC_CLKMIG_LOCKED : cdc_signal_s1_as
port map (
CLKO => CLKMIG,
DI => LOCKED,
DO => LOCKED_CLKMIG
);
IOB_RS232 : bp_rs232_4line_iob -- serport iob ----------------------
port map (
CLK => CLKS,
RXD => RXD,
TXD => TXD,
CTS_N => CTS_N,
RTS_N => RTS_N,
I_RXD => I_RXD,
O_TXD => O_TXD,
I_CTS_N => I_CTS_N,
O_RTS_N => O_RTS_N
);
RLINK : rlink_sp2c
generic map (
BTOWIDTH => 8, -- 256 cycles, for slow mem iface
RTAWIDTH => 12,
SYSID => sysid_proj & sysid_board & sysid_vers,
IFAWIDTH => 5, -- 32 word input fifo
OFAWIDTH => 5, -- 32 word output fifo
ENAPIN_RLMON => sbcntl_sbf_rlmon,
ENAPIN_RBMON => sbcntl_sbf_rbmon,
CDWIDTH => 12,
CDINIT => sys_conf_ser2rri_cdinit,
RBMON_AWIDTH => 0,
RBMON_RBADDR => rbaddr_rbmon)
port map (
CLK => CLK,
CE_USEC => CE_USEC,
CE_MSEC => CE_MSEC,
CE_INT => CE_MSEC,
RESET => '0', -- FIXME: no RESET
CLKS => CLKS,
CES_MSEC => CES_MSEC,
ENAXON => '0',
ESCFILL => '0',
RXSD => RXD,
TXSD => TXD,
CTS_N => CTS_N,
RTS_N => RTS_N,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES,
RB_LAM => RB_LAM,
RB_STAT => RB_STAT,
RL_MONI => open,
SER_MONI => SER_MONI
);
TST : entity work.tst_mig
generic map (
RB_ADDR => slv(to_unsigned(2#0000000000000000#,16)),
MAWIDTH => mig_mawidth,
MWIDTH => mig_mwidth)
port map (
CLK => CLK,
CE_USEC => CE_USEC,
RESET => '0', -- FIXME: no RESET
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_TST,
RB_STAT => RB_STAT,
RB_LAM => RB_LAM_TST,
APP_ADDR => APP_ADDR,
APP_CMD => APP_CMD,
APP_EN => APP_EN,
APP_WDF_DATA => APP_WDF_DATA,
APP_WDF_END => APP_WDF_END,
APP_WDF_MASK => APP_WDF_MASK,
APP_WDF_WREN => APP_WDF_WREN,
APP_RD_DATA => APP_RD_DATA,
APP_RD_DATA_END => APP_RD_DATA_END,
APP_RD_DATA_VALID => APP_RD_DATA_VALID,
APP_RDY => APP_RDY,
APP_WDF_RDY => APP_WDF_RDY,
APP_SR_REQ => APP_SR_REQ,
APP_REF_REQ => APP_REF_REQ,
APP_ZQ_REQ => APP_ZQ_REQ,
APP_SR_ACTIVE => APP_SR_ACTIVE,
APP_REF_ACK => APP_REF_ACK,
APP_ZQ_ACK => APP_ZQ_ACK,
MIG_UI_CLK_SYNC_RST => MIG_UI_CLK_SYNC_RST,
MIG_INIT_CALIB_COMPLETE => MIG_INIT_CALIB_COMPLETE,
MIG_DEVICE_TEMP_I => XADC_TEMP
);
MIG_CTL: migui_nexys4d -- MIG iface -----------------
port map (
DDR2_DQ => DDR2_DQ,
DDR2_DQS_P => DDR2_DQS_P,
DDR2_DQS_N => DDR2_DQS_N,
DDR2_ADDR => DDR2_ADDR,
DDR2_BA => DDR2_BA,
DDR2_RAS_N => DDR2_RAS_N,
DDR2_CAS_N => DDR2_CAS_N,
DDR2_WE_N => DDR2_WE_N,
DDR2_CK_P => DDR2_CK_P,
DDR2_CK_N => DDR2_CK_N,
DDR2_CKE => DDR2_CKE,
DDR2_CS_N => DDR2_CS_N,
DDR2_DM => DDR2_DM,
DDR2_ODT => DDR2_ODT,
APP_ADDR => APP_ADDR,
APP_CMD => APP_CMD,
APP_EN => APP_EN,
APP_WDF_DATA => APP_WDF_DATA,
APP_WDF_END => APP_WDF_END,
APP_WDF_MASK => APP_WDF_MASK,
APP_WDF_WREN => APP_WDF_WREN,
APP_RD_DATA => APP_RD_DATA,
APP_RD_DATA_END => APP_RD_DATA_END,
APP_RD_DATA_VALID => APP_RD_DATA_VALID,
APP_RDY => APP_RDY,
APP_WDF_RDY => APP_WDF_RDY,
APP_SR_REQ => APP_SR_REQ,
APP_REF_REQ => APP_REF_REQ,
APP_ZQ_REQ => APP_ZQ_REQ,
APP_SR_ACTIVE => APP_SR_ACTIVE,
APP_REF_ACK => APP_REF_ACK,
APP_ZQ_ACK => APP_ZQ_ACK,
UI_CLK => CLK,
UI_CLK_SYNC_RST => MIG_UI_CLK_SYNC_RST,
INIT_CALIB_COMPLETE => MIG_INIT_CALIB_COMPLETE,
SYS_CLK_I => CLKMIG,
CLK_REF_I => CLKREF,
DEVICE_TEMP_I => XADC_TEMP,
SYS_RST => MIG_SYS_RST
);
MIG_SYS_RST <= (not LOCKED_CLKMIG) or I_BTN(3); -- provisional !
SMRB: sysmonx_rbus_base
generic map ( -- use default INIT_ (Vccint=1.00)
CLK_MHZ => sys_conf_clksys_mhz,
RB_ADDR => rbaddr_sysmon)
port map (
CLK => CLK,
RESET => '0', -- FIXME: no RESET
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_SYSMON,
ALM => open,
OT => open,
TEMP => XADC_TEMP
);
UARB : rbd_usracc
port map (
CLK => CLK,
RB_MREQ => RB_MREQ,
RB_SRES => RB_SRES_USRACC
);
RB_SRES_OR : rb_sres_or_3 -- rbus or ---------------------------
port map (
RB_SRES_1 => RB_SRES_TST,
RB_SRES_2 => RB_SRES_SYSMON,
RB_SRES_3 => RB_SRES_USRACC,
RB_SRES_OR => RB_SRES
);
proc_dim: process (CLKMIG)
begin
if rising_edge(CLKMIG) then
R_DIMCNT <= slv(unsigned(R_DIMCNT) + 1);
if unsigned(R_DIMCNT) = 0 then
R_DIMFLG <= '1';
else
R_DIMFLG <= '0';
end if;
end if;
end process proc_dim;
RB_LAM(0) <= RB_LAM_TST;
-- LED group(0:3): rlink traffic
O_LED(0) <= SER_MONI.rxact;
O_LED(1) <= SER_MONI.txact;
O_LED(2) <= '0';
O_LED(3) <= '0';
-- LED group(4:7) serious error conditions
O_LED(4) <= R_DIMFLG and (I_BTN(0) or not LOCKED);
O_LED(5) <= R_DIMFLG and (I_BTN(0));
O_LED(6) <= R_DIMFLG and (I_BTN(0) or MIG_UI_CLK_SYNC_RST);
O_LED(7) <= R_DIMFLG and (I_BTN(0) or not MIG_INIT_CALIB_COMPLETE);
-- green LED for activity
O_LED(8) <= R_DIMFLG and (I_BTN(1));
O_LED(9) <= R_DIMFLG and (I_BTN(1));
O_LED(10) <= R_DIMFLG and (I_BTN(1) or not APP_RDY);
O_LED(11) <= R_DIMFLG and (I_BTN(1) or not APP_WDF_RDY);
-- blue LED currently unused
O_LED(12) <= R_DIMFLG and (I_BTN(2));
O_LED(13) <= R_DIMFLG and (I_BTN(2));
O_LED(14) <= R_DIMFLG and (I_BTN(2));
O_LED(15) <= R_DIMFLG and (I_BTN(2));
-- RGB LEDs unused
O_RGBLED0 <= (others=>'0');
O_RGBLED1 <= (others=>'0');
-- 7 segment disp unused
O_ANO_N <= (others=>'1');
O_SEG_N <= (others=>'1');
end syn;

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rtl/sys_gen/tst_mig/nexys4d/sys_tst_mig_n4d.vmfset Normal file
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# $Id: sys_tst_mig_n4d.vmfset 1101 2019-01-02 21:22:37Z mueller $
#
# ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
[syn]
# general issues -----------------------------------------------
{2018.2:}
# stupid new warning, Xilinx suggests to safely ingnore
i [Constraints 18-5210] # generic
{:}
# false_path -hold ignored by synth ----------------------------
I [Designutils 20-1567] # generic
# port driven by constant --------------------------------------
# not all LEDs used # OK 2018-12-30
i [Synth 8-3917] O_LED[(2|3)]
i [Synth 8-3917] O_RGBLED0[\d]
i [Synth 8-3917] O_RGBLED1[\d]
# 7 segment display unused # OK 2018-12-30
i [Synth 8-3917] O_ANO_N[\d]
i [Synth 8-3917] O_SEG_N[\d]
# tying undriven pin to constant -------------------------------
# only few LAMs used # OK 2018-12-30
i [Synth 8-3295] RLINK:RB_LAM[\d*]
# unconnected ports --------------------------------------------
I [Synth 8-3331] RB_MREQ # generic
# --> I_SWI not used # OK 2018-12-30
i [Synth 8-3331] I_SWI[\d+]
# --> I_BTN partially, I_BTNRST_N not used # OK 2018-12-30
i [Synth 8-3331] I_BTN[4]
i [Synth 8-3331] I_BTNRST_N
# --> rlink_sp2c doesn't use CE_USEC and CE_MSEC # OK 2018-12-30
i [Synth 8-3331] rlink_sp2c.*CE_(USEC|MSEC)
# --> APP_SR_ACTIVE is unused (reserved port) # OK 2018-12-30
i [Synth 8-3331] APP_SR_ACTIVE
# sequential element removed (2017.1 nonsense) -----------------
I [Synth 8-6014] _reg # generic
# unused sequential element ------------------------------------
I [Synth 8-3332] R_LREGS_reg[attn][\d*] # generic
# --> usec unused # OK 2018-12-30
i [Synth 8-3332] R_REGS_reg[usec].* sys_tst_mig_n4d
# --> no stat used; moneop and monattn unused # OK 2018-12-30
i [Synth 8-3332] R_BREGS_reg[stat][(0|1|2|3)].* sys_tst_mig_n4d
i [Synth 8-3332] R_LREGS_reg[(moneop|monattn)].* sys_tst_mig_n4d
# --> no rbinit used # OK 2018-12-30
i [Synth 8-3332] R_BREGS_reg[rbinit].* sys_tst_mig_n4d
# ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
[imp]
I [Vivado 12-2489] # multiple of 1 ps
I [Physopt 32-742] # BRAM Flop Optimization
{:2017.2}
# --> spurious Invalid VCCINTIO messages # OK 2018-11-25
i [Designutils 20-266] Invalid Voltage Source VCCINTIO
{:}
# ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
[bit]
# see https://www.xilinx.com/support/answers/64180.html # OK 2018-12-22
i [DRC REQP-1709] PLLE2_ADV

2
rtl/sys_gen/tst_mig/nexys4d/tb/.gitignore vendored Normal file
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tb_tst_mig_n4d
sysmon_stim

39
rtl/sys_gen/tst_mig/nexys4d/tb/Makefile Normal file
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# $Id: Makefile 1099 2018-12-31 09:07:36Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2018-12-30 1099 1.0 Initial version
#
EXE_all = tb_tst_mig_n4d
#
include ${RETROBASE}/rtl/make_viv/viv_default_nexys4d.mk
#
.PHONY : all all_ssim all_osim clean
.PHONY : all_XSim all_XSim_ssim all_XSim_osim all_XSim_tsim
#
all : $(EXE_all)
all_ssim : $(EXE_all:=_ssim)
all_osim : $(EXE_all:=_osim)
#
all_XSim : $(EXE_all:=_XSim)
all_XSim_ssim : $(EXE_all:=_XSim_ssim)
all_XSim_osim : $(EXE_all:=_XSim_osim)
all_XSim_tsim : $(EXE_all:=_XSim_tsim)
#
clean : viv_clean ghdl_clean xsim_clean
#
#-----
#
include ${RETROBASE}/rtl/make_viv/generic_ghdl.mk
include ${RETROBASE}/rtl/make_viv/generic_xsim.mk
include ${RETROBASE}/rtl/make_viv/generic_vivado.mk
#
VBOM_all = $(wildcard *.vbom)
#
ifndef DONTINCDEP
include $(VBOM_all:.vbom=.dep_vsyn)
include $(VBOM_all:.vbom=.dep_ghdl)
include $(VBOM_all:.vbom=.dep_vsim)
include $(wildcard *.o.dep_ghdl)
endif
#

57
rtl/sys_gen/tst_mig/nexys4d/tb/sys_conf_sim.vhd Normal file
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-- $Id: sys_conf_sim.vhd 1099 2018-12-31 09:07:36Z mueller $
--
-- Copyright 2018- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 3, or (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for sys_tst_mig_nexys4d (for simulation)
--
-- Dependencies: -
-- Tool versions: viv 2017.2; ghdl 0.34
-- Revision History:
-- Date Rev Version Comment
-- 2018-12-23 1092 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package sys_conf is
constant sys_conf_clksys_vcodivide : positive := 1;
constant sys_conf_clksys_vcomultiply : positive := 8; -- vco 800 MHz
constant sys_conf_clksys_outdivide : positive := 10; -- sys 80 MHz
constant sys_conf_clksys_gentype : string := "MMCM";
-- dual clock design, clkser = 120 MHz
constant sys_conf_clkser_vcodivide : positive := 1;
constant sys_conf_clkser_vcomultiply : positive := 12; -- vco 1200 MHz
constant sys_conf_clkser_outdivide : positive := 10; -- sys 120 MHz
constant sys_conf_clkser_gentype : string := "PLL";
-- configure rlink and hio interfaces --------------------------------------
constant sys_conf_ser2rri_cdinit : integer := 1-1; -- 1 cycle/bit in sim
-- derived constants
constant sys_conf_clksys : integer :=
((12000000/sys_conf_clksys_vcodivide)*sys_conf_clksys_vcomultiply) /
sys_conf_clksys_outdivide;
constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000;
constant sys_conf_clkser : integer :=
((12000000/sys_conf_clkser_vcodivide)*sys_conf_clkser_vcomultiply) /
sys_conf_clkser_outdivide;
constant sys_conf_clkser_mhz : integer := sys_conf_clkser/1000000;
end package sys_conf;

9
rtl/sys_gen/tst_mig/nexys4d/tb/tb_tst_mig_n4d.vbom Normal file
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# configure tb_nexys4d_dram with sys_tst_mig_nexys4d target;
# use vhdl configure file (tb_tst_mig_nexys4d.vhd) to allow
# that all configurations will co-exist in work library
# configure
nexys4d_dram_aif = ../sys_tst_mig_n4d.vbom
sys_conf = sys_conf_sim.vhd
# design
../../../../bplib/nexys4d/tb/tb_nexys4d_dram.vbom
tb_tst_mig_n4d.vhd

35
rtl/sys_gen/tst_mig/nexys4d/tb/tb_tst_mig_n4d.vhd Normal file
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-- $Id: tb_tst_mig_n4d.vhd 1099 2018-12-31 09:07:36Z mueller $
--
-- Copyright 2018- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 3, or (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: tb_tst_mig_n4d
-- Description: Configuration for tb_tst_mig_n4d for tb_nexys4d_dram
--
-- Dependencies: sys_tst_mig_n4d
--
-- To test: sys_tst_mig_n4d
--
-- Revision History:
-- Date Rev Version Comment
-- 2018-12-23 1092 1.0 Initial version
------------------------------------------------------------------------------
configuration tb_tst_mig_n4d of tb_nexys4d_dram is
for sim
for all : nexys4d_dram_aif
use entity work.sys_tst_mig_n4d;
end for;
end for;
end tb_tst_mig_n4d;

13
rtl/sys_gen/tst_mig/nexys4d/tb/tbrun.yml Normal file
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# $Id: tbrun.yml 1099 2018-12-31 09:07:36Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2018-12-23 1092 1.0 Initial version
#
- default:
mode: ${viv_modes}
#
- tag: [viv, sys_tst_mig, n4d, base]
test: |
tbrun_tbwrri --lsuf base --pack tst_mig tb_tst_mig_n4d${ms} \
tst_mig::setup tst_mig::test_all

7
rtl/sys_gen/tst_mig/nexys4d/tb/tbw.dat Normal file
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# $Id: tbw.dat 1104 2019-01-06 09:17:06Z mueller $
#
[tb_tst_mig_n4d]
rlink_cext_fifo_rx = <fifo>
rlink_cext_fifo_tx = <fifo>
rlink_cext_conf = <null>
sysmon_stim = ../../../../bplib/sysmon/tb/sysmon_stim_n4.dat

3
rtl/sys_gen/tst_mig/tbrun.yml
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@@ -1,7 +1,8 @@
# $Id: tbrun.yml 1092 2018-12-24 08:01:50Z mueller $
# $Id: tbrun.yml 1103 2019-01-04 13:18:54Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2018-12-23 1092 1.0 Initial version
#
- include: arty/tb/tbrun.yml
- include: nexys4d/tb/tbrun.yml