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additional documentation
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Walter F.J. Mueller
7
INSTALL.txt
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7
INSTALL.txt
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# $Id: INSTALL.txt 317 2010-07-22 19:36:56Z mueller $
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For project installation notes see
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doc/INSTALL.txt
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For further release and usage notes see
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doc/README.txt
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139
doc/INSTALL.txt
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doc/INSTALL.txt
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# $Id: INSTALL.txt 317 2010-07-22 19:36:56Z mueller $
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Guide to install and build w11a
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Table of content:
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1. Download
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2. Install and setup the build system
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3. Compile UNISIM/SIMPRIM libraries for ghdl
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4. The build system
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5. Building test benches
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6. Building systems
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1. Download ---------------------------------------------------------------
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All instructions below assume that the project files reside in a
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working directory with the name represented as <wdir>
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To download latest tagged version (V0.5) of w11a
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cd <wdir>
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svn co http://opencores.org/ocsvn/w11/w11/tags/w11a_V0.5
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To download latest snapshot of trunk
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cd <wdir>
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svn co http://opencores.org/ocsvn/w11/w11/trunk
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2. Install and setup the build system -------------------------------------
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The build system for test benches and systems requires
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- the definition of the environment variable RETROBASE
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- that the tools binary directory is in the path
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For bash and alike use
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export RETROBASE=<wdir>
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export PATH=$PATH:$RETROBASE/tools/bin
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After that building functional model based test benches will work. If you
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want to also build post-xst or post-par test benches read next section.
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3. Compile UNISIM/SIMPRIM libraries for ghdl ------------------------------
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The build system for test benches also supports test benches run against
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the gate level models derived after the xst, map or par step. In this
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case ghdl has to link against a compiled UNISIM or SIMPRIM library.
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To make handling of the parallel installion of several WebPack versions
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easy the compiled libraries are stored in sub-directories under $XILINX:
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$XILINX/ghdl/unisim
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$XILINX/ghdl/simprim
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Two helper scripts will create these libraries:
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<setup WebPack, e.g. source .../ISE_DS/settings32.sh>
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cd $RETROBASE
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xilinx_ghdl_unisim
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xilinx_ghdl_simprim
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If you have several WebPack versions installed, repeat for each version.
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4. The build system -------------------------------------------------------
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Simulation and synthesis tools usually need a list of the VHDL source
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files, often in proper compilation order (libraries before components).
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The different tools have different formats of these 'project files'.
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The build system employed in this project is based on
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"VHDL bill of material" or 'vbom' files
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which list for each vhdl source file the libraries and sources for
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the instantiated components, the later via their vbom, and last but
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not least the name of the vhdl source file. All file name are relative
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to the current directory. A recursive traversal through all vbom's gives
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for each vhld module all sources needed to compile it. The vbomconv script
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in tools/bin does this, and generates depending on options
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- make dependency files
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- ISE xst project files
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- ISE ISim project files
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- ghdl commands for analysis, inspection and make step
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The master make files contain pattern rules like
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%.ngc : %.vbom -- synthesize with xst
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% : %.vbom -- build functional model test bench
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which encapsulate all the vbomconf magic
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A full w11a is build from more than 80 source files, test benches from
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even more. Using the vbom's a large number of designs can be easily
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maintained.
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5. Building test benches --------------------------------------------------
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To compile a test bench named <tbench> all is needed is
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make <tbench>
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The make file will use <tbench>.vbom, create all make dependency files,
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and generate the needed ghdl commands.
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In many cases the test benches can also be compiled against the gate
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level models derived after the xst, map or par step. To compile them
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make ghdl_tmp_clean
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make <tbench>_ssim # for post-xst
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make <tbench>_fsim # for post-map
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make <tbench>_tsim # for post-par
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The 'make ghdl_tmp_clean' is needed to flush the ghdl work area from
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the compilation remains of earlier functional model compiles.
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6. Building systems -------------------------------------------------------
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To generate a bit file for a system named <sys> all is needed is
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make <sys>.bit
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The make file will use <sys>.vbom, create all make dependency files, build
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the ucf file with cpp, and run the synthesis flow (xst, ngdbuild, par, trce).
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The log files will be named
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<sys>_xst.log # xst log file
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<sys>_tra.log # translate (ngdbuild) log file (renamed %.bld)
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<sys>_map.log # map log file (renamed %_map.mrp)
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<sys>_par.log # par log file (renamed %.par)
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<sys>_pad.log # pad file (renamed %_pad.txt)
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<sys>_twr.log # trce log file (renamed %.twr)
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To load the bitfile with WebPack impact into the target board use
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make <sys>.impact
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If only the xst or par output is wanted just use
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make <sys>.ngc
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make <sys>.ncd
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57
doc/README.txt
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doc/README.txt
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# $Id: README.txt 317 2010-07-22 19:36:56Z mueller $
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Release notes for w11a
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Table of content:
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1. Documentation
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2. Files
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3. Change Log
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1. Documentation ----------------------------------------------------------
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More detailed information on installation, build and test can be found
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in the doc directory, specifically
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* README.txt: release notes
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* INSTALL.txt: installation and building test benches and systems
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* w11a_tb_guide.txt: running test benches
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* w11a_os_guide.txt: booting operating systems
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2. Files ------------------------------------------------------------------
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doc Documentation
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rtl VHDL sources
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rtl/bplib - board and component support libs
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rtl/bplib/issi - for ISSI parts
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rtl/bplib/micron - for Micron parts
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rtl/bplib/nexys2 - for Digilent Nexsy2 board
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rtl/bplib/s3board - for Digilent S3BOARD
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rtl/ibus - ibus devices (UNIBUS peripherals)
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rtl/sys_gen - top level designs
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rtl/sys_gen/w11a - top level designs for w11a SoC
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rtl/sys_gen/w11a/nexys2 - w11a SoC for Digilent Nexsy2
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rtl/sys_gen/w11a/s3board - w11a SoC for Digilent S3BOARD
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rtl/vlib - VHDL component libs
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rtl/vlib/comlib - communication
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rtl/vlib/genlib - general
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rtl/vlib/memlib - memory
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rtl/vlib/rri - remote-register-interface
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rtl/vlib/serport - serial port (UART)
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rtl/vlib/simlib - simulation helper lib
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rtl/vlib/xlib - Xilinx specific components
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rtl/w11a - w11a core
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tools helper programs
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tools/bin - scripts and binaries
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3. Change Log -------------------------------------------------------------
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2010-07-24 - w11a version V0.5 -----------------------------
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Initial release with
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- w11a CPU core
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- basic set of peripherals: kw11l, dl11, lp11, pc11, rk11/rk05
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- just for fun: iist (not fully implemented and tested yet)
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- two complete system configurations with
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- for a Digilent S3BOARD rtl/sys_gen/w11a/s3board/sys_w11a_s3
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- for a Digilent Nexys2 rtl/sys_gen/w11a/nexys2/sys_w11a_n2
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@@ -1,6 +1,14 @@
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# $ $Id: w11a_known_issues.txt 316 2010-07-16 19:07:47Z mueller $
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# $Id: w11a_known_issues.txt 317 2010-07-22 19:36:56Z mueller $
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1. Known differences between w11a and KB-11C (11/70)
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Summary of known issues for w11a CPU and systems
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Table of content:
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1. Known differences between w11a and KB-11C (11/70)
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2. Known limitations
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3. Known bugs
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1. Known differences between w11a and KB-11C (11/70) ----------------------
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- the SPL instruction in the 11/70 always fetched the next instruction
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regardless of pending device or even console interrupts. This is known
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@@ -30,7 +38,7 @@
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depends on them, therefore they are considered acceptable implementation
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differences
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2. Known limitations
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2. Known limitations ------------------------------------------------------
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- some programs use timing loops based on the execution speed of the
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original processors. This can lead to spurious timeouts, especially
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@@ -44,7 +52,7 @@
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--> a 'watch dog' mechanism will be added in a future version which
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suspends the CPU when the server doesn't respond fast enough.
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3. Known bugs
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3. Known bugs -------------------------------------------------------------
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- TCK-036 pri=L: RK11: hardware poll not working
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The RK11/RK05 hardware poll logic is probably no reflecting the
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@@ -1,4 +1,14 @@
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# $ $Id: w11a_os_guide.txt 316 2010-07-16 19:07:47Z mueller $
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# $Id: w11a_os_guide.txt 317 2010-07-22 19:36:56Z mueller $
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Guide to run operating system images on w11a systems
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Table of content:
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1. I/O emulation setup
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2. FPGA Board setup
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3. Unix V5 system
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4. 2.11BSD system
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1. I/O emulation setup ----------------------------------------------------
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@@ -1,4 +1,4 @@
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$ $Id: w11a_seq_flow.txt 315 2010-07-11 22:18:39Z mueller $
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# $Id: w11a_seq_flow.txt 317 2010-07-22 19:36:56Z mueller $
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The states are
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1. grouped by 'flows', related states are in a dashed box
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@@ -1,6 +1,14 @@
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# $ $Id: w11a_tb_guide.txt 316 2010-07-16 19:07:47Z mueller $
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# $Id: w11a_tb_guide.txt 317 2010-07-22 19:36:56Z mueller $
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Guide to running w11a test benches
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Table of content:
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1. Unit tests benches
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2. Available unit tests benches
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3. System tests benches
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4. Available system tests benches
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== Guide to running w11a test benches ==
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1. Unit tests benches -----------------------------------------------------
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@@ -1,4 +1,4 @@
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-- $Id: ibdr_rk11.vhd 314 2010-07-09 17:38:41Z mueller $
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-- $Id: ibdr_rk11.vhd 317 2010-07-22 19:36:56Z mueller $
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--
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-- Copyright 2008-2010 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
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--
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@@ -75,7 +75,7 @@ architecture syn of ibdr_rk11 is
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constant ibaddr_rkcs : slv3 := "010"; -- rkcs address offset
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constant ibaddr_rkwc : slv3 := "011"; -- rkwc address offset
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constant ibaddr_rkba : slv3 := "100"; -- rkba address offset
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constant ibaddr_rkda : slv3 := "101"; -- rkba address offset
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constant ibaddr_rkda : slv3 := "101"; -- rkda address offset
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constant ibaddr_rkmr : slv3 := "110"; -- rkmr address offset
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constant ibaddr_rkdb : slv3 := "111"; -- rkdb address offset
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@@ -1,4 +1,4 @@
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# $Id: Makefile.xflow 311 2010-06-30 17:52:37Z mueller $
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# $Id: Makefile.xflow 317 2010-07-22 19:36:56Z mueller $
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#
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# Revision History:
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# Date Rev Version Comment
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@@ -111,6 +111,7 @@ XFLOW = xflow -p ${ISE_PATH}
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# %_map.log map log file (renamed %_map.mrp)
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# %_par.log par log file (renamed %.par)
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# %_pad.log pad file (renamed %_pad.txt)
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# %_twr.log trce log file (renamed %.twr)
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#
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%.ncd %.pcf: %.ngc
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if [ ! -d ./ise ]; then mkdir ./ise; fi
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