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doc update [skip ci]

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wfjm
2022-09-13 08:07:43 +02:00
parent 278d2e229d
commit 6f0bd3a81f
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26
doc/README_resolved_issues.md
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@@ -1,5 +1,31 @@
# Resolved issues
### V0.791-3 {[issue #35](https://github.com/wfjm/w11/issues/35)} -- MMU: D space used instead of I space for PC deferred specifiers
Test 072 of `ekbee1` fails with
```
D-SPACE ENABLE CIRCUITRY HAS FAILED
ERROR AUTOI/D VIRTUAL
REGISTR REGISTR ADDRESS TESTNO PC AT ABORT
100027 000000 060410 000072 060412
100027 000027 060416 000072 060422
```
The test does
```
060410: tst (pc)
060416: cmp #240,(pc)
```
and expects that these accesses are done to I space.
They are done to D space instead.
The w11 uses D space only for `(pc)+` and `@(pc)+` specifiers.
Clearly a bug.
Wasn't detected so far because this access mode has no practical value
and this therefore not used in normal software.
Fixed with commit [278d2e2](https://github.com/wfjm/w11/commit/278d2e2),
see [ECO-034](ECO-034-MMU_d-space-pc.md).
### V0.791-2 {[issue #34](https://github.com/wfjm/w11/issues/34)} -- MMU: ACF=1 traps on any access
Test 055 of `ekbee1` fails with

17
doc/w11a_diff_70_mmu_trap_suppression.md
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@@ -2,8 +2,9 @@
### MMU traps not suppressed when MMU register accessed
The 11/70 does not execute an MMU trap when an MMU register is accessed,
thus `MMR0` to `MMR3` and any of the `PDR` and `PAR` registers.
The 11/70 does not execute an MMU trap and doesn't set A or W bits in `PDR`
when an MMU register is accessed, thus `MMR0` to `MMR3` and any of the
`PDR` and `PAR` registers.
This causes test 061 of `ekbee1` to fail.
@@ -11,3 +12,15 @@ The w11 doesn't implement this trap suppression (neither does SimH).
Since MMU traps are a 11/70,11/45 only feature no OS uses them.
Given that, this is considered an acceptable deviation from 11/70 behavior.
Note: the decision whether to request a trap or to update the A and W bits
must be done in the clock cycle in which the MMU translates the virtual
address into a physical address. The w11 determines only in the following
clock cycle whether the physical address is a UNIBUS address and starts an
`ibus` transaction, and the UNIBUS address decoder decision is available in
the respective `IBSEL` registers in the next following cycle. With this
structure, it is not possible to use the available UNIBUS address decoding
information during the MMU decision whether to request a trap or not.
Implementing the 11/70 behavior would require a separate MMU register
detection, which would increase the logic depth at a point that is already
quite long.