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content renames gpr -> gr

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wfjm
2022-10-28 08:48:07 +02:00
parent feff6feca7
commit 792b175100
14 changed files with 251 additions and 238 deletions
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4
doc/CHANGELOG.md
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@@ -29,11 +29,13 @@ The full set of tests is only run for tagged releases.
### Summary
### New features
### Changes
- general changes
- rename _gpr to _gr, use 'general registers' not 'general purpose registers'
### Bug Fixes
<!-- --------------------------------------------------------------------- -->
---
## <a id="w11a_v0.792">2022-04-26: [w11a_V0.792](https://github.com/wfjm/w11/releases/tag/w11a_V0.792) - rev 1307(wfjm)</a>
## <a id="w11a_v0.792">2022-04-25: [w11a_V0.792](https://github.com/wfjm/w11/releases/tag/w11a_V0.792) - rev 1307(wfjm)</a>
### Summary
- retire ancient and unmaintainable tb_pdp11core_stim.dat verification code

61
rtl/w11a/pdp11.vhd
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@@ -1,4 +1,4 @@
-- $Id: pdp11.vhd 1301 2022-10-06 08:53:46Z mueller $
-- $Id: pdp11.vhd 1310 2022-10-27 16:15:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2006-2022 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@@ -11,6 +11,7 @@
--
-- Revision History:
-- Date Rev Version Comment
-- 2022-10-25 1309 1.6.15 rename _gpr -> _gr
-- 2022-10-03 1301 1.6.14 add decode_stat_type.is_dstpcmode1
-- 2022-08-13 1279 1.6.13 ssr->mmr rename
-- 2019-06-02 1159 1.6.12 add rbaddr_ constants
@@ -159,13 +160,13 @@ package pdp11 is
);
type dpath_cntl_type is record -- data path control
gpr_asrc : slv3; -- src register address
gpr_adst : slv3; -- dst register address
gpr_mode : slv2; -- psw mode for gpr access
gpr_rset : slbit; -- register set
gpr_we : slbit; -- gpr write enable
gpr_bytop : slbit; -- gpr high byte enable
gpr_pcinc : slbit; -- pc increment enable
gr_asrc : slv3; -- src register address
gr_adst : slv3; -- dst register address
gr_mode : slv2; -- psw mode for gr access
gr_rset : slbit; -- register set
gr_we : slbit; -- gr write enable
gr_bytop : slbit; -- gr high byte enable
gr_pcinc : slbit; -- pc increment enable
psr_ccwe : slbit; -- enable update cc
psr_we: slbit; -- write enable psw (from DIN)
psr_func : slv3; -- write function psw (from DIN)
@@ -205,7 +206,7 @@ package pdp11 is
end record dpath_cntl_type;
constant dpath_cntl_init : dpath_cntl_type := (
"000","000","00",'0','0','0','0', -- gpr
"000","000","00",'0','0','0','0', -- gr
'0','0',"000", -- psr
'0','0','0','0',"00",'0', -- dsrc,..,dtmp
"00",'0',"000000000","00",'0', -- ounit
@@ -378,7 +379,7 @@ package pdp11 is
trap_mmu : slbit; -- mmu trace trap pending
trap_ysv : slbit; -- ysv trap pending
prefdone : slbit; -- prefetch done
do_gprwe : slbit; -- pending gpr_we
do_grwe : slbit; -- pending gr_we
do_intrsv : slbit; -- active rsv interrupt sequence
end record cpustat_type;
@@ -392,7 +393,7 @@ package pdp11 is
'0','0','0','0', -- itimer,creset,breset,intack
(others=>'0'), -- intvect
'0','0','0', -- trap_(mmu|ysv), prefdone
'0','0' -- do_gprwe, do_intrsv
'0','0' -- do_grwe, do_intrsv
);
type cpuerr_type is record -- CPU error register
@@ -650,10 +651,10 @@ package pdp11 is
dtmp_we : slbit; -- dtmp we
dres : slv16; -- dres bus
cpdout_we : slbit; -- cpdout we
gpr_adst : slv3; -- gpr dst regsiter
gpr_mode : slv2; -- gpr mode
gpr_bytop : slbit; -- gpr bytop
gpr_we : slbit; -- gpr we
gr_adst : slv3; -- gr dst regsiter
gr_mode : slv2; -- gr mode
gr_bytop : slbit; -- gr bytop
gr_we : slbit; -- gr we
end record dm_stat_dp_type;
constant dm_stat_dp_init : dm_stat_dp_type := (
@@ -665,8 +666,8 @@ package pdp11 is
(others=>'0'),'0', -- dtmp,dtmp_we
(others=>'0'), -- dres
'0', -- cpdout_we
(others=>'0'),(others=>'0'), -- gpr_adst, gpr_mode
'0','0' -- gpr_bytop, gpr_we
(others=>'0'),(others=>'0'), -- gr_adst, gr_mode
'0','0' -- gr_bytop, gr_we
);
type dm_stat_vm_type is record -- debug and monitor status - vmbox
@@ -748,14 +749,14 @@ package pdp11 is
constant c_rbaddr_mem : slv5 := "00110"; -- R/W memory access
constant c_rbaddr_memi : slv5 := "00111"; -- R/W memory access; inc addr
constant c_rbaddr_r0 : slv5 := "01000"; -- R/W gpr 0
constant c_rbaddr_r1 : slv5 := "01001"; -- R/W gpr 1
constant c_rbaddr_r2 : slv5 := "01010"; -- R/W gpr 2
constant c_rbaddr_r3 : slv5 := "01011"; -- R/W gpr 3
constant c_rbaddr_r4 : slv5 := "01100"; -- R/W gpr 4
constant c_rbaddr_r5 : slv5 := "01101"; -- R/W gpr 5
constant c_rbaddr_sp : slv5 := "01110"; -- R/W gpr 6 (sp)
constant c_rbaddr_pc : slv5 := "01111"; -- R/W gpr 7 (pc)
constant c_rbaddr_r0 : slv5 := "01000"; -- R/W gr 0
constant c_rbaddr_r1 : slv5 := "01001"; -- R/W gr 1
constant c_rbaddr_r2 : slv5 := "01010"; -- R/W gr 2
constant c_rbaddr_r3 : slv5 := "01011"; -- R/W gr 3
constant c_rbaddr_r4 : slv5 := "01100"; -- R/W gr 4
constant c_rbaddr_r5 : slv5 := "01101"; -- R/W gr 5
constant c_rbaddr_sp : slv5 := "01110"; -- R/W gr 6 (sp)
constant c_rbaddr_pc : slv5 := "01111"; -- R/W gr 7 (pc)
constant c_rbaddr_membe: slv5 := "10000"; -- R/W memory write byte enables
@@ -779,7 +780,7 @@ package pdp11 is
-- -------------------------------------
component pdp11_gpr is -- general purpose registers
component pdp11_gr is -- general registers
port (
CLK : in slbit; -- clock
DIN : in slv16; -- input data
@@ -796,9 +797,9 @@ component pdp11_gpr is -- general purpose registers
);
end component;
constant c_gpr_r5 : slv3 := "101"; -- register number of r5
constant c_gpr_sp : slv3 := "110"; -- register number of SP
constant c_gpr_pc : slv3 := "111"; -- register number of PC
constant c_gr_r5 : slv3 := "101"; -- register number of r5
constant c_gr_sp : slv3 := "110"; -- register number of SP
constant c_gr_pc : slv3 := "111"; -- register number of PC
component pdp11_psr is -- processor status word register
port (
@@ -910,7 +911,7 @@ component pdp11_munit is -- mul/div unit for data (munit)
DSRC : in slv16; -- 'src' data in
DDST : in slv16; -- 'dst' data in
DTMP : in slv16; -- 'tmp' data in
GPR_DSRC : in slv16; -- 'src' data from GPR
GR_DSRC : in slv16; -- 'src' data from GR
FUNC : in slv2; -- function
S_DIV : in slbit; -- s_opg_div state (load dd_low)
S_DIV_CN : in slbit; -- s_opg_div_cn state (1st..16th cycle)

4
rtl/w11a/pdp11_core_rbus.vhd
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@@ -1,4 +1,4 @@
-- $Id: pdp11_core_rbus.vhd 1181 2019-07-08 17:00:50Z mueller $
-- $Id: pdp11_core_rbus.vhd 1310 2022-10-27 16:15:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2007-2019 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@@ -82,7 +82,7 @@
-- 5:00 addr r/w/- addr(21:16)
-- 00110 mem r/w/- memory access
-- 00111 memi r/w/- memory access, inc address
-- 01rrr gpr[] r/w/- general purpose regs
-- 01rrr gr[] r/w/- general regs
-- 10000 membe r/w/- memory write byte enables
-- 3 stick r/w/- sticky flag
-- 1:00 be r/w/- byte enables

15
rtl/w11a/pdp11_decode.vhd
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@@ -1,6 +1,6 @@
-- $Id: pdp11_decode.vhd 1301 2022-10-06 08:53:46Z mueller $
-- $Id: pdp11_decode.vhd 1310 2022-10-27 16:15:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2006-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2006-2022 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
------------------------------------------------------------------------------
-- Module Name: pdp11_decode - syn
@@ -12,6 +12,7 @@
-- Tool versions: ise 8.2-14.7; viv 2014.4-2022.1; ghdl 0.18-2.0.0
-- Revision History:
-- Date Rev Version Comment
-- 2022-10-25 1309 1.0.8 rename _gpr -> _gr
-- 2022-10-03 1301 1.0.7 add STAT.is_dstpcmode1
-- 2011-11-18 427 1.0.6 now numeric_std clean
-- 2010-09-18 300 1.0.5 rename (adlm)box->(oalm)unit
@@ -128,19 +129,19 @@ begin
if DSTMODF = "000" then
nstat.is_dstmode0 := '1';
if DSTREG /= c_gpr_pc then
if DSTREG /= c_gr_pc then
is_dstmode0notpc := '1';
end if;
end if;
if SRCREG = c_gpr_pc then
if SRCREG = c_gr_pc then
nstat.is_srcpc := '1';
if SRCMODF = "001" then
nstat.is_srcpcmode1 := '1';
end if;
end if;
if DSTREG = c_gpr_pc then
if DSTREG = c_gr_pc then
nstat.is_dstpc := '1';
if DSTMODF = "001" then
nstat.is_dstpcmode1 := '1';
@@ -353,7 +354,7 @@ begin
if OPEXT2 = "101" then -- MFP(I/D)
nstat.is_res := '0';
nstat.force_srcsp := '1';
if DSTREG = c_gpr_sp then -- is dst reg == sp ?
if DSTREG = c_gr_sp then -- is dst reg == sp ?
nstat.updt_dstadsrc := '1'; -- ensure DSRC update in dsta flow
end if;
nstat.res_sel := c_dpath_res_ounit;
@@ -548,7 +549,7 @@ begin
if (is_dstw or is_dstm)='1' and nstat.is_dstmode0='1' then
nstat.is_dstw_reg := '1';
if DSTREG = c_gpr_pc then
if DSTREG = c_gr_pc then
nstat.is_dstw_pc := '1'; --??? hack rename -> is_dstw_pc
end if;
end if;

7
rtl/w11a/pdp11_dmcmon.vhd
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@@ -1,6 +1,6 @@
-- $Id: pdp11_dmcmon.vhd 1181 2019-07-08 17:00:50Z mueller $
-- $Id: pdp11_dmcmon.vhd 1310 2022-10-27 16:15:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2015-2019 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2015-2022 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
------------------------------------------------------------------------------
-- Module Name: pdp11_dmcmon- syn
@@ -19,6 +19,7 @@
--
-- Revision History: -
-- Date Rev Version Comment
-- 2022-10-25 1309 2.0.2 rename _gpr -> _gr
-- 2019-06-02 1159 2.0.1 use rbaddr_ constants
-- 2017-04-22 884 2.0 use DM_STAT_SE.idle; revised interface, add suspend
-- 2015-08-03 709 1.0 Initial version
@@ -622,7 +623,7 @@ architecture syn of pdp11_dmcmon is
n.dp_dsrc_we := DM_STAT_DP.dsrc_we;
n.dp_ddst_we := DM_STAT_DP.ddst_we;
n.dp_dres_val := '0';
if ((DM_STAT_DP.gpr_we or DM_STAT_DP.psr_we or -- capture dres only when
if ((DM_STAT_DP.gr_we or DM_STAT_DP.psr_we or -- capture dres only when
DM_STAT_DP.dsrc_we or DM_STAT_DP.ddst_we or -- actually used
DM_STAT_DP.dtmp_we or DM_STAT_DP.cpdout_we or
DM_STAT_VM.vmcntl.req) = '1') then

63
rtl/w11a/pdp11_dpath.vhd
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@@ -1,12 +1,12 @@
-- $Id: pdp11_dpath.vhd 1181 2019-07-08 17:00:50Z mueller $
-- $Id: pdp11_dpath.vhd 1310 2022-10-27 16:15:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2006-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2006-2022 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
------------------------------------------------------------------------------
-- Module Name: pdp11_dpath - syn
-- Description: pdp11: CPU datapath
--
-- Dependencies: pdp11_gpr
-- Dependencies: pdp11_gr
-- pdp11_psr
-- pdp11_ounit
-- pdp11_aunit
@@ -15,10 +15,11 @@
--
-- Test bench: tb/tb_pdp11_core (implicit)
-- Target Devices: generic
-- Tool versions: ise 8.2-14.7; viv 2014.4; ghdl 0.18-0.31
-- Tool versions: ise 8.2-14.7; viv 2014.4-2022.1; ghdl 0.18-2.0.0
--
-- Revision History:
-- Date Rev Version Comment
-- 2022-10-25 1309 1.2.6 rename _gpr -> _gr
-- 2015-07-19 702 1.2.5 set new DM_STAT_DP fields
-- 2014-08-10 581 1.2.4 use c_cc_f_*
-- 2014-07-12 569 1.2.3 use DIV_QUIT and S_DIV_SR for pdp11_munit
@@ -78,9 +79,9 @@ architecture syn of pdp11_dpath is
signal R_CPDOUT : slv16 := (others=>'0'); -- cp dout buffer
signal GPR_DSRC : slv16 := (others=>'0'); --
signal GPR_DDST : slv16 := (others=>'0'); --
signal GPR_PC : slv16 := (others=>'0'); --
signal GR_DSRC : slv16 := (others=>'0'); -- source register
signal GR_DDST : slv16 := (others=>'0'); -- destination register
signal GR_PC : slv16 := (others=>'0'); -- program counter
signal PSW : psw_type := psw_init; --
signal CCIN : slv4 := (others=>'0'); -- cc input to xbox's
@@ -107,19 +108,19 @@ architecture syn of pdp11_dpath is
begin
GPR : pdp11_gpr port map (
GR : pdp11_gr port map (
CLK => CLK,
DIN => DRES,
ASRC => CNTL.gpr_asrc,
ADST => CNTL.gpr_adst,
MODE => CNTL.gpr_mode,
RSET => CNTL.gpr_rset,
WE => CNTL.gpr_we,
BYTOP => CNTL.gpr_bytop,
PCINC => CNTL.gpr_pcinc,
DSRC => GPR_DSRC,
DDST => GPR_DDST,
PC => GPR_PC
ASRC => CNTL.gr_asrc,
ADST => CNTL.gr_adst,
MODE => CNTL.gr_mode,
RSET => CNTL.gr_rset,
WE => CNTL.gr_we,
BYTOP => CNTL.gr_bytop,
PCINC => CNTL.gr_pcinc,
DSRC => GR_DSRC,
DDST => GR_DDST,
PC => GR_PC
);
PSR : pdp11_psr port map(
@@ -139,7 +140,7 @@ begin
DSRC => R_DSRC,
DDST => R_DDST,
DTMP => R_DTMP,
PC => GPR_PC,
PC => GR_PC,
ASEL => CNTL.ounit_asel,
AZERO => CNTL.ounit_azero,
IREG8 => R_IREG(7 downto 0),
@@ -180,7 +181,7 @@ begin
DSRC => R_DSRC,
DDST => R_DDST,
DTMP => R_DTMP,
GPR_DSRC => GPR_DSRC,
GR_DSRC => GR_DSRC,
FUNC => CNTL.munit_func,
S_DIV => CNTL.munit_s_div,
S_DIV_CN => CNTL.munit_s_div_cn,
@@ -242,7 +243,7 @@ begin
if CNTL.dsrc_we = '1' then
if CNTL.dsrc_sel = '0' then
R_DSRC <= GPR_DSRC;
R_DSRC <= GR_DSRC;
else
R_DSRC <= DRES;
end if;
@@ -250,7 +251,7 @@ begin
if CNTL.ddst_we = '1' then
if CNTL.ddst_sel = '0' then
R_DDST <= GPR_DDST;
R_DDST <= GR_DDST;
else
R_DDST <= DRES;
end if;
@@ -258,7 +259,7 @@ begin
if CNTL.dtmp_we = '1' then
case CNTL.dtmp_sel is
when c_dpath_dtmp_dsrc => R_DTMP <= GPR_DSRC;
when c_dpath_dtmp_dsrc => R_DTMP <= GR_DSRC;
when c_dpath_dtmp_psw =>
R_DTMP <= (others=>'0');
R_DTMP(psw_ibf_cmode) <= PSW.cmode;
@@ -302,13 +303,13 @@ begin
end if;
end process proc_cpdout;
proc_vmaddr_sel: process (R_DSRC, R_DDST, R_DTMP, GPR_PC, CNTL)
proc_vmaddr_sel: process (R_DSRC, R_DDST, R_DTMP, GR_PC, CNTL)
begin
case CNTL.vmaddr_sel is
when c_dpath_vmaddr_dsrc => VM_ADDR <= R_DSRC;
when c_dpath_vmaddr_ddst => VM_ADDR <= R_DDST;
when c_dpath_vmaddr_dtmp => VM_ADDR <= R_DTMP;
when c_dpath_vmaddr_pc => VM_ADDR <= GPR_PC;
when c_dpath_vmaddr_pc => VM_ADDR <= GR_PC;
when others => null;
end case;
end process proc_vmaddr_sel;
@@ -316,12 +317,12 @@ begin
STAT.ccout_z <= CCOUT(c_cc_f_z); -- current Z cc flag
PSWOUT <= PSW;
PCOUT <= GPR_PC;
PCOUT <= GR_PC;
IREG <= R_IREG;
VM_DIN <= DRES;
CP_DOUT <= R_CPDOUT;
DM_STAT_DP.pc <= GPR_PC;
DM_STAT_DP.pc <= GR_PC;
DM_STAT_DP.psw <= PSW;
DM_STAT_DP.psr_we <= CNTL.psr_we;
DM_STAT_DP.ireg <= R_IREG;
@@ -334,9 +335,9 @@ begin
DM_STAT_DP.dtmp_we <= CNTL.dtmp_we;
DM_STAT_DP.dres <= DRES;
DM_STAT_DP.cpdout_we <= CNTL.cpdout_we;
DM_STAT_DP.gpr_adst <= CNTL.gpr_adst;
DM_STAT_DP.gpr_mode <= CNTL.gpr_mode;
DM_STAT_DP.gpr_bytop <= CNTL.gpr_bytop;
DM_STAT_DP.gpr_we <= CNTL.gpr_we;
DM_STAT_DP.gr_adst <= CNTL.gr_adst;
DM_STAT_DP.gr_mode <= CNTL.gr_mode;
DM_STAT_DP.gr_bytop <= CNTL.gr_bytop;
DM_STAT_DP.gr_we <= CNTL.gr_we;
end syn;

31
rtl/w11a/pdp11_gr.vhd
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@@ -1,18 +1,19 @@
-- $Id: pdp11_gr.vhd 1309 2022-10-25 15:19:00Z mueller $
-- $Id: pdp11_gr.vhd 1310 2022-10-27 16:15:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2006-2019 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2006-2022 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
------------------------------------------------------------------------------
-- Module Name: pdp11_gpr - syn
-- Description: pdp11: general purpose registers
-- Module Name: pdp11_gr - syn
-- Description: pdp11: general registers
--
-- Dependencies: memlib/ram_1swar_1ar_gen
--
-- Test bench: tb/tb_pdp11_core (implicit)
-- Target Devices: generic
-- Tool versions: ise 8.2-14.7; viv 2014.4-2019.1; ghdl 0.18-0.36
-- Tool versions: ise 8.2-14.7; viv 2014.4-2022.1; ghdl 0.18-2.0.0
-- Revision History:
-- Date Rev Version Comment
-- 2022-10-25 1309 1.0.3 rename _gpr -> _gr
-- 2019-08-17 1203 1.0.2 fix for ghdl V0.36 -Whide warnings
-- 2011-11-18 427 1.0.4 now numeric_std clean
-- 2008-08-22 161 1.0.3 rename ubf_ -> ibf_; use iblib
@@ -32,7 +33,7 @@ use work.pdp11.all;
-- ----------------------------------------------------------------------------
entity pdp11_gpr is -- general purpose registers
entity pdp11_gr is -- general registers
port (
CLK : in slbit; -- clock
DIN : in slv16; -- input data
@@ -47,9 +48,9 @@ entity pdp11_gpr is -- general purpose registers
DDST : out slv16; -- destination register data
PC : out slv16 -- current PC value
);
end pdp11_gpr;
end pdp11_gr;
architecture syn of pdp11_gpr is
architecture syn of pdp11_gr is
-- --------------------------------------
-- the register map determines the internal register file storage address
@@ -79,9 +80,9 @@ architecture syn of pdp11_gpr is
signal PADDR : out slv4 -- internal address in regfile
) is
begin
if PRNUM = c_gpr_pc then
if PRNUM = c_gr_pc then
PADDR <= "1110";
elsif PRNUM = c_gpr_sp then
elsif PRNUM = c_gr_sp then
PADDR <= PMODE(1) & "11" & PMODE(0);
else
PADDR <= PRSET & PRNUM;
@@ -104,7 +105,7 @@ begin
WE1 <= WE and not BYTOP;
GPR_LOW : ram_1swar_1ar_gen
GR_LOW : ram_1swar_1ar_gen
generic map (
AWIDTH => 4,
DWIDTH => 8)
@@ -117,7 +118,7 @@ begin
DOA => MEMDST(ibf_byte0),
DOB => MEMSRC(ibf_byte0));
GPR_HIGH : ram_1swar_1ar_gen
GR_HIGH : ram_1swar_1ar_gen
generic map (
AWIDTH => 4,
DWIDTH => 8)
@@ -134,7 +135,7 @@ begin
alias R_PC15 : slv15 is R_PC(15 downto 1); -- upper 15 bit of PC
begin
if rising_edge(CLK) then
if WE='1' and ADST=c_gpr_pc then
if WE='1' and ADST=c_gr_pc then
R_PC(ibf_byte0) <= DIN(ibf_byte0);
if BYTOP = '0' then
R_PC(ibf_byte1) <= DIN(ibf_byte1);
@@ -145,8 +146,8 @@ begin
end if;
end process proc_pc;
DSRC <= R_PC when ASRC=c_gpr_pc else MEMSRC;
DDST <= R_PC when ADST=c_gpr_pc else MEMDST;
DSRC <= R_PC when ASRC=c_gr_pc else MEMSRC;
DDST <= R_PC when ADST=c_gr_pc else MEMDST;
PC <= R_PC;
end syn;

15
rtl/w11a/pdp11_munit.vhd
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@@ -1,6 +1,6 @@
-- $Id: pdp11_munit.vhd 1181 2019-07-08 17:00:50Z mueller $
-- $Id: pdp11_munit.vhd 1310 2022-10-27 16:15:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2006-2014 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2006-2022 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
------------------------------------------------------------------------------
-- Module Name: pdp11_munit - syn
@@ -9,7 +9,7 @@
-- Dependencies: -
-- Test bench: tb/tb_pdp11_core (implicit)
-- Target Devices: generic
-- Tool versions: ise 8.2-14.7; viv 2014.4; ghdl 0.18-0.31
-- Tool versions: ise 8.2-14.7; viv 2014.4-2022.1; ghdl 0.18-2.0.0
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
@@ -18,6 +18,7 @@
--
-- Revision History:
-- Date Rev Version Comment
-- 2022-10-25 1309 1.2.5 rename _gpr -> _gr
-- 2014-08-10 581 1.2.4 rename NEXT_ to N_; use c_cc_f_*
-- 2014-08-05 578 1.2.3 fix proc_div sensitivity list
-- 2014-08-03 577 1.2.2 use DTMP_POS rather signed(Q)>0 (xst bug for S-3)
@@ -45,7 +46,7 @@ entity pdp11_munit is -- mul/div unit for data (munit)
DSRC : in slv16; -- 'src' data in
DDST : in slv16; -- 'dst' data in
DTMP : in slv16; -- 'tmp' data in
GPR_DSRC : in slv16; -- 'src' data from GPR
GR_DSRC : in slv16; -- 'src' data from GR
FUNC : in slv2; -- function
S_DIV : in slbit; -- s_opg_div state (load dd_low)
S_DIV_CN : in slbit; -- s_opg_div_cn state (1st..16th cycle)
@@ -186,7 +187,7 @@ begin
end process proc_shc;
proc_div: process (DDST, DSRC, DTMP, GPR_DSRC, DR, DD_H, Q,
proc_div: process (DDST, DSRC, DTMP, GR_DSRC, DR, DD_H, Q,
R_DD_L, R_DDO_LT, R_MAXFIX, R_QO_LT, R_DIV_V, R_SHC, R_C1,
S_DIV, S_DIV_CN, S_DIV_CR, S_DIV_SR,
DDST_ZERO, DDST_NMAX, DSRC_ZERO, DTMP_ZERO, DTMP_POS)
@@ -269,9 +270,9 @@ begin
if S_DIV = '1' then
N_DDO_LT <= DD_H(15);
N_DD_L <= GPR_DSRC;
N_DD_L <= GR_DSRC;
N_MAXFIX <= '0';
if DDST_NMAX = '1' and GPR_DSRC = "0000000000000000" then
if DDST_NMAX = '1' and GR_DSRC = "0000000000000000" then
N_MAXFIX <= '1'; -- b_dr_nmax && (ddi_l == 0)
end if;
N_QO_LT <= DD_H(15) xor DR(15); -- b_di_lt ^ b_dr_lt

207
rtl/w11a/pdp11_sequencer.vhd
View File

@@ -1,4 +1,4 @@
-- $Id: pdp11_sequencer.vhd 1301 2022-10-06 08:53:46Z mueller $
-- $Id: pdp11_sequencer.vhd 1310 2022-10-27 16:15:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2006-2022 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@@ -13,6 +13,7 @@
--
-- Revision History:
-- Date Rev Version Comment
-- 2022-10-25 1309 1.6.16 rename _gpr -> _gr
-- 2022-10-03 1301 1.6.15 finalize fix for I space mode=1 in s_dstr_def
-- 2022-09-08 1296 1.6.14 BUGFIX: use I space for all mode=1,2,3 if reg=pc
-- 2022-08-13 1279 1.6.13 ssr->mmr rename
@@ -388,7 +389,7 @@ begin
pndpcntl.vmaddr_sel := c_dpath_vmaddr_pc; -- VA = PC
pnvmcntl.dspace := '0';
pnvmcntl.req := '1';
pndpcntl.gpr_pcinc := '1'; -- (pc)++
pndpcntl.gr_pcinc := '1'; -- (pc)++
pnstate := pwstate;
end procedure do_memread_i;
@@ -423,8 +424,8 @@ begin
if pupdt_sp = '1' then
pnmmumoni.regmod := '1';
pnmmumoni.isdec := '0';
pndpcntl.gpr_adst := c_gpr_sp; -- update SP too
pndpcntl.gpr_we := '1';
pndpcntl.gr_adst := c_gr_sp; -- update SP too
pndpcntl.gr_we := '1';
end if;
pndpcntl.vmaddr_sel := c_dpath_vmaddr_dsrc; -- VA = DSRC
pnvmcntl.dspace := '1';
@@ -475,7 +476,7 @@ begin
begin
pndpcntl := pndpcntl; -- dummy to add driver (vivado)
if pbytop='0' or pisdef='1' or
pregnum=c_gpr_pc or pregnum=c_gpr_sp then
pregnum=c_gr_pc or pregnum=c_gr_sp then
pndpcntl.ounit_const := "000000010";
else
pndpcntl.ounit_const := "000000001";
@@ -563,7 +564,7 @@ begin
R_STATUS.cpususp='0' and -- and not suspended
not R_STATUS.cmdbusy='1' then -- and no cmd pending
pnvmcntl.req := '1'; -- read next instruction
pndpcntl.gpr_pcinc := '1'; -- inc PC
pndpcntl.gr_pcinc := '1' ; -- inc PC
pnmmumoni.istart := '1'; -- signal istart to MMU
pnstate := s_ifetch_w; -- next: wait for fetched instruction
else
@@ -641,7 +642,7 @@ begin
if PSW.cmode = c_psw_kmode then
is_kmode := '1';
if DSTREG = c_gpr_sp and
if DSTREG = c_gr_sp and
(DSTMODF="001" or DSTMODF="010" or
DSTMODF="100" or DSTMODF="110") then
is_dstkstack1246 := '1';
@@ -656,13 +657,13 @@ begin
nvmcntl.intrsv := R_STATUS.do_intrsv; -- DEFAULT
ndpcntl := dpath_cntl_init;
ndpcntl.gpr_asrc := SRCREG; -- DEFAULT
ndpcntl.gpr_adst := DSTREG; -- DEFAULT
ndpcntl.gpr_mode := PSW.cmode; -- DEFAULT
ndpcntl.gpr_rset := PSW.rset; -- DEFAULT
ndpcntl.gpr_we := '0'; -- DEFAULT
ndpcntl.gpr_bytop := '0'; -- DEFAULT
ndpcntl.gpr_pcinc := '0'; -- DEFAULT
ndpcntl.gr_asrc := SRCREG; -- DEFAULT
ndpcntl.gr_adst := DSTREG; -- DEFAULT
ndpcntl.gr_mode := PSW.cmode; -- DEFAULT
ndpcntl.gr_rset := PSW.rset; -- DEFAULT
ndpcntl.gr_we := '0'; -- DEFAULT
ndpcntl.gr_bytop := '0'; -- DEFAULT
ndpcntl.gr_pcinc := '0'; -- DEFAULT
ndpcntl.psr_ccwe := '0'; -- DEFAULT
ndpcntl.psr_we := '0'; -- DEFAULT
@@ -801,15 +802,15 @@ begin
nstate := s_idle;
when c_cpfunc_rreg => -- rreg : read register ------
ndpcntl.gpr_adst := R_STATUS.cprnum;
ndpcntl.gr_adst := R_STATUS.cprnum;
ndpcntl.ddst_sel := c_dpath_ddst_dst;
ndpcntl.ddst_we := '1';
nstate := s_cp_regread;
when c_cpfunc_wreg => -- wreg : write register -----
ndpcntl.dres_sel := c_dpath_res_cpdin; -- DRES = CPDIN
ndpcntl.gpr_adst := R_STATUS.cprnum;
ndpcntl.gpr_we := '1';
ndpcntl.gr_adst := R_STATUS.cprnum;
ndpcntl.gr_we := '1';
nstatus.cmdack := '1';
nstate := s_idle;
@@ -917,7 +918,7 @@ begin
nstatus.itimer := '1'; -- itimer counts each decode
nidstat := ID_STAT; -- register decode status
if ID_STAT.force_srcsp = '1' then
ndpcntl.gpr_asrc := c_gpr_sp;
ndpcntl.gr_asrc := c_gr_sp;
end if;
ndpcntl.dsrc_sel := c_dpath_dsrc_src;
ndpcntl.dsrc_we := '1';
@@ -932,7 +933,7 @@ begin
not R_STATUS.cmdbusy='1'
then
nvmcntl.req := '1';
ndpcntl.gpr_pcinc := '1'; -- (pc)++
ndpcntl.gr_pcinc := '1'; -- (pc)++
nmmumoni.istart := '1';
nstatus.prefdone := '1';
end if;
@@ -1046,8 +1047,8 @@ begin
do_const_opsize(ndpcntl, R_IDSTAT.is_bytop, SRCDEF, SRCREG);
ndpcntl.ounit_bsel := c_ounit_bsel_const; -- OUNIT B=const
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.gpr_adst := SRCREG;
ndpcntl.gpr_we := '1';
ndpcntl.gr_adst := SRCREG;
ndpcntl.gr_we := '1';
nmmumoni.regmod := '1';
nmmumoni.isdec := '0';
ndpcntl.ddst_sel := c_dpath_ddst_res; -- DDST = DRES (for if)
@@ -1085,8 +1086,8 @@ begin
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.dsrc_sel := c_dpath_dsrc_res; -- DSRC = DRES
ndpcntl.dsrc_we := '1'; -- update DSRC
ndpcntl.gpr_adst := SRCREG;
ndpcntl.gpr_we := '1';
ndpcntl.gr_adst := SRCREG;
ndpcntl.gr_we := '1';
nmmumoni.regmod := '1';
nmmumoni.isdec := '1';
ndpcntl.ddst_sel := c_dpath_ddst_res; -- DDST = DRES (for if)
@@ -1207,8 +1208,8 @@ begin
do_const_opsize(ndpcntl, R_IDSTAT.is_bytop, DSTDEF, DSTREG);
ndpcntl.ounit_bsel := c_ounit_bsel_const;-- OUNIT B=const
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.gpr_adst := DSTREG;
ndpcntl.gpr_we := '1';
ndpcntl.gr_adst := DSTREG;
ndpcntl.gr_we := '1';
nmmumoni.regmod := '1';
nmmumoni.isdec := '0';
ndpcntl.vmaddr_sel := c_dpath_vmaddr_ddst; -- VA = DDST
@@ -1239,8 +1240,8 @@ begin
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.ddst_sel := c_dpath_ddst_res; -- DDST = DRES
ndpcntl.ddst_we := '1'; -- update DDST
ndpcntl.gpr_adst := DSTREG;
ndpcntl.gpr_we := '1';
ndpcntl.gr_adst := DSTREG;
ndpcntl.gr_we := '1';
nmmumoni.regmod := '1';
nmmumoni.isdec := '1';
nstate := s_dstr_dec1;
@@ -1359,11 +1360,11 @@ begin
ndpcntl.dres_sel := R_IDSTAT.res_sel; -- DRES = choice of idec
nvmcntl.kstack := is_dstkstack1246;
do_memwrite(nstate, nvmcntl, s_dstw_inc_w, pispace=>R_IDSTAT.is_dstpc);
nstatus.do_gprwe := '1';
nstatus.do_grwe := '1';
else
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.gpr_adst := DSTREG;
ndpcntl.gpr_we := '1';
ndpcntl.gr_adst := DSTREG;
ndpcntl.gr_we := '1';
nmmumoni.regmod := '1';
nmmumoni.isdec := '0';
do_memread_d(nstate, nvmcntl, s_dstw_incdef_w,
@@ -1376,14 +1377,14 @@ begin
do_const_opsize(ndpcntl, R_IDSTAT.is_bytop, DSTDEF, DSTREG);
ndpcntl.ounit_bsel := c_ounit_bsel_const; -- OUNIT B=const
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.gpr_adst := DSTREG;
if R_STATUS.do_gprwe = '1' then
ndpcntl.gr_adst := DSTREG;
if R_STATUS.do_grwe = '1' then
nmmumoni.regmod := '1';
nmmumoni.isdec := '0';
nmmumoni.trace_prev := '1'; -- mmr freeze of prev state
ndpcntl.gpr_we := '1'; -- update DST reg
ndpcntl.gr_we := '1'; -- update DST reg
end if;
nstatus.do_gprwe := '0';
nstatus.do_grwe := '0';
do_memcheck(nstate, nstatus, imemok);
if imemok then
idm_idone := '1'; -- instruction done
@@ -1409,8 +1410,8 @@ begin
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.ddst_sel := c_dpath_ddst_res; -- DDST = DRES
ndpcntl.ddst_we := '1'; -- update DDST
ndpcntl.gpr_adst := DSTREG;
ndpcntl.gpr_we := '1';
ndpcntl.gr_adst := DSTREG;
ndpcntl.gr_we := '1';
nmmumoni.regmod := '1';
nmmumoni.isdec := '1';
nstate := s_dstw_dec1;
@@ -1486,8 +1487,8 @@ begin
ndpcntl.ounit_const := "000000010";
ndpcntl.ounit_bsel := c_ounit_bsel_const; -- OUNIT B=const(2)
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.gpr_adst := DSTREG;
ndpcntl.gpr_we := '1';
ndpcntl.gr_adst := DSTREG;
ndpcntl.gr_we := '1';
nmmumoni.regmod := '1';
nmmumoni.isdec := '0';
ndpcntl.dsrc_sel := c_dpath_dsrc_res; -- DSRC = DRES (for if)
@@ -1520,8 +1521,8 @@ begin
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.ddst_sel := c_dpath_ddst_res; -- DDST = DRES
ndpcntl.ddst_we := '1'; -- update DDST
ndpcntl.gpr_adst := DSTREG;
ndpcntl.gpr_we := '1';
ndpcntl.gr_adst := DSTREG;
ndpcntl.gr_we := '1';
nmmumoni.regmod := '1';
nmmumoni.isdec := '1';
ndpcntl.dsrc_sel := c_dpath_dsrc_res; -- DSRC = DRES (for if)
@@ -1579,7 +1580,7 @@ begin
-- to s_op_wait, waitsusp is cleared here. This ensures that the
-- idm_idone logic (for dmcmon) sees only one WAIT even if it is
-- interrupted by control commands.
ndpcntl.gpr_asrc := "000"; -- load R0 in DSRC for DR emulation
ndpcntl.gr_asrc := "000"; -- load R0 in DSRC for DR emulation
ndpcntl.dsrc_sel := c_dpath_dsrc_src;
ndpcntl.dsrc_we := '1';
nstatus.waitsusp := '0'; -- in case of returning from s_idle
@@ -1617,8 +1618,8 @@ begin
ndpcntl.ounit_asel := c_ounit_asel_ddst; -- OUNIT A=DDST
ndpcntl.ounit_bsel := c_ounit_bsel_const; -- OUNIT B=const(0)
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.gpr_adst := c_gpr_pc;
ndpcntl.gpr_we := '1'; -- load PC with reg(dst)
ndpcntl.gr_adst := c_gr_pc;
ndpcntl.gr_we := '1'; -- load PC with reg(dst)
idm_pcload := '1'; -- signal flow change
nstate := s_op_rts_pop;
@@ -1629,10 +1630,10 @@ begin
when s_op_rts_pop_w => -- -----------------------------------
nstate := s_op_rts_pop_w;
ndpcntl.dres_sel := c_dpath_res_vmdout; -- DRES = VMDOUT
ndpcntl.gpr_adst := DSTREG;
ndpcntl.gr_adst := DSTREG;
do_memcheck(nstate, nstatus, imemok);
if imemok then
ndpcntl.gpr_we := '1'; -- load R with (SP)+
ndpcntl.gr_we := '1'; -- load R with (SP)+
idm_idone := '1'; -- instruction done
do_fork_next(nstate, nstatus, nmmumoni); -- fetch next
end if;
@@ -1684,10 +1685,10 @@ begin
when others => null;
end case;
ndpcntl.gpr_adst := c_gpr_pc;
ndpcntl.gr_adst := c_gr_pc;
idm_idone := '1'; -- instruction done
if brcond = brcode(0) then -- this coding creates redundant code
ndpcntl.gpr_we := '1'; -- but synthesis optimizes this way !
ndpcntl.gr_we := '1'; -- but synthesis optimizes this way !
idm_pcload := '1'; -- signal flow change
do_fork_next(nstate, nstatus, nmmumoni);
else
@@ -1700,7 +1701,7 @@ begin
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.dsrc_sel := c_dpath_dsrc_res; -- DSRC = DRES
ndpcntl.dsrc_we := '1'; -- update DSRC (with PC+2*nn)
ndpcntl.gpr_adst := c_gpr_r5; -- fetch r5
ndpcntl.gr_adst := c_gr_r5; -- fetch r5
ndpcntl.ddst_sel := c_dpath_ddst_dst;
ndpcntl.ddst_we := '1';
nstate := s_op_mark1;
@@ -1709,8 +1710,8 @@ begin
ndpcntl.ounit_asel := c_ounit_asel_ddst; -- OUNIT A = DDST
ndpcntl.ounit_bsel := c_ounit_bsel_const;-- OUNIT B = const(0)
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.gpr_adst := c_gpr_pc;
ndpcntl.gpr_we := '1'; -- load PC with r5
ndpcntl.gr_adst := c_gr_pc;
ndpcntl.gr_we := '1'; -- load PC with r5
idm_pcload := '1'; -- signal flow change
nstate := s_op_mark_pop;
@@ -1721,10 +1722,10 @@ begin
when s_op_mark_pop_w => -- -----------------------------------
nstate := s_op_mark_pop_w;
ndpcntl.dres_sel := c_dpath_res_vmdout; -- DRES = VMDOUT
ndpcntl.gpr_adst := c_gpr_r5;
ndpcntl.gr_adst := c_gr_r5;
do_memcheck(nstate, nstatus, imemok);
if imemok then
ndpcntl.gpr_we := '1'; -- load R5 with (sp)+
ndpcntl.gr_we := '1'; -- load R5 with (sp)+
idm_idone := '1'; -- instruction done
do_fork_next(nstate, nstatus, nmmumoni); -- fetch next
end if;
@@ -1734,8 +1735,8 @@ begin
--nvmcntl.dspace := '0'; -- prepare do_fork_next_pref
--ndpcntl.vmaddr_sel := c_dpath_vmaddr_pc; -- VA = PC
ndpcntl.dres_sel := R_IDSTAT.res_sel;
ndpcntl.gpr_adst := SRCREG;
ndpcntl.gpr_we := '1';
ndpcntl.gr_adst := SRCREG;
ndpcntl.gr_we := '1';
if DP_STAT.ccout_z = '0' then -- if z=0 branch, if z=1 fall thru
nstate := s_op_sob1;
@@ -1750,8 +1751,8 @@ begin
ndpcntl.ounit_bsel := c_ounit_bsel_ireg6;-- OUNIT B = IREG6
ndpcntl.ounit_opsub := '1'; -- OUNIT = A - B
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.gpr_adst := c_gpr_pc;
ndpcntl.gpr_we := '1';
ndpcntl.gr_adst := c_gr_pc;
ndpcntl.gr_we := '1';
idm_pcload := '1'; -- signal flow change
idm_idone := '1'; -- instruction done
do_fork_next(nstate, nstatus, nmmumoni); -- fetch next
@@ -1759,17 +1760,17 @@ begin
when s_opg_gen => -- -----------------------------------
nvmcntl.dspace := '0'; -- prepare do_fork_next_pref
ndpcntl.vmaddr_sel := c_dpath_vmaddr_pc; -- VA = PC
ndpcntl.gpr_bytop := R_IDSTAT.is_bytop;
ndpcntl.gr_bytop := R_IDSTAT.is_bytop;
ndpcntl.dres_sel := R_IDSTAT.res_sel; -- DRES = choice of idec
if R_IDSTAT.op_mov = '1' then -- in case of MOV xx,R
ndpcntl.gpr_bytop := '0'; -- no bytop, do sign extend
ndpcntl.gr_bytop := '0'; -- no bytop, do sign extend
end if;
ndpcntl.psr_ccwe := '1';
if R_IDSTAT.is_dstw_reg = '1' then
ndpcntl.gpr_we := '1';
ndpcntl.gr_we := '1';
end if;
if R_IDSTAT.is_rmwop = '1' then
@@ -1803,8 +1804,8 @@ begin
when s_opg_mul => -- MUL (oper) ------------------------
ndpcntl.dres_sel := R_IDSTAT.res_sel; -- DRES = choice of idec
ndpcntl.gpr_adst := SRCREG; -- write high order result
ndpcntl.gpr_we := '1';
ndpcntl.gr_adst := SRCREG; -- write high order result
ndpcntl.gr_we := '1';
ndpcntl.dsrc_sel := c_dpath_dsrc_res; -- DSRC = DRES
ndpcntl.dsrc_we := '1'; -- capture high order part
ndpcntl.dtmp_sel := c_dpath_dtmp_drese; -- DTMP = DRESE
@@ -1815,15 +1816,15 @@ begin
ndpcntl.ounit_asel := c_ounit_asel_dtmp; -- OUNIT A = DTMP
ndpcntl.ounit_bsel := c_ounit_bsel_const;-- OUNIT B = const(0)
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.gpr_adst := SRCREG(2 downto 1) & "1";-- write odd reg !
ndpcntl.gpr_we := '1';
ndpcntl.gr_adst := SRCREG(2 downto 1) & "1"; -- write odd reg !
ndpcntl.gr_we := '1';
ndpcntl.psr_ccwe := '1';
idm_idone := '1'; -- instruction done
do_fork_next(nstate, nstatus, nmmumoni); -- fetch next
when s_opg_div => -- DIV (load dd_low) -----------------
ndpcntl.munit_s_div := '1';
ndpcntl.gpr_asrc := SRCREG(2 downto 1) & "1";-- read odd reg !
ndpcntl.gr_asrc := SRCREG(2 downto 1) & "1"; -- read odd reg !
ndpcntl.dtmp_sel := c_dpath_dtmp_dsrc;
ndpcntl.dtmp_we := '1';
nstate := s_opg_div_cn;
@@ -1856,8 +1857,8 @@ begin
ndpcntl.ounit_const := "00000000"&DP_STAT.div_cq;-- OUNIT const = Q corr.
ndpcntl.ounit_bsel := c_ounit_bsel_const; -- OUNIT B=const (q cor)
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.gpr_adst := SRCREG; -- write result
ndpcntl.gpr_we := '1';
ndpcntl.gr_adst := SRCREG; -- write result
ndpcntl.gr_we := '1';
ndpcntl.dtmp_sel := c_dpath_dtmp_dres; -- DTMP = DRES
ndpcntl.dtmp_we := '1'; -- update DTMP (Q)
nstate := s_opg_div_sr;
@@ -1867,8 +1868,8 @@ begin
ndpcntl.ounit_asel := c_ounit_asel_dsrc; -- OUNIT A=DSRC
ndpcntl.ounit_bsel := c_ounit_bsel_const; -- OUNIT B=const (0)
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.gpr_adst := SRCREG(2 downto 1) & "1";-- write odd reg !
ndpcntl.gpr_we := '1';
ndpcntl.gr_adst := SRCREG(2 downto 1) & "1"; -- write odd reg !
ndpcntl.gr_we := '1';
ndpcntl.psr_ccwe := '1';
if DP_STAT.div_quit = '1' then
nstate := s_opg_div_quit;
@@ -1891,7 +1892,7 @@ begin
ndpcntl.dsrc_sel := c_dpath_dsrc_res; -- DSRC = DRES
ndpcntl.ounit_asel := c_ounit_asel_dsrc; -- OUNIT A=DSRC
ndpcntl.ounit_bsel := c_ounit_bsel_const; -- OUNIT B=const(0)
ndpcntl.gpr_adst := SRCREG; -- write result
ndpcntl.gr_adst := SRCREG; -- write result
ndpcntl.munit_s_ash_cn := '1';
ndpcntl.vmaddr_sel := c_dpath_vmaddr_pc; -- VA = PC
nstate := s_opg_ash_cn;
@@ -1900,14 +1901,14 @@ begin
ndpcntl.dsrc_we := '1'; -- update DSRC
else
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.gpr_we := '1';
ndpcntl.gr_we := '1';
ndpcntl.psr_ccwe := '1';
idm_idone := '1'; -- instruction done
do_fork_next_pref(nstate, nstatus, ndpcntl, nvmcntl, nmmumoni);
end if;
when s_opg_ashc => -- ASHC (load low, load shc) ---------
ndpcntl.gpr_asrc := SRCREG(2 downto 1) & "1";-- read odd reg !
ndpcntl.gr_asrc := SRCREG(2 downto 1) & "1"; -- read odd reg !
ndpcntl.dtmp_sel := c_dpath_dtmp_dsrc;
ndpcntl.dtmp_we := '1';
ndpcntl.munit_s_ashc := '1';
@@ -1918,7 +1919,7 @@ begin
ndpcntl.dtmp_sel := c_dpath_dtmp_drese; -- DTMP = DRESE
ndpcntl.ounit_asel := c_ounit_asel_dsrc; -- OUNIT A=DSRC
ndpcntl.ounit_bsel := c_ounit_bsel_const; -- OUNIT B=const(0)
ndpcntl.gpr_adst := SRCREG; -- write result
ndpcntl.gr_adst := SRCREG; -- write result
ndpcntl.munit_s_ashc_cn := '1';
nstate := s_opg_ashc_cn;
if DP_STAT.shc_tc = '0' then
@@ -1927,7 +1928,7 @@ begin
ndpcntl.dtmp_we := '1'; -- update DTMP
else
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.gpr_we := '1';
ndpcntl.gr_we := '1';
ndpcntl.psr_ccwe := '1';
nstate := s_opg_ashc_wl;
end if;
@@ -1936,15 +1937,15 @@ begin
ndpcntl.ounit_asel := c_ounit_asel_dtmp; -- OUNIT A = DTMP
ndpcntl.ounit_bsel := c_ounit_bsel_const;-- OUNIT B = const(0)
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.gpr_adst := SRCREG(2 downto 1) & "1";-- write odd reg !
ndpcntl.gpr_we := '1';
ndpcntl.gr_adst := SRCREG(2 downto 1) & "1"; -- write odd reg !
ndpcntl.gr_we := '1';
idm_idone := '1'; -- instruction done
do_fork_next(nstate, nstatus, nmmumoni); -- fetch next
-- dsta mode operations -----------------------------------------------------
when s_opa_jsr => -- -----------------------------------
ndpcntl.gpr_asrc := c_gpr_sp; -- (for else)
ndpcntl.gr_asrc := c_gr_sp; -- (for else)
ndpcntl.dsrc_sel := c_dpath_dsrc_src; -- DSRC = regfile (for else)
if R_IDSTAT.is_dstmode0 = '1' then
nstate := s_trap_10; -- trap 10 like 11/70
@@ -1954,7 +1955,7 @@ begin
end if;
when s_opa_jsr1 => -- -----------------------------------
ndpcntl.gpr_asrc := SRCREG;
ndpcntl.gr_asrc := SRCREG;
ndpcntl.dtmp_sel := c_dpath_dtmp_dsrc; -- DTMP = regfile
ndpcntl.dtmp_we := '1';
@@ -1965,8 +1966,8 @@ begin
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.dsrc_sel := c_dpath_dsrc_res; -- DDST = DRES
ndpcntl.dsrc_we := '1'; -- update DDST
ndpcntl.gpr_adst := c_gpr_sp;
ndpcntl.gpr_we := '1'; -- update SP
ndpcntl.gr_adst := c_gr_sp;
ndpcntl.gr_we := '1'; -- update SP
nmmumoni.regmod := '1';
nmmumoni.isdec := '1';
nstate := s_opa_jsr_push;
@@ -1987,10 +1988,10 @@ begin
ndpcntl.ounit_asel := c_ounit_asel_pc; -- OUNIT A=PC
ndpcntl.ounit_bsel := c_ounit_bsel_const; -- OUNIT B=const(0)
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.gpr_adst := SRCREG;
ndpcntl.gr_adst := SRCREG;
do_memcheck(nstate, nstatus, imemok);
if imemok then
ndpcntl.gpr_we := '1'; -- load R with PC
ndpcntl.gr_we := '1'; -- load R with PC
nstate := s_opa_jsr2;
end if;
@@ -1998,8 +1999,8 @@ begin
ndpcntl.ounit_asel := c_ounit_asel_ddst; -- OUNIT A=DDST
ndpcntl.ounit_bsel := c_ounit_bsel_const; -- OUNIT B=const(0)
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.gpr_adst := c_gpr_pc;
ndpcntl.gpr_we := '1'; -- load PC with dsta
ndpcntl.gr_adst := c_gr_pc;
ndpcntl.gr_we := '1'; -- load PC with dsta
idm_pcload := '1'; -- signal flow change
idm_idone := '1'; -- instruction done
do_fork_next(nstate, nstatus, nmmumoni); -- fetch next
@@ -2008,11 +2009,11 @@ begin
ndpcntl.ounit_asel := c_ounit_asel_ddst; -- OUNIT A=DDST
ndpcntl.ounit_bsel := c_ounit_bsel_const; -- OUNIT B=const(0)
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.gpr_adst := c_gpr_pc;
ndpcntl.gr_adst := c_gr_pc;
if R_IDSTAT.is_dstmode0 = '1' then
nstate := s_trap_10; -- trap 10 like 11/70
else
ndpcntl.gpr_we := '1'; -- load PC with dsta
ndpcntl.gr_we := '1'; -- load PC with dsta
idm_pcload := '1'; -- signal flow change
idm_idone := '1'; -- instruction done
do_fork_next(nstate, nstatus, nmmumoni); -- fetch next
@@ -2049,8 +2050,8 @@ begin
ndpcntl.ounit_bsel := c_ounit_bsel_const; -- OUNIT B = const(0)
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.psr_ccwe := '1'; -- set cc (from ounit too)
ndpcntl.gpr_mode := PSW.pmode; -- load reg in pmode
ndpcntl.gpr_we := '1';
ndpcntl.gr_mode := PSW.pmode; -- load reg in pmode
ndpcntl.gr_we := '1';
idm_idone := '1'; -- instruction done
do_fork_next(nstate, nstatus, nmmumoni); -- fetch next
@@ -2075,7 +2076,7 @@ begin
end if;
when s_opa_mfp_reg => -- -----------------------------------
ndpcntl.gpr_mode := PSW.pmode; -- fetch reg in pmode
ndpcntl.gr_mode := PSW.pmode; -- fetch reg in pmode
ndpcntl.ddst_sel := c_dpath_ddst_dst; -- DDST = reg(dst)
ndpcntl.ddst_we := '1';
nstate := s_opa_mfp_dec;
@@ -2110,8 +2111,8 @@ begin
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.dsrc_sel := c_dpath_dsrc_res; -- DSRC = DRES
ndpcntl.dsrc_we := '1'; -- update DSRC
ndpcntl.gpr_adst := c_gpr_sp;
ndpcntl.gpr_we := '1'; -- update SP
ndpcntl.gr_adst := c_gr_sp;
ndpcntl.gr_we := '1'; -- update SP
nmmumoni.regmod := '1';
nmmumoni.isdec := '1';
nstate := s_opa_mfp_push;
@@ -2205,7 +2206,7 @@ begin
end if;
when s_int_getsp => -- -----------------------------------
ndpcntl.gpr_asrc := c_gpr_sp;
ndpcntl.gr_asrc := c_gr_sp;
ndpcntl.dsrc_we := '1'; -- DSRC = SP (in new mode)
nstate := s_int_decsp;
@@ -2217,8 +2218,8 @@ begin
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.dsrc_sel := c_dpath_dsrc_res; -- DSRC = DRES
ndpcntl.dsrc_we := '1'; -- update DSRC
ndpcntl.gpr_adst := c_gpr_sp;
ndpcntl.gpr_we := '1'; -- update SP too
ndpcntl.gr_adst := c_gr_sp;
ndpcntl.gr_we := '1'; -- update SP too
nstate := s_int_pushps;
when s_int_pushps => -- -----------------------------------
@@ -2239,13 +2240,13 @@ begin
ndpcntl.ounit_opsub := '1'; -- OUNIT = A-B
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.dsrc_sel := c_dpath_dsrc_res; -- DSRC = DRES
ndpcntl.gpr_adst := c_gpr_sp;
ndpcntl.gr_adst := c_gr_sp;
nstate := s_int_pushps_w;
do_memcheck(nstate, nstatus, imemok);
if imemok then
ndpcntl.dsrc_we := '1'; -- update DSRC
ndpcntl.gpr_we := '1'; -- update SP too
ndpcntl.gr_we := '1'; -- update SP too
nstate := s_int_pushpc;
end if;
@@ -2264,13 +2265,13 @@ begin
ndpcntl.ounit_asel := c_ounit_asel_ddst; -- OUNIT A=DDST
ndpcntl.ounit_bsel := c_ounit_bsel_const; -- OUNIT B=const (0)
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.gpr_adst := c_gpr_pc;
ndpcntl.gr_adst := c_gr_pc;
nstate := s_int_pushpc_w;
do_memcheck(nstate, nstatus, imemok);
if imemok then
nstatus.do_intrsv := '0'; -- signal end of rsv
ndpcntl.gpr_we := '1'; -- load new PC
ndpcntl.gr_we := '1'; -- load new PC
idm_pcload := '1'; -- signal flow change
do_fork_next(nstate, nstatus, nmmumoni); -- ???
end if;
@@ -2313,8 +2314,8 @@ begin
ndpcntl.ounit_asel := c_ounit_asel_ddst; -- OUNIT A=DDST
ndpcntl.ounit_bsel := c_ounit_bsel_const; -- OUNIT B=const (0)
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.gpr_adst := c_gpr_pc;
ndpcntl.gpr_we := '1'; -- load new PC
ndpcntl.gr_adst := c_gr_pc;
ndpcntl.gr_we := '1'; -- load new PC
idm_pcload := '1'; -- signal flow change
idm_idone := '1'; -- instruction done
if R_IDSTAT.op_rtt = '1' then -- if RTT instruction
@@ -2333,8 +2334,8 @@ begin
ndpcntl.ounit_const := "000000100"; -- emergency stack pointer
ndpcntl.ounit_bsel := c_ounit_bsel_const; -- OUNIT B=const(vector)
ndpcntl.dres_sel := c_dpath_res_ounit; -- DRES = OUNIT
ndpcntl.gpr_mode := c_psw_kmode; -- set kmode SP to 4
ndpcntl.gpr_adst := c_gpr_sp;
ndpcntl.gr_mode := c_psw_kmode; -- set kmode SP to 4
ndpcntl.gr_adst := c_gr_sp;
nstatus.trap_mmu :='0'; -- drop pending mmu trap
@@ -2351,7 +2352,7 @@ begin
elsif R_VMSTAT.err = '1' then -- normal vm errors
if R_VMSTAT.err_rsv = '1' then
nstatus.do_intrsv := '1'; -- signal start of rsv
ndpcntl.gpr_we := '1';
ndpcntl.gr_we := '1';
if R_VMSTAT.err_odd='1' or R_VMSTAT.err_mmu='1' then
ncpuerr.adderr := '1';
@@ -2422,7 +2423,7 @@ begin
VM_CNTL <= nvmcntl;
VM_CNTL_L <= nvmcntl;
nmmumoni.regnum := ndpcntl.gpr_adst;
nmmumoni.regnum := ndpcntl.gr_adst;
nmmumoni.delta := ndpcntl.ounit_const(3 downto 0);
MMU_MONI <= nmmumoni;

25
rtl/w11a/pdp11_tmu.vhd
View File

@@ -1,6 +1,6 @@
-- $Id: pdp11_tmu.vhd 1181 2019-07-08 17:00:50Z mueller $
-- $Id: pdp11_tmu.vhd 1310 2022-10-27 16:15:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2008-2018 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2008-2022 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
------------------------------------------------------------------------------
-- Module Name: pdp11_tmu - sim
@@ -10,10 +10,11 @@
--
-- Test bench: tb/tb_pdp11_core (implicit)
-- Target Devices: generic
-- Tool versions: viv 2016.2-2018.2; ghdl 0.18-0.34
-- Tool versions: viv 2016.2-2022.1; ghdl 0.18-2.0.0
--
-- Revision History:
-- Date Rev Version Comment
-- 2022-10-25 1309 1.3.2 rename _gpr -> _gr
-- 2018-10-05 1053 1.3.1 use DM_STAT_CA instead of DM_STAT_SY
-- 2016-12-28 833 1.3 open tmu_ofile only when used
-- 2015-07-03 697 1.2.1 adapt to new DM_STAT_SY/DM_STAT_VM
@@ -95,10 +96,10 @@ begin
write(oline, string'(" dp.ddst:o"));
write(oline, string'(" dp.dtmp:o"));
write(oline, string'(" dp.dres:o"));
write(oline, string'(" dp.gpr_adst:o"));
write(oline, string'(" dp.gpr_mode:o"));
write(oline, string'(" dp.gpr_bytop:b"));
write(oline, string'(" dp.gpr_we:b"));
write(oline, string'(" dp.gr_adst:o"));
write(oline, string'(" dp.gr_mode:o"));
write(oline, string'(" dp.gr_bytop:b"));
write(oline, string'(" dp.gr_we:b"));
write(oline, string'(" vm.ibmreq.aval:b"));
write(oline, string'(" vm.ibmreq.re:b"));
@@ -156,7 +157,7 @@ begin
wcycle := false;
if dp_ireg_we_last='1' or
DM_STAT_DP.gpr_we='1' or
DM_STAT_DP.gr_we='1' or
DM_STAT_VM.emmreq.req='1' or
DM_STAT_VM.emsres.ack_r='1' or
DM_STAT_VM.emsres.ack_w='1' or
@@ -191,10 +192,10 @@ begin
writeoct(oline, DM_STAT_DP.ddst, right, 7);
writeoct(oline, DM_STAT_DP.dtmp, right, 7);
writeoct(oline, DM_STAT_DP.dres, right, 7);
writeoct(oline, DM_STAT_DP.gpr_adst, right, 2);
writeoct(oline, DM_STAT_DP.gpr_mode, right, 2);
write(oline, DM_STAT_DP.gpr_bytop, right, 2);
write(oline, DM_STAT_DP.gpr_we, right, 2);
writeoct(oline, DM_STAT_DP.gr_adst, right, 2);
writeoct(oline, DM_STAT_DP.gr_mode, right, 2);
write(oline, DM_STAT_DP.gr_bytop, right, 2);
write(oline, DM_STAT_DP.gr_we, right, 2);
write(oline, DM_STAT_VM.ibmreq.aval, right, 2);
write(oline, DM_STAT_VM.ibmreq.re, right, 2);

9
rtl/w11a/tb/tb_pdp11core.vhd
View File

@@ -1,6 +1,6 @@
-- $Id: tb_pdp11core.vhd 1181 2019-07-08 17:00:50Z mueller $
-- $Id: tb_pdp11core.vhd 1310 2022-10-27 16:15:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2006-2019 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2006-2022 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
------------------------------------------------------------------------------
-- Module Name: tb_pdp11core - sim
@@ -13,7 +13,7 @@
-- To test: pdp11_core
--
-- Target Devices: generic
-- Tool versions: ghdl 0.18-0.31; ISim 14.7
-- Tool versions: ghdl 0.18-2.0.0; ISim 14.7
--
-- Verified (with tb_pdp11core_stim.dat):
-- Date Rev Code ghdl ise Target Comment
@@ -38,6 +38,7 @@
--
-- Revision History:
-- Date Rev Version Comment
-- 2022-10-25 1309 1.5.2 rename _gpr -> _gr
-- 2019-03-17 1123 1.5.1 print header
-- 2015-05-08 675 1.5 start/stop/suspend overhaul
-- 2014-12-26 621 1.4.1 adopt wmembe,ribr,wibr emulation to new 4k window
@@ -473,7 +474,7 @@ begin
-- first a wpc followed by a 'sta'.
when "stapc " => -- stapc
ifunc := c_cpfunc_wreg;
irnum := c_gpr_pc;
irnum := c_gr_pc;
readoct_ea(iline, idin);
idosta := '1'; -- request 'sta' to be done next

37
tools/bin/tmuconv
View File

@@ -1,10 +1,11 @@
#!/usr/bin/perl -w
# $Id: tmuconv 1303 2022-10-17 17:55:51Z mueller $
# $Id: tmuconv 1310 2022-10-27 16:15:50Z mueller $
# SPDX-License-Identifier: GPL-3.0-or-later
# Copyright 2008-2022 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
#
# Revision History:
# Date Rev Version Comment
# 2022-10-25 1309 1.1.9 rename _gpr -> _gr
# 2022-08-22 1283 1.1.8 print ru after em,ib, best for reg from mem cases
# map r6,r7 to sp,pc for rdst,1reg,rsrc instructions
# 2022-07-23 1261 1.1.7 add -emcancel; drop em 'cancel' when -t-ib
@@ -40,10 +41,10 @@
# dp.ddst:o
# dp.dtmp:o
# dp.dres:o
# dp.gpr_adst:o
# dp.gpr_mode:o
# dp.gpr_bytop:b
# dp.gpr_we:b
# dp.gr_adst:o
# dp.gr_mode:o
# dp.gr_bytop:b
# dp.gr_we:b
# vm.ibmreq.aval:b
# vm.ibmreq.re:b
# vm.ibmreq.we:b
@@ -112,10 +113,10 @@ my $ind_dp_ireg;
my $ind_dp_ireg_we;
my $ind_dp_ireg_we_last;
my $ind_dp_dres;
my $ind_dp_gpr_adst;
my $ind_dp_gpr_mode;
my $ind_dp_gpr_bytop;
my $ind_dp_gpr_we;
my $ind_dp_gr_adst;
my $ind_dp_gr_mode;
my $ind_dp_gr_bytop;
my $ind_dp_gr_we;
my $ind_vm_ibmreq_aval;
my $ind_vm_ibmreq_re;
@@ -538,10 +539,10 @@ sub do_file {
$ind_dp_ireg_we = $name{'dp.ireg_we'}->{ind};
$ind_dp_ireg_we_last = $name{'dp.ireg_we_last'}->{ind};
$ind_dp_dres = $name{'dp.dres'}->{ind};
$ind_dp_gpr_adst = $name{'dp.gpr_adst'}->{ind};
$ind_dp_gpr_mode = $name{'dp.gpr_mode'}->{ind};
$ind_dp_gpr_bytop = $name{'dp.gpr_bytop'}->{ind};
$ind_dp_gpr_we = $name{'dp.gpr_we'}->{ind};
$ind_dp_gr_adst = $name{'dp.gr_adst'}->{ind};
$ind_dp_gr_mode = $name{'dp.gr_mode'}->{ind};
$ind_dp_gr_bytop = $name{'dp.gr_bytop'}->{ind};
$ind_dp_gr_we = $name{'dp.gr_we'}->{ind};
$ind_vm_ibmreq_aval = $name{'vm.ibmreq.aval'}->{ind};
$ind_vm_ibmreq_re = $name{'vm.ibmreq.re'}->{ind};
@@ -663,13 +664,13 @@ sub do_file {
# handle t_ru
# uses cycles with dp_gpr_we = '1'
# uses cycles with dp_gr_we = '1'
#
if ($opts{t_ru}) {
if ($val_curr[$ind_dp_gpr_we]) {
my $adst = $val_curr[$ind_dp_gpr_adst];
my $mode = $val_curr[$ind_dp_gpr_mode];
my $bytop = $val_curr[$ind_dp_gpr_bytop];
if ($val_curr[$ind_dp_gr_we]) {
my $adst = $val_curr[$ind_dp_gr_adst];
my $mode = $val_curr[$ind_dp_gr_mode];
my $bytop = $val_curr[$ind_dp_gr_bytop];
my $psw = $val_curr[$ind_dp_psw];
my $dres = $val_curr[$ind_dp_dres];
my $rset = $psw>>11 & 01;

4
tools/tbench/cp/cp_all.dat
View File

@@ -1,8 +1,8 @@
# $Id: cp_all.dat 683 2015-05-17 21:54:35Z mueller $
# $Id: cp_all.dat 1310 2022-10-27 16:15:50Z mueller $
#
## steering file for all cp tests
#
test_cp_gpr.tcl
test_cp_gr.tcl
test_cp_psw.tcl
test_cp_membasics.tcl
test_cp_ibrbasics.tcl

7
tools/tbench/cp/test_cp_gpr.tcl → tools/tbench/cp/test_cp_gr.tcl
View File

@@ -1,19 +1,20 @@
# $Id: test_cp_gpr.tcl 1178 2019-06-30 12:39:40Z mueller $
# $Id: test_cp_gr.tcl 1310 2022-10-27 16:15:50Z mueller $
# SPDX-License-Identifier: GPL-3.0-or-later
# Copyright 2013- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
#
# Revision History:
# Date Rev Version Comment
# 2022-10-27 1309 1.0.1 rename _gpr -> _gr
# 2013-03-31 502 1.0 Initial version
#
# Test that general purpose registers are writable and readable via cp
# Test that general registers are writable and readable via cp
# check all 16 registers, especially that
# set 0 and 1 are distinct
# k,s,u mode sp are distinct
#
# ----------------------------------------------------------------------------
rlc log "test_cp_gpr: test cp access to general purpose registers ------------"
rlc log "test_cp_gr: test cp access to general registers ---------------------"
rlc log " write set 0"
$cpu cp -wps 0000000
$cpu cp -wr0 0000001 \