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wfjm 2023-02-10 12:16:50 +01:00
parent 03ef66e2cb
commit 7a72da83d6
6 changed files with 35 additions and 19 deletions
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11
Makefile
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@ -1,6 +1,6 @@
# $Id: Makefile 1339 2022-12-27 12:11:34Z mueller $
# $Id: Makefile 1371 2023-02-10 11:14:03Z mueller $
# SPDX-License-Identifier: GPL-3.0-or-later
# Copyright 2011-2022 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
# Copyright 2011-2023 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
#
# 'Meta Makefile' for whole retro project
# allows to make all synthesis targets
@ -8,7 +8,8 @@
#
# Revision History:
# Date Rev Version Comment
# 2022-12-27 1388 1.2.14 drop ISE targets except for w11a
# 2023-02-10 1371 1.2.15 add tst_serloop for basys3
# 2022-12-27 1339 1.2.14 drop ISE targets except for w11a
# 2022-06-03 1244 1.2.13 use 3G memory for njobihtm in vivado targets
# 2019-08-07 1201 1.2.12 drop nexys4, add nexys4d
# 2019-01-10 1111 1.2.11 drop w11a/arty_bram
@ -69,7 +70,7 @@ SYN_ise += rtl/sys_gen/w11a/nexys3
# Vivado based targets, by board type --------------------
# Basys3 -------------------------------------
SYN_viv += rtl/sys_gen/tst_snhumanio/basys3
#SYN_viv += rtl/sys_gen/tst_serloop/basys3
SYN_viv += rtl/sys_gen/tst_serloop/basys3
SYN_viv += rtl/sys_gen/tst_rlink/basys3
SYN_viv += rtl/sys_gen/w11a/basys3
@ -131,7 +132,7 @@ SIM_viv += rtl/w11a/tb
# Basys3 -------------------------------------
SIM_viv += rtl/sys_gen/tst_rlink/basys3/tb
#SIM_viv += rtl/sys_gen/tst_serloop/basys3/tb
SIM_viv += rtl/sys_gen/tst_serloop/basys3/tb
SIM_viv += rtl/sys_gen/w11a/basys3/tb
# Nexys4d ------------------------------------

2
doc/CHANGELOG.md
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@ -75,7 +75,7 @@ The full set of tests is only run for tagged releases.
- tools/bin/asm-11:
- BUGFIX: support @(R) modifier with omitted offset
- BUGFIX: misused # and @ don't cause BUGCHECKs anymore
- BUFGIX: expressions: allow uunary after binary operator
- BUFGIX: expressions: allow unary after binary operator
- BUFGIX: proper sign handling for '/','*' operator and .if ge,gt,le,lt
<!-- --------------------------------------------------------------------- -->

2
doc/README_buildsystem_Vivado.md
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@ -268,7 +268,7 @@ Vivado hardware server. Simply use
make <sys>.vconfig
Note: works with Arty, Basys3, Cmod A7, and Nexys4,
Note: works with Arty, Basys3, Cmod A7, Nexys A7, and Nexys4,
only one board must connected.
### <a id="ise">Note on ISE</a>

11
rtl/vlib/genlib/gray_cnt_4.vhd
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@ -1,6 +1,6 @@
-- $Id: gray_cnt_4.vhd 1181 2019-07-08 17:00:50Z mueller $
-- $Id: gray_cnt_4.vhd 1371 2023-02-10 11:14:03Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2007--2017 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2007-2023 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
------------------------------------------------------------------------------
-- Module Name: gray_cnt_4 - syn
@ -9,13 +9,16 @@
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic
-- Tool versions: xst 8.1-14.7; viv 2014.4-2016.4; ghdl 0.18-0.33
-- Tool versions: xst 8.1-14.7; viv 2014.4-2022.1; ghdl 0.18-2.0.0
-- Revision History:
-- Date Rev Version Comment
-- 2017-01-07 840 1.1 disable fsm recognition in vivado
-- 2007-12-26 106 1.0 Initial version
--
-- Some synthesis results:
-- Some synthesis results (after synthesis step):
-- - 2023-02-10 viv 2022.1 for xc7a100tcsg324-1:
-- LUT Flop
-- 4 4
-- - 2007-12-27 ise 8.2.03 for xc3s1000-ft256-4:
-- LUT Flop clock(xst est.)
-- 4 4 365MHz/ 2.76ns

11
rtl/vlib/genlib/gray_cnt_5.vhd
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@ -1,6 +1,6 @@
-- $Id: gray_cnt_5.vhd 1181 2019-07-08 17:00:50Z mueller $
-- $Id: gray_cnt_5.vhd 1371 2023-02-10 11:14:03Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2007-2017 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2007-2023 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
------------------------------------------------------------------------------
-- Module Name: gray_cnt_5 - syn
@ -9,13 +9,16 @@
-- Dependencies: -
-- Test bench: -
-- Target Devices: generic
-- Tool versions: xst 8.1-14.7; viv 2014.4-2016.4; ghdl 0.18-0.33
-- Tool versions: xst 8.1-14.7; viv 2014.4-2022.1; ghdl 0.18-2.0.0
-- Revision History:
-- Date Rev Version Comment
-- 2017-01-07 840 1.1 disable fsm recognition in vivado
-- 2007-12-26 106 1.0 Initial version
--
-- Some synthesis results:
-- Some synthesis results (after synthesis step):
-- - 2023-02-10 viv 2022.1 for xc7a100tcsg324-1:
-- LUT Flop
-- 5 5
-- - 2007-12-27 ise 8.2.03 for xc3s1000-ft256-4:
-- LUT Flop clock(xst est.)
-- 9 5 302MHz/ 3.31ns

17
rtl/vlib/genlib/gray_cnt_n.vhd
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@ -1,6 +1,6 @@
-- $Id: gray_cnt_n.vhd 1181 2019-07-08 17:00:50Z mueller $
-- $Id: gray_cnt_n.vhd 1371 2023-02-10 11:14:03Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2007- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2007-2023 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
------------------------------------------------------------------------------
-- Module Name: gray_cnt_n - syn
@ -9,12 +9,21 @@
-- Dependencies: -
-- Test bench: tb/tb_gray_cnt_n
-- Target Devices: generic
-- Tool versions: xst 8.1-14.7; ghdl 0.18-0.33
-- Tool versions: xst 8.1-14.7; viv 2014.4-2022.1; ghdl 0.18-2.0.0
-- Revision History:
-- Date Rev Version Comment
-- 2007-12-26 106 1.0 Initial version
--
-- Some synthesis results:
-- Some synthesis results (after synthesis step):
-- - 2023-02-10 viv 2022.1 for xc7a100tcsg324-1:
-- DWIDTH LUT Flop
-- 4 5 5
-- 5 6 6
-- 6 8 7
-- 8 10 9
-- 16 24 17
-- 32 52 33
-- 64 105 65
-- - 2016-03-25 ise 14.7 for xc6slx16-csg324-2:
-- DWIDTH LUT Flop clock(xst est.)
-- 4 5 5 421MHz/ 2.37ns