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Some minor updates

Browse Source 
- top-level Makefile: drop w11a/arty_bram
- sys_w11a_s3: set BTOWIDTH 7 (was 6, must be > vmbox atowidth (6))
- RtclGet.ipp: use const& for oper() of string& and Rtime&
- *.Doxyfile: bump version to 0.77
- comment and docu updates
This commit is contained in:
wfjm 2019-02-24 12:50:38 +01:00
parent 4a64a63c4c
commit 8d323848b3
21 changed files with 167 additions and 46 deletions
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5
Makefile
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@ -1,4 +1,4 @@
# $Id: Makefile 1102 2019-01-03 08:46:04Z mueller $
# $Id: Makefile 1111 2019-02-10 16:13:55Z mueller $
#
# 'Meta Makefile' for whole retro project
# allows to make all synthesis targets
@ -6,6 +6,7 @@
#
# Revision History:
# Date Rev Version Comment
# 2019-01-10 1111 1.2.11 drop w11a/arty_bram
# 2019-01-02 1101 1.2.10 add tst_{mig,sram}/arty; add w11a/arty
# 2018-10-12 1055 1.2.9 use setup_package_filt
# 2017-06-28 918 1.2.8 add cmoda7 port for tst_rlink,tst_sram,w11a
@ -79,7 +80,6 @@ SYN_viv += rtl/sys_gen/tst_mig/arty
SYN_viv += rtl/sys_gen/tst_rlink/arty
SYN_viv += rtl/sys_gen/tst_sram/arty
SYN_viv += rtl/sys_gen/w11a/arty
SYN_viv += rtl/sys_gen/w11a/arty_bram
# CmodA7 -------------------------------------
SYN_viv += rtl/sys_gen/tst_rlink/cmoda7
@ -139,7 +139,6 @@ SIM_viv += rtl/sys_gen/tst_mig/arty/tb
SIM_viv += rtl/sys_gen/tst_rlink/arty/tb
SIM_viv += rtl/sys_gen/tst_sram/arty/tb
SIM_viv += rtl/sys_gen/w11a/arty/tb
SIM_viv += rtl/sys_gen/w11a/arty_bram/tb
# CmodA7 -------------------------------------
SIM_viv += rtl/sys_gen/tst_rlink/cmoda7/tb

7
README.md
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@ -8,9 +8,10 @@ The project contains the VHDL code for a **complete DEC PDP-11 system**:
a PDP-11/70 CPU with memory management unit, but without floating point unit,
a complete set of mass storage peripherals
(RK11/RK05, RL11/RL02, RK70/RP06, TM11/TU10)
and a basic set of UNIBUS peripherals
(DL11, LP11, PC11),
and last but not least a cache and memory controllers for SRAM and PSRAM.
and a rather complete set of UNIBUS peripherals
(DL11, LP11, PC11, and DEUNA),
and last but not least a cache and memory controllers for SRAM, PSRAM and
SDRAM (via Xilinx MIG core).
The design is **FPGA proven**, runs currently on
Digilent Arty, Basys3, CmodA7, Nexys4, Nexys3, Nexys2 and S3board boards
and boots 5th Edition UNIX and 2.11BSD UNIX.

18
doc/CHANGELOG.md
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@ -21,6 +21,24 @@ The HEAD version shows the current development. No guarantees that
software or firmware builds or that the documentation is consistent.
The full set of tests is only run for tagged releases.
### Summary
### New features
- new components
- fifo_simple_dram: simple fifo with CE/WE interface, dram based
- simclkv: test bench clock generator with variable period
### Changes
- tools changes
- RtclGet.ipp: use const& for oper() of string& and Rtime&
- firmware changes
- rbd_tester: use now fifo_simple_dram
- sys_w11a_s3: set BTOWIDTH 7 (was 6, must be > vmbox atowidth (6))
### Bug Fixes
### Known issues
<!-- --------------------------------------------------------------------- -->
---
## <a id="w11a_V0.76">2019-02-16: [w11a_V0.76](https://github.com/wfjm/w11/releases/tag/w11a_V0.76) - rev 1108(wfjm)</a>

5
doc/INSTALL_quickstart.md
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@ -65,10 +65,9 @@ All details of the Vivado implementation flow are encapsulated by the
with the currently supported combinations
board btype memory Comment
cmoda7 c7 672 kB Digilent Cmod A7 board
arty_bram br_arty 176 kB Digilent Arty A7-35 board
arty arty 3840 kB Digilent Arty A7-35 board
basys3 b3 176 kB Digilent Basys3 board
nexys4d_bram br_n4d 512 kB Digilent Nexys4 board (DDR RAM)
cmoda7 c7 672 kB Digilent Cmod A7 board
nexys4 n4 3840 kB Digilent Nexys4 board (cellular RAM)
The FPGA is configured via the vivado hardware server with

84
doc/README_known_issues.md
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@ -7,16 +7,68 @@ This file descibes general issues.
The case id indicates the release when the issue was first recognized.
### V0.73-3 {[issue #11](https://github.com/wfjm/w11/issues/11)}
The 'state number generator' code in `pdp11_sequencer` causes in vivado
2016.1 (and .2) that the main FSM isn't re-coded anymore, which has high
impact on achievable clock rate. The two optional debug units depending on
the state number, `dmscnt` and `dmcmon`, are therefore currently deactivated in
all Artix based systems (but are available on all Spartan based systems).
### V0.77-1 {[issue #19](https://github.com/wfjm/w11/issues/19)}
tcl commands like
```
cpu0 get type
cpu0rka get class
rlc get timeout
```
crash with a `SIGSEGV`. Apparently all getters which internally return a
const reference are affected. Observed with gcc 5.4.0. Unclear whether this
is a coding bug introduced when boost::bind was replaced by lambdas
(in commit [1620ee3](https://github.com/wfjm/w11/commit/1620ee3)) or a
compiler issue.
Issue is still in Vivado 2016.4. `dmcmon` can be enabled if wanted, this
might require a reduced clock rate. See procedure given in
[comment to issue #11](https://github.com/wfjm/w11/issues/11).
### V0.76-3 {[issue #18](https://github.com/wfjm/w11/issues/18)}
So far all Series-7 w11a systems ran with 80 MHz clock. The sys_w11_arty
design (with DDR memory support via MIG) also achieves timing closure under
Vivado 2017.2, but fails (with a small negative slack) under Vivado 2018.3.
The failing data path has
```
Source: SYS70/CACHE/CMEM_DAT1/sv_ram_reg_0/DOADO[1]
Destination: SYS70/CACHE/CMEM_DAT3/sv_ram_reg_0/DIADI[1]
via VMBOX->SEQ->OUNIT->SEQ->DPATH->SEQ->VMBOX
```
The connectivity of the multiplexers in `pdp_dpath` in principle allows such
a data flow, but `pdp11_sequencer` will never configure the multiplexers in
such a way. So technically this is a false path.
It seems that the placer strategy changed from Vivado 2017.2 to 2018.3 and
that 2018.3 is less tolerant to the sub-optimal w11a design.
This will be fixed in a future release, either by setting up an appropriate
false_path constraint, or by changing the data path structure.
### V0.76-2 {[issue #17](https://github.com/wfjm/w11/issues/17)}
The w11a design for Arty S7 (50 die size), see rtl/sys_gen/w11a/artys7,
was provided to support also an up-to-date Spartan-7 based board. Turned
out that speed is equivalent to Artix-7. It is so far only simulation tested.
Testing done with a real Arty S7, would be highly appreciated. Please double
check the pin assignments (see _mig_a.prj and artys7*.xdc_) with the
documentation of your board to avoid potential damage.
Looking forward to receive test reports.
### V0.76-1 {[issue #16](https://github.com/wfjm/w11/issues/16)}
The w11a design for Nexys4 DDR, see rtl/sys_gen/w11a/nexys4d, was provided
to support also an up-to-date Nexys4 board. It is so far only simulation tested.
Testing done with a real Nexyx4 DDR, or a newer Nexys A7-100T, would be highly
appreciated. Please double check the pin assignments
(see _mig_a.prj and nexys4d*.xdc_) with the documentation of your board
to avoid potential damage.
Looking forward to receive test reports.
### V0.742-1 {[issue #14](https://github.com/wfjm/w11/issues/14)}
The detach of a `tcp` type virtual terminal or a `tap` type virtual
ethernet device can lead to a SEGFAULT core dump, e.g. after a
`cpu0ttb0 det` command.
This is caused by a race condition between the detach run-down and the
implementation of `ReventLoop::RemovePollHandler()`.
### V0.73-2 {[issue #10](https://github.com/wfjm/w11/issues/10)}
Many post-synthesis functional and especially post-routing timing
@ -78,3 +130,17 @@ rlink command lists aren't split to fit in retransmit buffer size.
_{the last two issues are not relevant for w11 backend over USB usage because
the backend produces proper command lists and the USB channel is usually error
free}_
## Resolved Issues
### V0.73-3 {[issue #11](https://github.com/wfjm/w11/issues/11)}
#### Original Issue
The 'state number generator' code in `pdp11_sequencer` causes in vivado
2016.1 (and .2) that the main FSM isn't re-coded anymore, which has high
impact on achievable clock rate. The two optional debug units depending on
the state number, `dmscnt` and `dmcmon`, are therefore currently deactivated in
all Artix based systems (but are available on all Spartan based systems).
#### Fix
At least mitigated with [d14626c](https://github.com/wfjm/w11/commit/d14626c)
which allows to use `dmcmon` without the full state number generation logic
in `pdp11_sequencer`. Reintroduced `dmcmon` in `sys_w11a_n4` again. `dmscnt` is
still deconfigured for vivado designs, but this has much less practical impact.

1
rtl/bplib/README.md
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@ -17,6 +17,7 @@ and is organized in
| [nexys2](nexys2) | support for Digilent Nexys2 board |
| [nexys3](nexys3) | support for Digilent Nexys3 board |
| [nexys4](nexys4) | support for Digilent Nexys4 board (cram version) |
| [nexys4d](nexys4d) | support for Digilent Nexys4 DDR board |
| [nxcramlib](nxcramlib) | interface for ISSI CRAM |
| [s3board](s3board) | support for Digilent S3BOARD board |
| [sysmon](sysmon) | interface for Xilinx Series-7 sysmon |

4
rtl/ibus/ibdlib.vhd
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@ -1,4 +1,4 @@
-- $Id: ibdlib.vhd 1056 2018-10-13 16:01:17Z mueller $
-- $Id: ibdlib.vhd 1111 2019-02-10 16:13:55Z mueller $
--
-- Copyright 2008-2018 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@ -16,7 +16,7 @@
-- Description: Definitions for ibus devices
--
-- Dependencies: -
-- Tool versions: ise 8.2-14.7; viv 2014.4-2018.2; ghdl 0.18-0.34
-- Tool versions: ise 8.2-14.7; viv 2014.4-2018.3; ghdl 0.18-0.35
-- Revision History:
-- Date Rev Version Comment
-- 2018-10-13 1055 1.3.2 update ibdr_maxisys (add IDEC port)

10
rtl/sys_gen/w11a/README.md
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@ -3,11 +3,15 @@ and is organized in
| Directory | Content |
| --------- | ------- |
| [arty_bram](arty_bram) | design for Digilent Arty A7-35, using BRAM only |
| [arty](arty) | design for Digilent Arty A7-35 (use DDR via MIG) |
| [arty_bram](arty_bram) | design for Digilent Arty A7-35 (use BRAM only) |
| [artys7](artys7) | design for Digilent Arty S7-50 (use DDR via MIG) _!! only sim-tested !!_ |
| [artys7_bram](artys7_bram) | design for Digilent Arty S7-50 (use BRAM only) _!! only sim-tested !!_|
| [basys3](basys3) | design for Digilent Basys3 |
| [cmoda7](cmoda7) | design for Digilent Cmod A7 (35 die size) |
| [nexys2](nexys2) | design for Digilent Nexys2 |
| [nexys3](nexys3) | design for Digilent Nexys3 |
| [nexys4](nexys4) | design for Digilent Nexys4 (old CRAM version !!) |
| [nexys4d_bram](nexys4d_bram) | design for Digilent Nexys4 DDR, using BRAM only **UNTESTED** |
| [nexys4](nexys4) | design for Digilent Nexys4 (old CRAM version) |
| [nexys4d](nexys4d) | design for Digilent Nexys4 DDR (use DDR via MIG) _!! only sim-tested !!_ |
| [nexys4d_bram](nexys4d_bram) | design for Digilent Nexys4 DDR (use BRAM only) _!! only sim-tested !!_ |
| [s3board](s3board) | design for Digilent S3BOARD |

5
rtl/sys_gen/w11a/s3board/sys_w11a_s3.vhd
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@ -1,4 +1,4 @@
-- $Id: sys_w11a_s3.vhd 1108 2019-02-02 23:04:38Z mueller $
-- $Id: sys_w11a_s3.vhd 1112 2019-02-17 11:10:04Z mueller $
--
-- Copyright 2007-2019 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@ -79,6 +79,7 @@
--
-- Revision History:
-- Date Rev Version Comment
-- 2019-02-16 1112 2.2.1 set BTOWIDTH 7 (was 6, must > vmbox atowidth (6))
-- 2018-10-13 1055 2.2 use DM_STAT_EXP; IDEC to maxisys; setup PERFEXT
-- 2016-03-19 748 2.1.1 define rlink SYSID
-- 2015-05-09 677 2.1 start/stop/suspend overhaul; reset overhaul
@ -321,7 +322,7 @@ begin
RLINK : rlink_sp1c -- rlink for serport -----------------
generic map (
BTOWIDTH => 6, -- 64 cycles access timeout
BTOWIDTH => 7, -- 128 cycles access timeout
RTAWIDTH => 12,
SYSID => sysid_proj & sysid_board & sysid_vers,
IFAWIDTH => 5, -- 32 word input fifo

6
rtl/vlib/memlib/fifo_2c_dram.vhd
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@ -1,4 +1,4 @@
-- $Id: fifo_2c_dram.vhd 984 2018-01-02 20:56:27Z mueller $
-- $Id: fifo_2c_dram.vhd 1109 2019-02-09 13:36:41Z mueller $
--
-- Copyright 2007-2011 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@ -22,7 +22,9 @@
--
-- Test bench: tb/tb_fifo_2c_dram
-- Target Devices: generic Spartan, Virtex
-- Tool versions: xst 8.2-14.7; ghdl 0.18-0.33
-- Tool versions: xst 8.2-14.7; ghdl 0.18-0.35 !! NOT FOR VIVADO !!
-- Note: for usage with Vivado use fifo_2c_dram2
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-11-13 424 1.1 use capture+sync flops; reset now glitch free

6
rtl/vlib/memlib/fifo_2c_dram2.vhd
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@ -1,4 +1,4 @@
-- $Id: fifo_2c_dram2.vhd 984 2018-01-02 20:56:27Z mueller $
-- $Id: fifo_2c_dram2.vhd 1109 2019-02-09 13:36:41Z mueller $
--
-- Copyright 2016- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@ -22,7 +22,9 @@
--
-- Test bench: tb/tb_fifo_2c_dram
-- Target Devices: generic
-- Tool versions: viv 2015.4; ghdl 0.33
-- Tool versions: viv 2015.4-2018.3; ghdl 0.33-0.35 !! NOT FOR ISE !!
-- Note: for usage with ISE use fifo_2c_dram
--
-- Revision History:
-- Date Rev Version Comment
-- 2016-03-24 751 1.0 Initial version (derived from fifo_2c_dram, is

4
rtl/w11a/pdp11_vmbox.vhd
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@ -1,4 +1,4 @@
-- $Id: pdp11_vmbox.vhd 984 2018-01-02 20:56:27Z mueller $
-- $Id: pdp11_vmbox.vhd 1112 2019-02-17 11:10:04Z mueller $
--
-- Copyright 2006-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@ -100,6 +100,8 @@ architecture syn of pdp11_vmbox is
constant ibaddr_slim : slv16 := slv(to_unsigned(8#177774#,16));
constant atowidth : natural := 6; -- size of access timeout counter
-- ! rbus tout must be > ibus tout !
-- ! ensure all BTOWIDTH > atowidth !
type state_type is (
s_idle, -- s_idle: wait for vm_cntl request

2
tools/dox/w11_cpp.Doxyfile
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@ -5,7 +5,7 @@
#---------------------------------------------------------------------------
DOXYFILE_ENCODING = UTF-8
PROJECT_NAME = "w11 - cpp"
PROJECT_NUMBER = 0.76
PROJECT_NUMBER = 0.77
PROJECT_BRIEF = "Backend server for Rlink and w11"
PROJECT_LOGO =
OUTPUT_DIRECTORY = $(RETRODOXY)/w11/cpp

2
tools/dox/w11_tcl.Doxyfile
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@ -5,7 +5,7 @@
#---------------------------------------------------------------------------
DOXYFILE_ENCODING = UTF-8
PROJECT_NAME = "w11 - tcl"
PROJECT_NUMBER = 0.76
PROJECT_NUMBER = 0.77
PROJECT_BRIEF = "Backend server for Rlink and w11"
PROJECT_LOGO =
OUTPUT_DIRECTORY = $(RETRODOXY)/w11/tcl

2
tools/dox/w11_vhd_all.Doxyfile
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@ -5,7 +5,7 @@
#---------------------------------------------------------------------------
DOXYFILE_ENCODING = UTF-8
PROJECT_NAME = "w11 - vhd"
PROJECT_NUMBER = 0.76
PROJECT_NUMBER = 0.77
PROJECT_BRIEF = "W11 CPU core and support modules"
PROJECT_LOGO =
OUTPUT_DIRECTORY = $(RETRODOXY)/w11/vhd

20
tools/oskit/README.md Normal file
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@ -0,0 +1,20 @@
This directory tree contains **OS disk/tape image kits** and is organized in
| Directory | Content |
| --------- | ------- |
| [211bsd_rk](211bsd_rk) | 2.11BSD system on RK05 volumes |
| [211bsd_rl](211bsd_rl) | 2.11BSD system on RL02 volumes |
| [211bsd_rp](211bsd_rp) | 2.11BSD system on RP06 volume |
| [211bsd_rpeth](211bsd_rpeth) | 2.11BSD system on RP06 volume with Ethernet |
| [211bsd_rpmin](211bsd_rpmin) | 2.11BSD system on RP06 volume - minimal memory system |
| [211bsd_tm](211bsd_tm) | 2.11BSD system on a TM11 tape distribution kit |
| [doc](doc) | auxiliary documentation |
| [hook](hook) | `ti_w11` startup hook files |
| [rsx11m-31_rk](rsx11m-31_rk) | RSX-11M V3.1 system on RK05 volumes |
| [rsx11m-40_rk](rsx11m-40_rk) | RSX-11M V4.0 system on RK05 volumes |
| [rsx11mp-30_rp](rsx11mp-30_rp) | RSX-11Mpuls V3.0 system on RP06 volume |
| [rt11-40_rk](rt11-40_rk) | RT-11 V4.0 system on RK05 volumes |
| [rt11-53_rl](rt11-53_rl) | RT-11 V5.3 system on a RL02 volume |
| [u5ed_rk](u5ed_rk) | Unix 5th Edition system on RK05 volumes |
| [u7ed_rp](u7ed_rp) | Unix 7th Edition system on RP04 volume |
| [xxdp_rl](xxdp_rl) | XXDP V2.2 and V2.5 system on RL02 volumes |

2
tools/oskit/rsx11mp-30_rp/README.md
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@ -1,4 +1,4 @@
## Notes on oskit: RSX-11Mplus V3.0 system on RP06 volumes
## Notes on oskit: RSX-11Mplus V3.0 system on a RP06 volume
### General remarks

2
tools/oskit/rt11-53_rl/README.md
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@ -1,4 +1,4 @@
##Notes on oskit: RT-11 V5.3 system on a RL02 volume
## Notes on oskit: RT-11 V5.3 system on a RL02 volume
### General remarks

2
tools/oskit/u7ed_rp/README.md
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@ -1,4 +1,4 @@
## Notes on oskit: Unix 7th Edition system on RP04 volumes
## Notes on oskit: Unix 7th Edition system on a RP04 volume
### Proviso

10
tools/src/librtcltools/RtclGet.ipp
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@ -1,6 +1,6 @@
// $Id: RtclGet.ipp 1091 2018-12-23 12:38:29Z mueller $
// $Id: RtclGet.ipp 1112 2019-02-17 11:10:04Z mueller $
//
// Copyright 2013-2018 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
// Copyright 2013-2019 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
//
// This program is free software; you may redistribute and/or modify it under
// the terms of the GNU General Public License as published by the Free
@ -13,6 +13,7 @@
//
// Revision History:
// Date Rev Version Comment
// 2019-02-16 1112 1.2.5 use const& for oper() of string& and Rtime&
// 2018-12-22 1091 1.2.4 <float> add float cast (-Wdouble-promotion fix)
// 2018-12-18 1089 1.2.3 use c++ style casts
// 2018-12-15 1083 1.2.2 ctor: use rval ref and move semantics
@ -33,6 +34,7 @@
*/
#include "librtools/Rtime.hpp"
#include <iostream>
// all method definitions in namespace Retro
namespace Retro {
@ -188,7 +190,7 @@ inline Tcl_Obj* RtclGet<std::string>::operator()() const
template <>
inline Tcl_Obj* RtclGet<const std::string&>::operator()() const
{
std::string val = fGet();
const std::string& val = fGet();
return Tcl_NewStringObj(val.data(), val.length());
}
@ -208,7 +210,7 @@ inline Tcl_Obj* RtclGet<Rtime>::operator()() const
template <>
inline Tcl_Obj* RtclGet<const Rtime&>::operator()() const
{
Rtime val = fGet();
const Rtime& val = fGet();
return Tcl_NewDoubleObj(double(val));
}

16
tools/tbench/README.md
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@ -2,9 +2,13 @@ This directory tree contains the **w11 test bench** and is organized in
| Directory | Content |
| --------- | ------- |
| [cp](cp) | test of CPU control port |
| [rhrp](rhrp) | test of `rhrp` ibus device |
| [tm11](tm11) | test of `tm11` ibus devive |
| [w11a](w11a) | test of CPU core |
| [w11a_cmon](w11a_cmon) | test of CPU `cmon` unit (cpu monitor) |
| [w11a_hbpt](w11a_hbpt) | test of CPU `hbpt` unit (hardware breakpoint) |
| [cp](cp) | test of CPU control port |
| [deuna](deuna) | test of `deuna` ibus device |
| [rhrp](rhrp) | test of `rhrp` ibus device |
| [tm11](tm11) | test of `tm11` ibus device |
| [w11a](w11a) | test of CPU core |
| [w11a_cmon](w11a_cmon) | test of CPU `cmon` unit (cpu monitor) |
| [w11a_hbpt](w11a_hbpt) | test of CPU `hbpt` unit (hardware breakpoint) |
| [w11a_ibtst](w11a_ibtst) | test of `ibd_ibtst` (ibus test device) |
| [w11a_kw11p](w11a_kw11p) | test of `kw11p` ibus device (programmable clock) |
| [w11a_pcnt](w11a_pcnt) | test of CPU `pcnt` unit (performance counters) |