github.com/wfjm.w11
1
0
Fork 0
mirror of https://github.com/wfjm/w11.git synced 2026-03-30 19:59:04 +00:00
Code Issues Releases Wiki Activity

revise interface for ibd_ibmon and rbd_rbmon

Browse Source 
- use start,stop,suspend,resume functions; improved stop on wrap handling
  - add 'repeat collapse' logic (store only first and last of a sequence)
This commit is contained in:
Walter F.J. Mueller
2017-04-09 22:56:23 +02:00
parent 1ac2d8bfbf
commit 8e6d604de4
8 changed files with 641 additions and 169 deletions
Download Patch File Download Diff File Expand all files Collapse all files

8
doc/CHANGELOG.md
View File

@@ -14,9 +14,15 @@
### Proviso
_The HEAD version shows the current development. No guarantees that
software or firmware builds or that the documentation is consistent.
The full set of tests is only run for tagged releases._
The full set of tests is only run for tagged releases.
### Summary
- revise interface for ibd_ibmon and rbd_rbmon
- use start,stop,suspend,resume functions; improved stop on wrap handling
- add 'repeat collapse' logic (store only first and last of a sequence)
- BUGFIX: `rlc get logfile` or `rlc get *` crashed with segfault
- error was a type mismatch in the getter declaration in RtclRlinkConnect
- fixed by changing the return type in RlinkConnect
- remove double inheritance in RtclRw11Unit* stack
- RtclRw11Unit: drop fpCpu, use added Cpu()=0 instead
- RtclRw11UnitBase: add TUV,TB; add TUV* ObjUV(); inherit from TB

186
rtl/ibus/ibd_ibmon.vhd
View File

@@ -1,6 +1,6 @@
-- $Id: ibd_ibmon.vhd 697 2015-07-05 14:23:26Z mueller $
-- $Id: ibd_ibmon.vhd 872 2017-04-09 20:48:05Z mueller $
--
-- Copyright 2015- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2015-2017 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
@@ -20,29 +20,40 @@
-- Test bench: -
--
-- Target Devices: generic
-- Tool versions: xst 14.7; viv 2014.4; ghdl 0.31
-- Tool versions: xst 14.7; viv 2014.4-2016.4; ghdl 0.31-0.34
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2017-04-09 872 14.7 131013 xc6slx16-2 134 203 0 80 s 5.5
-- 2015-04-24 668 14.7 131013 xc6slx16-2 112 235 0 83 s 5.6
--
-- Revision History:
-- Date Rev Version Comment
-- 2017-04-09 872 2.0 revised interface, add suspend and repeat collapse
-- 2017-03-04 858 1.0.2 BUGFIX: wrap set when go=0 due to wena=0
-- 2015-05-02 672 1.0.1 use natural for AWIDTH to work around a ghdl issue
-- 2015-04-24 668 1.0 Initial version (derived from rbd_rbmon)
------------------------------------------------------------------------------
--
-- Addr Bits Name r/w/f Function
-- 000 cntl r/w/f Control register
-- 08 rcolw r/w/- repeat collapse writes
-- 07 rcolr r/w/- repeat collapse reads
-- 06 wstop r/w/- stop on wrap
-- 05 conena r/w/- con enable
-- 04 remena r/w/- rem enable
-- 03 locena r/w/- loc enable
-- 02 wena r/w/- wrap enable
-- 01 stop r/w/f writing 1 stops moni
-- 00 start r/w/f writing 1 starts moni and clears addr
-- 02:00 func 0/-/f change run status if != noop
-- 0xx noop
-- 100 sto stop
-- 101 sta start and latch all options
-- 110 sus suspend (noop if not started)
-- 111 res resume (noop if not started)
-- 001 stat r/w/- Status register
-- 15:13 bsize r/-/- buffer size (AWIDTH-9)
-- 00 wrap r/-/- line address wrapped (cleared on go)
-- 02 wrap r/-/- line address wrapped (cleared on start)
-- 01 susp r/-/- suspended
-- 00 run r/-/- running (can be suspended)
-- 010 12:01 hilim r/w/- upper address limit, inclusive (def: 177776)
-- 011 12:01 lolim r/w/- lower address limit, inclusive (def: 160000)
-- 100 addr r/w/- Address register
@@ -106,14 +117,19 @@ architecture syn of ibd_ibmon is
constant ibaddr_addr : slv3 := "100"; -- addr address offset
constant ibaddr_data : slv3 := "101"; -- data address offset
constant cntl_ibf_rcolw : integer := 8;
constant cntl_ibf_rcolr : integer := 7;
constant cntl_ibf_wstop : integer := 6;
constant cntl_ibf_conena : integer := 5;
constant cntl_ibf_remena : integer := 4;
constant cntl_ibf_locena : integer := 3;
constant cntl_ibf_wena : integer := 2;
constant cntl_ibf_stop : integer := 1;
constant cntl_ibf_start : integer := 0;
subtype cntl_ibf_func is integer range 2 downto 0;
subtype stat_ibf_bsize is integer range 15 downto 13;
constant stat_ibf_wrap : integer := 0;
constant stat_ibf_wrap : integer := 2;
constant stat_ibf_susp : integer := 1;
constant stat_ibf_run : integer := 0;
subtype addr_ibf_laddr is integer range 2+AWIDTH-1 downto 2;
subtype addr_ibf_waddr is integer range 1 downto 0;
@@ -136,19 +152,36 @@ architecture syn of ibd_ibmon is
subtype dat0_ibf_addr is integer range 12 downto 1;
constant dat0_ibf_cacc : integer := 0;
constant func_sto : slv3 := "100"; -- func: stop
constant func_sta : slv3 := "101"; -- func: start
constant func_sus : slv3 := "110"; -- func: suspend
constant func_res : slv3 := "111"; -- func: resume
type regs_type is record -- state registers
ibsel : slbit; -- ibus select
ibsel : slbit; -- ibus select
rcolw : slbit; -- rcolw flag (repeat collect writes)
rcolr : slbit; -- rcolr flag (repeat collect reads)
wstop : slbit; -- wstop flag (stop on wrap)
conena : slbit; -- conena flag (record console access)
remena : slbit; -- remena flag (record remote access)
locena : slbit; -- locena flag (record local access)
wena : slbit; -- wena flag (wrap enable)
go : slbit; -- go flag
hilim : slv13_1; -- upper address limit
lolim : slv13_1; -- lower address limit
wrap : slbit; -- laddr wrap flag
laddr : slv(AWIDTH-1 downto 0); -- line address
waddr : slv2; -- word address
ibtake_1 : slbit; -- ib capture active in last cycle
susp : slbit; -- suspended flag
go : slbit; -- go flag (actively running)
hilim : slv13_1; -- upper address limit
lolim : slv13_1; -- lower address limit
wrap : slbit; -- laddr wrap flag
laddr : slv(AWIDTH-1 downto 0); -- line address
waddr : slv2; -- word address
addrlast: slv13_1; -- last ib addr
addrsame: slbit; -- curr ib addr equal last ib addr
addrwind: slbit; -- curr ib addr in [lolim,hilim] window
aval_1 : slbit; -- last cycle aval
arm1r : slbit; -- 1st level arm for read
arm2r : slbit; -- 2nd level arm for read
arm1w : slbit; -- 1st level arm for write
arm2w : slbit; -- 2nd level arm for write
rcol : slbit; -- repeat collaps
ibtake_1: slbit; -- ib capture active in last cycle
ibaddr : slv13_1; -- ibus trace: addr
ibwe : slbit; -- ibus trace: we
ibrmw : slbit; -- ibus trace: rmw
@@ -171,12 +204,17 @@ architecture syn of ibd_ibmon is
constant regs_init : regs_type := (
'0', -- ibsel
'1','1','1','1','1', -- conena,remena,locena,wena,go
'0','0','0', -- rcolw,rcolr,wstop
'1','1','1', -- conena,remena,locena
'0','1', -- susp,go
(others=>'1'), -- hilim (def: 177776)
(others=>'0'), -- lolim (def: 160000)
'0', -- wrap
laddrzero, -- laddr
"00", -- waddr
(others=>'0'), -- addrlast (startup: 160000)
'0','0','0', -- addrsame,addrwind,aval_1
'0','0','0','0','0', -- arm1r,arm2r,arm1w,arm2w,rcol
'0', -- ibtake_1
(others=>'0'), -- ibaddr
'0','0','0','0','0','0', -- ibwe,ibrmw,ibbe0,ibbe1,ibcacc,ibracc
@@ -199,6 +237,7 @@ architecture syn of ibd_ibmon is
signal BRAM1_DI : slv32 := (others=>'0');
signal BRAM0_DO : slv32 := (others=>'0');
signal BRAM1_DO : slv32 := (others=>'0');
signal BRAM_ADDR : slv(AWIDTH-1 downto 0) := (others=>'0');
begin
@@ -214,7 +253,7 @@ begin
CLK => CLK,
EN => BRAM_EN,
WE => BRAM_WE,
ADDR => R_REGS.laddr,
ADDR => BRAM_ADDR,
DI => BRAM1_DI,
DO => BRAM1_DO
);
@@ -227,7 +266,7 @@ begin
CLK => CLK,
EN => BRAM_EN,
WE => BRAM_WE,
ADDR => R_REGS.laddr,
ADDR => BRAM_ADDR,
DI => BRAM0_DI,
DO => BRAM0_DO
);
@@ -258,6 +297,8 @@ begin
variable idat1 : slv16 := (others=>'0');
variable idat2 : slv16 := (others=>'0');
variable idat3 : slv16 := (others=>'0');
variable iaddrinc : slv(AWIDTH-1 downto 0) := (others=>'0');
variable iaddroff : slv(AWIDTH-1 downto 0) := (others=>'0');
begin
r := R_REGS;
@@ -281,6 +322,21 @@ begin
ibramen := '1'; -- ensures bram read before ibus read
end if;
-- ibus address monitor
if IB_MREQ.aval='1' and r.aval_1='0' then
n.addrlast := IB_MREQ.addr;
n.addrsame := '0';
if IB_MREQ.addr = r.addrlast then
n.addrsame := '1';
end if;
n.addrwind := '0';
if unsigned(IB_MREQ.addr)>=unsigned(r.lolim) and -- and in addr window
unsigned(IB_MREQ.addr)<=unsigned(r.hilim) then
n.addrwind := '1';
end if;
end if;
n.aval_1 := IB_MREQ.aval;
-- ibus transactions (react only on console (this includes racc))
if r.ibsel = '1' and IB_MREQ.cacc='1' then
@@ -289,20 +345,31 @@ begin
case IB_MREQ.addr(3 downto 1) is
when ibaddr_cntl => -- cntl ------------------
if IB_MREQ.we = '1' then
n.conena := IB_MREQ.din(cntl_ibf_conena);
n.remena := IB_MREQ.din(cntl_ibf_remena);
n.locena := IB_MREQ.din(cntl_ibf_locena);
n.wena := IB_MREQ.din(cntl_ibf_wena);
if IB_MREQ.din(cntl_ibf_start) = '1' then
n.go := '1';
n.wrap := '0';
n.laddr := laddrzero;
n.waddr := "00";
end if;
if IB_MREQ.din(cntl_ibf_stop) = '1' then
n.go := '0';
end if;
if IB_MREQ.we = '1' then
case IB_MREQ.din(cntl_ibf_func) is
when func_sto => -- func: stop ------------
n.go := '0';
n.susp := '0';
when func_sta => -- func: start -----------
n.rcolw := IB_MREQ.din(cntl_ibf_rcolw);
n.rcolr := IB_MREQ.din(cntl_ibf_rcolr);
n.wstop := IB_MREQ.din(cntl_ibf_wstop);
n.conena := IB_MREQ.din(cntl_ibf_conena);
n.remena := IB_MREQ.din(cntl_ibf_remena);
n.locena := IB_MREQ.din(cntl_ibf_locena);
n.go := '1';
n.susp := '0';
n.wrap := '0';
n.laddr := laddrzero;
n.waddr := "00";
when func_sus => -- func: susp ------------
n.go := '0';
n.susp := r.go;
when func_res => -- func: resu ------------
n.go := r.susp;
n.susp := '0';
when others => null; -- <> --------------------
end case;
end if;
when ibaddr_stat => null; -- stat ------------------
@@ -346,14 +413,17 @@ begin
if r.ibsel = '1' then
case IB_MREQ.addr(3 downto 1) is
when ibaddr_cntl => -- cntl ------------------
iib_dout(cntl_ibf_rcolw) := r.rcolw;
iib_dout(cntl_ibf_rcolr) := r.rcolr;
iib_dout(cntl_ibf_wstop) := r.wstop;
iib_dout(cntl_ibf_conena) := r.conena;
iib_dout(cntl_ibf_remena) := r.remena;
iib_dout(cntl_ibf_locena) := r.locena;
iib_dout(cntl_ibf_wena) := r.wena;
iib_dout(cntl_ibf_start) := r.go;
when ibaddr_stat => -- stat ------------------
iib_dout(stat_ibf_bsize) := slv(to_unsigned(AWIDTH-9,3));
iib_dout(stat_ibf_wrap) := r.wrap;
iib_dout(stat_ibf_susp) := r.susp; -- started and suspended
iib_dout(stat_ibf_run) := r.go or r.susp; -- started
when ibaddr_hilim => -- hilim -----------------
iib_dout(iba_ibf_pref) := (others=>'1');
iib_dout(iba_ibf_addr) := r.hilim;
@@ -380,10 +450,8 @@ begin
-- and the access is not refering to ibd_ibmon itself
ibtake := '0';
if IB_MREQ.aval='1' and iibena='1' then -- aval and (re or we)
if unsigned(IB_MREQ.addr)>=unsigned(r.lolim) and -- and in addr window
unsigned(IB_MREQ.addr)<=unsigned(r.hilim) and
r.ibsel='0' then -- and not self
if IB_MREQ.aval='1' and iibena='1' then -- aval and (re or we)
if r.addrwind='1' and r.ibsel='0' then -- and in window and not self
if (r.locena='1' and IB_MREQ.cacc='0' and IB_MREQ.racc='0') or
(r.remena='1' and IB_MREQ.racc='1') or
(r.conena='1' and IB_MREQ.cacc='1') then
@@ -418,6 +486,15 @@ begin
n.ibnak := not IB_SRES_SUM.ack;
n.ibtout := IB_SRES_SUM.busy;
if IB_SRES_SUM.busy = '0' then -- if last cycle of a transaction
n.arm1r := r.rcolr and IB_MREQ.re;
n.arm1w := r.rcolw and IB_MREQ.we;
n.arm2r := r.arm1r and r.addrsame and IB_MREQ.re;
n.arm2w := r.arm1w and r.addrsame and IB_MREQ.we;
n.rcol := ((r.arm2r and IB_MREQ.re) or
(r.arm2w and IB_MREQ.we)) and r.addrsame;
end if;
else -- if capture not active
if r.go='1' and r.ibtake_1='1' then -- active and transaction just ended
ibramen := '1';
@@ -437,13 +514,17 @@ begin
if IB_MREQ.aval = '0' then -- if aval gone
n.ibburst := '0'; -- clear burst flag
end if;
iaddrinc := (others=>'0');
iaddroff := (others=>'0');
iaddrinc(0) := not (r.rcol and r.go);
iaddroff(0) := (r.rcol and r.go);
if laddr_inc = '1' then
n.laddr := slv(unsigned(r.laddr) + 1);
n.laddr := slv(unsigned(r.laddr) + unsigned(iaddrinc));
if r.go='1' and r.laddr=laddrlast then
if r.wena = '1' then
n.wrap := '1';
else
n.wrap := '1';
if r.wstop = '1' then
n.go := '0';
end if;
end if;
@@ -471,11 +552,12 @@ begin
N_REGS <= n;
BRAM_EN <= ibramen;
BRAM_WE <= ibramwe;
BRAM1_DI <= idat3 & idat2;
BRAM0_DI <= idat1 & idat0;
BRAM_EN <= ibramen;
BRAM_WE <= ibramwe;
BRAM_ADDR <= slv(unsigned(R_REGS.laddr) - unsigned(iaddroff));
BRAM1_DI <= idat3 & idat2;
BRAM0_DI <= idat1 & idat0;
IB_SRES.dout <= iib_dout;
IB_SRES.ack <= iib_ack;

162
rtl/vlib/rbus/rbd_rbmon.vhd
View File

@@ -1,6 +1,6 @@
-- $Id: rbd_rbmon.vhd 758 2016-04-02 18:01:39Z mueller $
-- $Id: rbd_rbmon.vhd 872 2017-04-09 20:48:05Z mueller $
--
-- Copyright 2010-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
-- Copyright 2010-2017 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
@@ -20,16 +20,19 @@
-- Test bench: rlink/tb/tb_rlink_tba_ttcombo
--
-- Target Devices: generic
-- Tool versions: xst 12.1-14.7; viv 2014.4-2015.4; ghdl 0.29-0.33
-- Tool versions: xst 12.1-14.7; viv 2014.4-2016.4; ghdl 0.29-0.34
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2017-04-09 872 14.7 131013 xc6slx16-2 140 202 - 82 s 5.9
-- 2017-04-08 758 14.7 131013 xc6slx16-2 112 200 - 73 s 5.7
-- 2014-12-22 619 14.7 131013 xc6slx16-2 114 209 - 72 s 5.6
-- 2014-12-21 593 14.7 131013 xc6slx16-2 99 207 - 77 s 7.0
-- 2010-12-27 349 12.1 M53d xc3s1000-4 95 228 - 154 s 10.4
--
-- Revision History:
-- Date Rev Version Comment
-- 2017-04-09 872 6.0 revised interface, add suspend and repeat collapse
-- 2015-05-02 672 5.0.1 use natural for AWIDTH to work around a ghdl issue
-- 2014-12-22 619 5.0 reorganized, supports now 16 bit addresses
-- 2014-09-13 593 4.1 change default address -> ffe8
@@ -42,12 +45,20 @@
--
-- Addr Bits Name r/w/f Function
-- 000 cntl r/w/f Control register
-- 02 wena r/w/- wrap enable
-- 01 stop r/w/f writing 1 stops moni
-- 00 start r/w/f writing 1 starts moni and clears addr
-- 05 rcolw r/w/- repeat collapse writes
-- 04 rcolr r/w/- repeat collapse reads
-- 03 wstop r/w/- stop on wrap
-- 02:00 func 0/-/f change run status if != noop
-- 0xx noop
-- 100 sto stop
-- 101 sta start and latch all options
-- 110 sus suspend (noop if not started)
-- 111 res resume (noop if not started)
-- 001 stat r/w/- Status register
-- 15:13 bsize r/-/- buffer size (AWIDTH-9)
-- 00 wrap r/-/- line address wrapped (cleared on go)
-- 02 wrap r/-/- line address wrapped (cleared on start)
-- 01 susp r/-/- suspended
-- 00 run r/-/- running (can be suspended)
-- 010 hilim r/w/- upper address limit, inclusive (def: 0xfffb)
-- 011 lolim r/w/- lower address limit, inclusive (def: 0x0000)
-- 100 addr r/w/- Address register
@@ -107,11 +118,16 @@ architecture syn of rbd_rbmon is
constant rbaddr_addr : slv3 := "100"; -- addr address offset
constant rbaddr_data : slv3 := "101"; -- data address offset
constant cntl_rbf_wena : integer := 2;
constant cntl_rbf_stop : integer := 1;
constant cntl_rbf_start : integer := 0;
constant cntl_rbf_rcolw : integer := 5;
constant cntl_rbf_rcolr : integer := 4;
constant cntl_rbf_wstop : integer := 3;
subtype cntl_rbf_func is integer range 2 downto 0;
subtype stat_rbf_bsize is integer range 15 downto 13;
constant stat_rbf_wrap : integer := 0;
constant stat_rbf_wrap : integer := 2;
constant stat_rbf_susp : integer := 1;
constant stat_rbf_run : integer := 0;
subtype addr_rbf_laddr is integer range 2+AWIDTH-1 downto 2;
subtype addr_rbf_waddr is integer range 1 downto 0;
@@ -127,15 +143,32 @@ architecture syn of rbd_rbmon is
subtype dat2_rbf_ndlylsb is integer range 15 downto 10;
subtype dat2_rbf_nbusy is integer range 9 downto 0;
constant func_sto : slv3 := "100"; -- func: stop
constant func_sta : slv3 := "101"; -- func: start
constant func_sus : slv3 := "110"; -- func: suspend
constant func_res : slv3 := "111"; -- func: resume
type regs_type is record -- state registers
rbsel : slbit; -- rbus select
wena : slbit; -- wena flag (wrap enable)
rcolw : slbit; -- rcolw flag (repeat collect writes)
rcolr : slbit; -- rcolr flag (repeat collect reads)
wstop : slbit; -- wstop flag (stop on wrap)
susp : slbit; -- suspended flag
go : slbit; -- go flag
hilim : slv16; -- upper address limit
lolim : slv16; -- lower address limit
wrap : slbit; -- laddr wrap flag
laddr : slv(AWIDTH-1 downto 0); -- line address
waddr : slv2; -- word address
addrlast: slv16; -- last rb addr
addrsame: slbit; -- curr rb addr equal last rb addr
addrwind: slbit; -- curr rb addr in [lolim,hilim] window
aval_1 : slbit; -- last cycle aval
arm1r : slbit; -- 1st level arm for read
arm2r : slbit; -- 2nd level arm for read
arm1w : slbit; -- 1st level arm for write
arm2w : slbit; -- 2nd level arm for write
rcol : slbit; -- repeat collaps
rbtake_1 : slbit; -- rb capture active in last cycle
rbaddr : slv16; -- rbus trace: addr
rbinit : slbit; -- rbus trace: init
@@ -156,12 +189,16 @@ architecture syn of rbd_rbmon is
constant regs_init : regs_type := (
'0', -- rbsel
'0','0', -- wena,go
'0','0','0', -- rcolw,rcolr,wstop
'0','1', -- susp,go
x"fffb", -- hilim (def: fffb)
x"0000", -- lolim (def: 0000)
'0', -- wrap
laddrzero, -- laddr
"00", -- waddr
x"ffff", -- addrlast (startup: ffff)
'0','0','0', -- addrsame,addrwind,aval_1
'0','0','0','0','0', -- arm1r,arm2r,arm1w,arm2w,rcol
'0', -- rbtake_1
(others=>'0'), -- rbaddr
'0','0','0','0','0', -- rbinit,rbwe,rback,rbbusy,rberr
@@ -183,7 +220,8 @@ architecture syn of rbd_rbmon is
signal BRAM1_DI : slv32 := (others=>'0');
signal BRAM0_DO : slv32 := (others=>'0');
signal BRAM1_DO : slv32 := (others=>'0');
signal BRAM_ADDR : slv(AWIDTH-1 downto 0) := (others=>'0');
begin
assert AWIDTH>=9 and AWIDTH<=14
@@ -198,7 +236,7 @@ begin
CLK => CLK,
EN => BRAM_EN,
WE => BRAM_WE,
ADDR => R_REGS.laddr,
ADDR => BRAM_ADDR,
DI => BRAM1_DI,
DO => BRAM1_DO
);
@@ -211,7 +249,7 @@ begin
CLK => CLK,
EN => BRAM_EN,
WE => BRAM_WE,
ADDR => R_REGS.laddr,
ADDR => BRAM_ADDR,
DI => BRAM0_DI,
DO => BRAM0_DO
);
@@ -243,6 +281,8 @@ begin
variable idat1 : slv16 := (others=>'0');
variable idat2 : slv16 := (others=>'0');
variable idat3 : slv16 := (others=>'0');
variable iaddrinc : slv(AWIDTH-1 downto 0) := (others=>'0');
variable iaddroff : slv(AWIDTH-1 downto 0) := (others=>'0');
begin
r := R_REGS;
@@ -267,6 +307,21 @@ begin
ibramen := '1';
end if;
-- rbus address monitor
if RB_MREQ.aval='1' and r.aval_1='0' then
n.addrlast := RB_MREQ.addr;
n.addrsame := '0';
if RB_MREQ.addr = r.addrlast then
n.addrsame := '1';
end if;
n.addrwind := '0';
if unsigned(RB_MREQ.addr)>=unsigned(r.lolim) and -- and in addr window
unsigned(RB_MREQ.addr)<=unsigned(r.hilim) then
n.addrwind := '1';
end if;
end if;
n.aval_1 := RB_MREQ.aval;
-- rbus transactions
if r.rbsel = '1' then
@@ -276,16 +331,27 @@ begin
when rbaddr_cntl => -- cntl ------------------
if RB_MREQ.we = '1' then
n.wena := RB_MREQ.din(cntl_rbf_wena);
if RB_MREQ.din(cntl_rbf_start) = '1' then
n.go := '1';
n.wrap := '0';
n.laddr := laddrzero;
n.waddr := "00";
end if;
if RB_MREQ.din(cntl_rbf_stop) = '1' then
n.go := '0';
end if;
case RB_MREQ.din(cntl_rbf_func) is
when func_sto => -- func: stop ------------
n.go := '0';
n.susp := '0';
when func_sta => -- func: start -----------
n.rcolw := RB_MREQ.din(cntl_rbf_rcolw);
n.rcolr := RB_MREQ.din(cntl_rbf_rcolr);
n.wstop := RB_MREQ.din(cntl_rbf_wstop);
n.go := '1';
n.susp := '0';
n.wrap := '0';
n.laddr := laddrzero;
n.waddr := "00";
when func_sus => -- func: susp ------------
n.go := '0';
n.susp := r.go;
when func_res => -- func: resu ------------
n.go := r.susp;
n.susp := '0';
when others => null; -- <> --------------------
end case;
end if;
when rbaddr_stat => null; -- stat ------------------
@@ -329,11 +395,14 @@ begin
if r.rbsel = '1' then
case RB_MREQ.addr(2 downto 0) is
when rbaddr_cntl => -- cntl ------------------
irb_dout(cntl_rbf_wena) := r.wena;
irb_dout(cntl_rbf_start) := r.go;
irb_dout(cntl_rbf_rcolw) := r.rcolw;
irb_dout(cntl_rbf_rcolr) := r.rcolr;
irb_dout(cntl_rbf_wstop) := r.wstop;
when rbaddr_stat => -- stat ------------------
irb_dout(stat_rbf_bsize) := slv(to_unsigned(AWIDTH-9,3));
irb_dout(stat_rbf_wrap) := r.wrap;
irb_dout(stat_rbf_susp) := r.susp; -- started and suspended
irb_dout(stat_rbf_run) := r.go or r.susp; -- started
when rbaddr_hilim => -- hilim -----------------
irb_dout := r.hilim;
when rbaddr_lolim => -- lolim -----------------
@@ -358,10 +427,8 @@ begin
-- and the access is not refering to rbd_rbmon itself
rbtake := '0';
if RB_MREQ.aval='1' and irbena='1' then -- aval and (re or we)
if unsigned(RB_MREQ.addr)>=unsigned(r.lolim) and -- and in addr window
unsigned(RB_MREQ.addr)<=unsigned(r.hilim) and
r.rbsel='0' then -- and not self
if RB_MREQ.aval='1' and irbena='1' then -- aval and (re or we)
if r.addrwind='1' and r.rbsel='0' then -- and in window and not self
rbtake := '1';
end if;
end if;
@@ -395,6 +462,16 @@ begin
n.rbnak := not RB_SRES_SUM.ack;
n.rbtout := RB_SRES_SUM.busy;
if RB_SRES_SUM.busy = '0' then -- if last cycle of a transaction
n.addrsame := '1'; -- in case of burst
n.arm1r := r.rcolr and RB_MREQ.re;
n.arm1w := r.rcolw and RB_MREQ.we;
n.arm2r := r.arm1r and r.addrsame and RB_MREQ.re;
n.arm2w := r.arm1w and r.addrsame and RB_MREQ.we;
n.rcol := ((r.arm2r and RB_MREQ.re) or
(r.arm2w and RB_MREQ.we)) and r.addrsame;
end if;
else -- if capture not active
if r.go='1' and r.rbtake_1='1' then -- active and transaction just ended
ibramen := '1';
@@ -415,12 +492,16 @@ begin
n.rbburst := '0'; -- clear burst flag
end if;
iaddrinc := (others=>'0');
iaddroff := (others=>'0');
iaddrinc(0) := not (r.rcol and r.go);
iaddroff(0) := (r.rcol and r.go);
if laddr_inc = '1' then
n.laddr := slv(unsigned(r.laddr) + 1);
n.laddr := slv(unsigned(r.laddr) + unsigned(iaddrinc));
if r.go='1' and r.laddr=laddrlast then
if r.wena = '1' then
n.wrap := '1';
else
n.wrap := '1';
if r.wstop = '1' then
n.go := '0';
end if;
end if;
@@ -445,11 +526,12 @@ begin
N_REGS <= n;
BRAM_EN <= ibramen;
BRAM_WE <= ibramwe;
BRAM_EN <= ibramen;
BRAM_WE <= ibramwe;
BRAM_ADDR <= slv(unsigned(R_REGS.laddr) - unsigned(iaddroff));
BRAM1_DI <= idat3 & idat2;
BRAM0_DI <= idat1 & idat0;
BRAM1_DI <= idat3 & idat2;
BRAM0_DI <= idat1 & idat0;
RB_SRES.dout <= irb_dout;
RB_SRES.ack <= irb_ack;

89
tools/tcl/ibd_ibmon/util.tcl
View File

@@ -1,4 +1,4 @@
# $Id: util.tcl 837 2017-01-02 19:23:34Z mueller $
# $Id: util.tcl 872 2017-04-09 20:48:05Z mueller $
#
# Copyright 2015-2017 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
#
@@ -13,6 +13,7 @@
#
# Revision History:
# Date Rev Version Comment
# 2017-04-09 872 2.0 revised interface, add suspend and repeat collect
# 2017-01-02 837 1.1.1 add procs ime,imf
# 2016-12-30 833 1.1 add proc filter
# 2015-12-28 721 1.0.2 add regmap_add defs; add symbolic register dump
@@ -30,8 +31,10 @@ namespace eval ibd_ibmon {
#
# setup register descriptions for ibd_ibmon
#
regdsc CNTL {conena 5} {remena 4} {locena 3} {wena 2} {stop 1} {start 0}
regdsc STAT {bsize 15 3} {wrap 0}
regdsc CNTL {rcolw 8} {rcolr 7} {wstop 6} \
{conena 5} {remena 4} {locena 3} \
{func 2 3 "s:NOOP:NOOP1:NOOP2:NOOP3:STO:STA:SUS:RES"}
regdsc STAT {bsize 15 3} {wrap 2} {susp 1} {run 0}
regdsc ADDR {laddr 15 14} {waddr 1 2}
#
regdsc DAT3 {burst 15} {tout 14} {nak 13} {ack 12} \
@@ -64,64 +67,77 @@ namespace eval ibd_ibmon {
#
proc init {{cpu "cpu0"}} {
$cpu cp \
-wibr im.cntl [regbld ibd_ibmon::CNTL stop] \
-wibr im.cntl [regbld ibd_ibmon::CNTL {func "STO"}] \
-wibr im.hilim 0177776 \
-wibr im.lolim 0160000 \
-wibr im.addr 0x0000
}
#
# start: start the ibmon ---------------------------------------------------
#
proc start {{cpu "cpu0"} args} {
args2opts opts { conena 1 remena 1 locena 1 wena 1 } {*}$args
$cpu cp -wibr im.cntl [regbld ibd_ibmon::CNTL start \
[list wena $opts(wena)] \
[list locena $opts(locena)] \
[list remena $opts(remena)] \
[list conena $opts(conena)] \
]
}
#
# start: setup filter window -----------------------------------------------
#
proc filter {{cpu "cpu0"} {lolim 0} {hilim 0177776}} {
$cpu cp -wibr im.lolim $lolim \
-wibr im.hilim $hilim
}
#
# start: start the ibmon ---------------------------------------------------
#
proc start {{cpu "cpu0"} args} {
args2opts opts {rcolw 0 rcolr 0 wstop 0 conena 1 remena 1 locena 1} {*}$args
$cpu cp -wibr im.cntl [regbld ibd_ibmon::CNTL {func "STA"} \
[list rcolw $opts(rcolw)] \
[list rcolr $opts(rcolr)] \
[list wstop $opts(wstop)] \
[list locena $opts(locena)] \
[list remena $opts(remena)] \
[list conena $opts(conena)] \
]
}
#
# stop: stop the ibmon -----------------------------------------------------
#
proc stop {{cpu "cpu0"}} {
$cpu cp -wibr im.cntl [regbld ibd_ibmon::CNTL stop]
$cpu cp -wibr im.cntl [regbld ibd_ibmon::CNTL {func "STO"}]
}
#
# read: read nent last entries (by default all) ----------------------------
#
proc read {{cpu "cpu0"} {nent -1}} {
$cpu cp -ribr im.addr raddr \
# suspend and get address and status
$cpu cp -wibr im.cntl [regbld ibd_ibmon::CNTL {func "SUS"}] \
-ribr im.cntl rcntl \
-ribr im.addr raddr \
-ribr im.stat rstat
# determine max number items
set bsize [regget ibd_ibmon::STAT(bsize) $rstat]
set amax [expr {( 512 << $bsize ) - 1}]
if {$nent == -1} { set nent $amax }
set nmax [expr { $amax + 1 } ]
if {$nent == -1} { set nent $nmax }
if {$nent > $nmax} { set nent $nmax }
# determine number of available items (check wrap flag)
set laddr [regget ibd_ibmon::ADDR(laddr) $raddr]
set nval $laddr
if {[regget ibd_ibmon::STAT(wrap) $rstat]} { set nval $amax }
if {[regget ibd_ibmon::STAT(wrap) $rstat]} { set nval $nmax }
if {$nent > $nval} {set nent $nval}
if {$nent == 0} { return {} }
if {$nent == 0} { return {} }
set caddr [expr {( $laddr - $nent ) & $amax}]
# if wstop set use first nent items, otherwise last nent items
set caddr 0
if {![regget ibd_ibmon::CNTL(wstop) $rcntl]} {
set caddr [expr {( $laddr - $nent ) & $amax}]
}
$cpu cp -wibr im.addr [regbld ibd_ibmon::ADDR [list laddr $caddr]]
set rval {}
set nblkmax [expr {( [rlc get bsizemax] >> 2 ) << 2}]; # ensure multiple of 4
set nrest $nent
while {$nrest > 0} {
set nblk [expr {$nrest << 2}]
if {$nblk > 256} {set nblk 256}
if {$nblk > $nblkmax} {set nblk $nblkmax}
set iaddr [$cpu imap im.data]
$cpu cp -rbibr $iaddr $nblk rawdat
@@ -164,8 +180,10 @@ namespace eval ibd_ibmon {
set nrest [expr {$nrest - ( $nblk >> 2 ) }]
}
$cpu cp -wibr im.addr $raddr
# resume and restore address
$cpu cp -wibr im.addr $raddr \
-wibr im.cntl [regbld ibd_ibmon::CNTL {func "RES"}]
return $rval
}
#
@@ -313,17 +331,24 @@ namespace eval ibd_ibmon {
# ime: ibmon enable --------------------------------------------------------
#
proc ime {{cpu "cpu0"} {mode "lrc"}} {
if {![regexp {^[crl]+n?$} $mode]} {
error "ime-E: bad mode '$mode', use \[lrc\] and n"
if {![regexp {^[lrcnRW]*$} $mode]} {
error "ime-E: bad mode '$mode', use \[lrc\]* and \[nRW\]*"
}
set locena [string match *l* $mode]
set remena [string match *r* $mode]
set conena [string match *c* $mode]
set wena 1
if {[string match *n* $mode]} {set wena 0}
if {$locena == 0 && $remena == 0 && $conena == 0} {
set locena 1
set remena 1
set conena 1
}
set wstop [string match *n* $mode]
set rcolr [string match *R* $mode]
set rcolw [string match *W* $mode]
ibd_ibmon::start $cpu \
locena $locena remena $remena conena $conena wena $wena
locena $locena remena $remena conena $conena \
wstop $wstop rcolr $rcolr rcolw $rcolw
return ""
}

228
tools/tcl/rbmoni/test_rbtest.tcl
View File

@@ -1,6 +1,6 @@
# $Id: test_rbtest.tcl 661 2015-04-03 18:28:41Z mueller $
# $Id: test_rbtest.tcl 872 2017-04-09 20:48:05Z mueller $
#
# Copyright 2011-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
# Copyright 2011-2017 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
#
# This program is free software; you may redistribute and/or modify it under
# the terms of the GNU General Public License as published by the Free
@@ -13,6 +13,7 @@
#
# Revision History:
# Date Rev Version Comment
# 2017-04-09 872 3.0 adopt to revised interface
# 2015-04-03 661 2.1 drop estatdef; fix test 5 (wrong regs accessed)
# 2014-12-22 619 2.0 adopt to new rbd_rbmon and rlink v4
# 2011-03-27 374 1.0 Initial version
@@ -57,12 +58,12 @@ namespace eval rbmoni {
# write/read te.stat and te.data with rbmoni on; check that 4 lines aquired
rlc exec \
-wreg rm.cntl [regbld rbmoni::CNTL start] \
-wreg rm.cntl [regbld rbmoni::CNTL {func "STA"}] \
-wreg te.stat $vtestat \
-wreg te.data $vtedata \
-rreg te.stat -edata $vtestat \
-rreg te.data -edata $vtedata \
-wreg rm.cntl [regbld rbmoni::CNTL stop] \
-wreg rm.cntl [regbld rbmoni::CNTL {func "STO"}] \
-rreg rm.addr -edata [regbld rbmoni::ADDR {laddr 4}]
if {$print} {puts [print]}
@@ -331,6 +332,225 @@ namespace eval rbmoni {
rbmoni::init
#
#-------------------------------------------------------------------------
rlc log " test 6: test repeat collapse read with wreg,rreg "
#-----------------------------------------------------------------
rlc log " test 6a: dry run, no collapse active"
set vteinit [regbld rbtest::INIT cntl]
# build expect list: list of {eflag eaddr edata enbusy} sublists
raw_edata edat emsk \
[list [regbld rbmoni::FLAGS nak init] $atecntl $vteinit 0] \
[list [regbld rbmoni::FLAGS ack we] $atefifo 0x0001 0] \
[list [regbld rbmoni::FLAGS ack we] $atefifo 0x0002 0] \
[list [regbld rbmoni::FLAGS ack we] $atefifo 0x0003 0] \
[list [regbld rbmoni::FLAGS ack we] $atefifo 0x0004 0] \
[list [regbld rbmoni::FLAGS ack ] $atefifo 0x0001 0] \
[list [regbld rbmoni::FLAGS ack ] $atefifo 0x0002 0] \
[list [regbld rbmoni::FLAGS ack ] $atefifo 0x0003 0] \
[list [regbld rbmoni::FLAGS ack ] $atefifo 0x0004 0] \
[list [regbld rbmoni::FLAGS nak init] $atecntl $vteinit 0]
#
rbmoni::start
rlc exec \
-init te.cntl $vteinit \
-wreg te.fifo 0x0001 \
-wreg te.fifo 0x0002 \
-wreg te.fifo 0x0003 \
-wreg te.fifo 0x0004 \
-rreg te.fifo -edata 0x0001 \
-rreg te.fifo -edata 0x0002 \
-rreg te.fifo -edata 0x0003 \
-rreg te.fifo -edata 0x0004 \
-init te.cntl $vteinit
rbmoni::stop
if {$print} {puts [print]}
raw_check $edat $emsk
#-----------------------------------------------------------------
rlc log " test 6b: read collapse active"
# build expect list: list of {eflag eaddr edata enbusy} sublists
raw_edata edat emsk \
[list [regbld rbmoni::FLAGS nak init] $atecntl $vteinit 0] \
[list [regbld rbmoni::FLAGS ack we] $atefifo 0x0001 0] \
[list [regbld rbmoni::FLAGS ack we] $atefifo 0x0002 0] \
[list [regbld rbmoni::FLAGS ack we] $atefifo 0x0003 0] \
[list [regbld rbmoni::FLAGS ack we] $atefifo 0x0004 0] \
[list [regbld rbmoni::FLAGS ack ] $atefifo 0x0001 0] \
[list [regbld rbmoni::FLAGS ack ] $atefifo 0x0004 0] \
[list [regbld rbmoni::FLAGS nak init] $atecntl $vteinit 0]
#
rbmoni::start rcolr 1
rlc exec \
-init te.cntl $vteinit \
-wreg te.fifo 0x0001 \
-wreg te.fifo 0x0002 \
-wreg te.fifo 0x0003 \
-wreg te.fifo 0x0004 \
-rreg te.fifo -edata 0x0001 \
-rreg te.fifo -edata 0x0002 \
-rreg te.fifo -edata 0x0003 \
-rreg te.fifo -edata 0x0004 \
-init te.cntl $vteinit
rbmoni::stop
if {$print} {puts [print]}
raw_check $edat $emsk
#-----------------------------------------------------------------
rlc log " test 6c: write collapse active"
# build expect list: list of {eflag eaddr edata enbusy} sublists
raw_edata edat emsk \
[list [regbld rbmoni::FLAGS nak init] $atecntl $vteinit 0] \
[list [regbld rbmoni::FLAGS ack we] $atefifo 0x0001 0] \
[list [regbld rbmoni::FLAGS ack we] $atefifo 0x0004 0] \
[list [regbld rbmoni::FLAGS ack ] $atefifo 0x0001 0] \
[list [regbld rbmoni::FLAGS ack ] $atefifo 0x0002 0] \
[list [regbld rbmoni::FLAGS ack ] $atefifo 0x0003 0] \
[list [regbld rbmoni::FLAGS ack ] $atefifo 0x0004 0] \
[list [regbld rbmoni::FLAGS nak init] $atecntl $vteinit 0]
#
rbmoni::start rcolw 1
rlc exec \
-init te.cntl $vteinit \
-wreg te.fifo 0x0001 \
-wreg te.fifo 0x0002 \
-wreg te.fifo 0x0003 \
-wreg te.fifo 0x0004 \
-rreg te.fifo -edata 0x0001 \
-rreg te.fifo -edata 0x0002 \
-rreg te.fifo -edata 0x0003 \
-rreg te.fifo -edata 0x0004 \
-init te.cntl $vteinit
rbmoni::stop
if {$print} {puts [print]}
raw_check $edat $emsk
#-----------------------------------------------------------------
rlc log " test 6d: read and write collapse active"
# build expect list: list of {eflag eaddr edata enbusy} sublists
raw_edata edat emsk \
[list [regbld rbmoni::FLAGS nak init] $atecntl $vteinit 0] \
[list [regbld rbmoni::FLAGS ack we] $atefifo 0x0001 0] \
[list [regbld rbmoni::FLAGS ack we] $atefifo 0x0004 0] \
[list [regbld rbmoni::FLAGS ack ] $atefifo 0x0001 0] \
[list [regbld rbmoni::FLAGS ack ] $atefifo 0x0004 0] \
[list [regbld rbmoni::FLAGS nak init] $atecntl $vteinit 0]
#
rbmoni::start rcolw 1 rcolr 1
rlc exec \
-init te.cntl $vteinit \
-wreg te.fifo 0x0001 \
-wreg te.fifo 0x0002 \
-wreg te.fifo 0x0003 \
-wreg te.fifo 0x0004 \
-rreg te.fifo -edata 0x0001 \
-rreg te.fifo -edata 0x0002 \
-rreg te.fifo -edata 0x0003 \
-rreg te.fifo -edata 0x0004 \
-init te.cntl $vteinit
rbmoni::stop
if {$print} {puts [print]}
raw_check $edat $emsk
#
#-------------------------------------------------------------------------
rlc log " test 7: test repeat collapse read with wblk,rblk "
#-----------------------------------------------------------------
rlc log " test 7a: dry run, no collapse active"
set vteinit [regbld rbtest::INIT cntl]
set vtefifo {0x1101 0x2202 0x3303 0x4404}
# build expect list: list of {eflag eaddr edata enbusy} sublists
raw_edata edat emsk \
[list [regbld rbmoni::FLAGS nak init] $atecntl $vteinit 0] \
[list [regbld rbmoni::FLAGS ack we] $atefifo 0x1101 0] \
[list [regbld rbmoni::FLAGS burst ack we] $atefifo 0x2202 0] \
[list [regbld rbmoni::FLAGS burst ack we] $atefifo 0x3303 0] \
[list [regbld rbmoni::FLAGS burst ack we] $atefifo 0x4404 0] \
[list [regbld rbmoni::FLAGS ack ] $atefifo 0x1101 0] \
[list [regbld rbmoni::FLAGS burst ack ] $atefifo 0x2202 0] \
[list [regbld rbmoni::FLAGS burst ack ] $atefifo 0x3303 0] \
[list [regbld rbmoni::FLAGS burst ack ] $atefifo 0x4404 0] \
[list [regbld rbmoni::FLAGS nak init] $atecntl $vteinit 0]
#
rbmoni::start
rlc exec \
-init te.cntl $vteinit \
-wblk te.fifo $vtefifo \
-rblk te.fifo [llength $vtefifo] -edata $vtefifo \
-init te.cntl $vteinit
rbmoni::stop
if {$print} {puts [print]}
raw_check $edat $emsk
#-----------------------------------------------------------------
rlc log " test 7b: read collapse active"
#
# build expect list: list of {eflag eaddr edata enbusy} sublists
raw_edata edat emsk \
[list [regbld rbmoni::FLAGS nak init] $atecntl $vteinit 0] \
[list [regbld rbmoni::FLAGS ack we] $atefifo 0x1101 0] \
[list [regbld rbmoni::FLAGS burst ack we] $atefifo 0x2202 0] \
[list [regbld rbmoni::FLAGS burst ack we] $atefifo 0x3303 0] \
[list [regbld rbmoni::FLAGS burst ack we] $atefifo 0x4404 0] \
[list [regbld rbmoni::FLAGS ack ] $atefifo 0x1101 0] \
[list [regbld rbmoni::FLAGS burst ack ] $atefifo 0x4404 0] \
[list [regbld rbmoni::FLAGS nak init] $atecntl $vteinit 0]
#
rbmoni::start rcolr 1
rlc exec \
-init te.cntl $vteinit \
-wblk te.fifo $vtefifo \
-rblk te.fifo [llength $vtefifo] -edata $vtefifo \
-init te.cntl $vteinit
rbmoni::stop
if {$print} {puts [print]}
raw_check $edat $emsk
#-----------------------------------------------------------------
rlc log " test 7c: write collapse active"
#
# build expect list: list of {eflag eaddr edata enbusy} sublists
raw_edata edat emsk \
[list [regbld rbmoni::FLAGS nak init] $atecntl $vteinit 0] \
[list [regbld rbmoni::FLAGS ack we] $atefifo 0x1101 0] \
[list [regbld rbmoni::FLAGS burst ack we] $atefifo 0x4404 0] \
[list [regbld rbmoni::FLAGS ack ] $atefifo 0x1101 0] \
[list [regbld rbmoni::FLAGS burst ack ] $atefifo 0x2202 0] \
[list [regbld rbmoni::FLAGS burst ack ] $atefifo 0x3303 0] \
[list [regbld rbmoni::FLAGS burst ack ] $atefifo 0x4404 0] \
[list [regbld rbmoni::FLAGS nak init] $atecntl $vteinit 0]
#
rbmoni::start rcolw 1
rlc exec \
-init te.cntl $vteinit \
-wblk te.fifo $vtefifo \
-rblk te.fifo [llength $vtefifo] -edata $vtefifo \
-init te.cntl $vteinit
rbmoni::stop
if {$print} {puts [print]}
raw_check $edat $emsk
#-----------------------------------------------------------------
rlc log " test 7d: read and write collapse active"
#
# build expect list: list of {eflag eaddr edata enbusy} sublists
raw_edata edat emsk \
[list [regbld rbmoni::FLAGS nak init] $atecntl $vteinit 0] \
[list [regbld rbmoni::FLAGS ack we] $atefifo 0x1101 0] \
[list [regbld rbmoni::FLAGS burst ack we] $atefifo 0x4404 0] \
[list [regbld rbmoni::FLAGS ack ] $atefifo 0x1101 0] \
[list [regbld rbmoni::FLAGS burst ack ] $atefifo 0x4404 0] \
[list [regbld rbmoni::FLAGS nak init] $atecntl $vteinit 0]
#
rbmoni::start rcolw 1 rcolr 1
rlc exec \
-init te.cntl $vteinit \
-wblk te.fifo $vtefifo \
-rblk te.fifo [llength $vtefifo] -edata $vtefifo \
-init te.cntl $vteinit
rbmoni::stop
if {$print} {puts [print]}
raw_check $edat $emsk
#-------------------------------------------------------------------------
rlc log "rbmoni::test_rbtest - cleanup:"
rbtest::init

73
tools/tcl/rbmoni/test_regs.tcl
View File

@@ -1,6 +1,6 @@
# $Id: test_regs.tcl 661 2015-04-03 18:28:41Z mueller $
# $Id: test_regs.tcl 872 2017-04-09 20:48:05Z mueller $
#
# Copyright 2011-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
# Copyright 2011-2017 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
#
# This program is free software; you may redistribute and/or modify it under
# the terms of the GNU General Public License as published by the Free
@@ -13,6 +13,7 @@
#
# Revision History:
# Date Rev Version Comment
# 2017-04-09 872 3.0 adopt to revised interface
# 2015-04-03 661 2.1 drop estatdef (stat err check default now)
# 2014-12-27 622 2.0 rbd_rbmon reorganized, supports now 16 bit addresses
# 2011-03-27 374 1.0 Initial version
@@ -38,18 +39,56 @@ namespace eval rbmoni {
#
#-------------------------------------------------------------------------
rlc log " test 1: write/read cntl"
# test that starting caputes option flags, and that stoping keeps them
rlc exec \
-wreg rm.cntl [regbld rbmoni::CNTL start] \
-rreg rm.cntl -edata [regbld rbmoni::CNTL start] \
-wreg rm.cntl [regbld rbmoni::CNTL stop] \
-rreg rm.cntl -edata 0 \
-wreg rm.cntl [regbld rbmoni::CNTL start wena] \
-rreg rm.cntl -edata [regbld rbmoni::CNTL start wena] \
-wreg rm.cntl [regbld rbmoni::CNTL stop] \
-rreg rm.cntl -edata 0
-wreg rm.cntl [regbld rbmoni::CNTL {func "STA"}] \
-rreg rm.cntl -edata [regbld rbmoni::CNTL] \
-wreg rm.cntl [regbld rbmoni::CNTL wstop {func "STA"}] \
-rreg rm.cntl -edata [regbld rbmoni::CNTL wstop] \
-wreg rm.cntl [regbld rbmoni::CNTL rcolr {func "STA"}] \
-rreg rm.cntl -edata [regbld rbmoni::CNTL rcolr] \
-wreg rm.cntl [regbld rbmoni::CNTL rcolw {func "STA"}] \
-rreg rm.cntl -edata [regbld rbmoni::CNTL rcolw] \
-wreg rm.cntl [regbld rbmoni::CNTL rcolw rcolr {func "STA"}] \
-rreg rm.cntl -edata [regbld rbmoni::CNTL rcolw rcolr] \
-wreg rm.cntl [regbld rbmoni::CNTL {func "STO"}] \
-rreg rm.cntl -edata [regbld rbmoni::CNTL rcolw rcolr]
#
#-------------------------------------------------------------------------
rlc log " test 2: read stat"
rlc log " test 2: write cntl, read stat"
# test that susp/run follow functions set to cntl
rlc exec \
-wreg rm.cntl [regbld rbmoni::CNTL {func "STA"}] \
-rreg rm.stat -edata [regbld rbmoni::STAT run] \
-wreg rm.cntl [regbld rbmoni::CNTL {func "SUS"}] \
-rreg rm.stat -edata [regbld rbmoni::STAT susp run] \
-wreg rm.cntl [regbld rbmoni::CNTL {func "RES"}] \
-rreg rm.stat -edata [regbld rbmoni::STAT run] \
-wreg rm.cntl [regbld rbmoni::CNTL {func "STO"}] \
-rreg rm.stat -edata [regbld rbmoni::STAT]
# test that suspend/resume of a stopped system is a noop
rlc exec \
-wreg rm.cntl [regbld rbmoni::CNTL {func "SUS"}] \
-rreg rm.stat -edata [regbld rbmoni::STAT] \
-wreg rm.cntl [regbld rbmoni::CNTL {func "RES"}] \
-rreg rm.stat -edata [regbld rbmoni::STAT]
# test that start of a suspended system clears suspend
rlc exec \
-wreg rm.cntl [regbld rbmoni::CNTL {func "STA"}] \
-rreg rm.stat -edata [regbld rbmoni::STAT run] \
-wreg rm.cntl [regbld rbmoni::CNTL {func "SUS"}] \
-rreg rm.stat -edata [regbld rbmoni::STAT susp run] \
-wreg rm.cntl [regbld rbmoni::CNTL {func "STA"}] \
-rreg rm.stat -edata [regbld rbmoni::STAT run]
# test that stop of a suspended system clears suspend
rlc exec \
-wreg rm.cntl [regbld rbmoni::CNTL {func "STA"}] \
-rreg rm.stat -edata [regbld rbmoni::STAT run] \
-wreg rm.cntl [regbld rbmoni::CNTL {func "SUS"}] \
-rreg rm.stat -edata [regbld rbmoni::STAT susp run] \
-wreg rm.cntl [regbld rbmoni::CNTL {func "STO"}] \
-rreg rm.stat -edata [regbld rbmoni::STAT]
# get amax for later usage
rlc exec \
-rreg rm.stat rstat
set bsize [regget rbmoni::STAT(bsize) $rstat]
@@ -74,17 +113,13 @@ namespace eval rbmoni {
}
#
#-------------------------------------------------------------------------
rlc log " test 5: verify that cntl.go 0->1 clear addr"
rlc log " test 5: verify that starting clears addr"
rlc exec \
-wreg rm.cntl [regbld rbmoni::CNTL stop] \
-rreg rm.cntl -edata 0x0 \
-wreg rm.cntl [regbld rbmoni::CNTL {func "STO"}] \
-wreg rm.addr [regbld rbmoni::ADDR [list laddr $amax]] \
-rreg rm.addr -edata [regbld rbmoni::ADDR [list laddr $amax]] \
-wreg rm.cntl [regbld rbmoni::CNTL start] \
-rreg rm.cntl -edata [regbld rbmoni::CNTL start] \
-rreg rm.addr -edata 0x00 \
-wreg rm.cntl [regbld rbmoni::CNTL stop] \
-rreg rm.cntl -edata 0x0
-wreg rm.cntl [regbld rbmoni::CNTL {func "STA"}] \
-rreg rm.addr -edata 0x00
#
#-------------------------------------------------------------------------
rlc log "rbmoni::test_regs - cleanup"

58
tools/tcl/rbmoni/util.tcl
View File

@@ -1,6 +1,6 @@
# $Id: util.tcl 661 2015-04-03 18:28:41Z mueller $
# $Id: util.tcl 872 2017-04-09 20:48:05Z mueller $
#
# Copyright 2011-2015 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
# Copyright 2011-2017 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
#
# This program is free software; you may redistribute and/or modify it under
# the terms of the GNU General Public License as published by the Free
@@ -13,6 +13,7 @@
#
# Revision History:
# Date Rev Version Comment
# 2017-04-09 872 4.0 revised interface, add suspend and repeat collect
# 2015-04-03 661 3.1 drop estatdef; invert mask in raw_edata
# 2014-12-23 619 3.0 rbd_rbmon reorganized, supports now 16 bit addresses
# 2014-11-09 603 2.0 use rlink v4 address layout
@@ -29,8 +30,9 @@ namespace eval rbmoni {
#
# setup register descriptions for rbd_rbmon
#
regdsc CNTL {wena 2} {stop 1} {start 0}
regdsc STAT {bsize 15 3} {wrap 0}
regdsc CNTL {rcolw 5} {rcolr 4} {wstop 3} \
{func 2 3 "s:NOOP:NOOP1:NOOP2:NOOP3:STO:STA:SUS:RES"}
regdsc STAT {bsize 15 3} {wrap 2} {susp 1} {run 0}
regdsc ADDR {laddr 15 14} {waddr 1 2}
#
regdsc DAT3 {flags 15 8 "-"} {burst 15} {tout 14} {nak 13} {ack 12} \
@@ -57,7 +59,7 @@ namespace eval rbmoni {
#
proc init {} {
rlc exec \
-wreg rm.cntl [regbld rbmoni::CNTL stop] \
-wreg rm.cntl [regbld rbmoni::CNTL {func "STO"}] \
-wreg rm.hilim 0xfffb \
-wreg rm.lolim 0x0000 \
-wreg rm.addr 0x0000
@@ -65,42 +67,58 @@ namespace eval rbmoni {
#
# start: start the rbmon
#
proc start {{wena 0}} {
rlc exec -wreg rm.cntl [regbld rbmoni::CNTL start [list wena $wena]]
proc start {args} {
args2opts opts {rcolw 0 rcolr 0 wstop 0} {*}$args
rlc exec -wreg rm.cntl [regbld rbmoni::CNTL {func "STA"} \
[list rcolw $opts(rcolw)] \
[list rcolr $opts(rcolr)] \
[list wstop $opts(wstop)] \
]
}
#
# stop: stop the rbmon
#
proc stop {} {
rlc exec -wreg rm.cntl [regbld rbmoni::CNTL stop]
rlc exec -wreg rm.cntl [regbld rbmoni::CNTL {func "STO"}]
}
#
# read: read nent last entries (by default all)
#
proc read {{nent -1}} {
rlc exec -rreg rm.addr raddr \
rlc exec -wreg rm.cntl [regbld rbmoni::CNTL {func "SUS"}] \
-rreg rm.cntl rcntl \
-rreg rm.addr raddr \
-rreg rm.stat rstat
# determine max number items
set bsize [regget rbmoni::STAT(bsize) $rstat]
set amax [expr {( 512 << $bsize ) - 1}]
if {$nent == -1} { set nent $amax }
set nmax [expr { $amax + 1 } ]
if {$nent == -1} { set nent $nmax }
if {$nent > $nmax} { set nent $nmax }
# determine number of available items (check wrap flag)
set laddr [regget rbmoni::ADDR(laddr) $raddr]
set nval $laddr
if {[regget rbmoni::STAT(wrap) $rstat]} { set nval $amax }
if {[regget rbmoni::STAT(wrap) $rstat]} { set nval $nmax }
if {$nent > $nval} {set nent $nval}
if {$nent == 0} { return {} }
if {$nent == 0} { return {} }
set caddr [expr {( $laddr - $nent ) & $amax}]
# if wstop set use first nent items, otherwise last nent items
set caddr 0
if {![regget rbmoni::CNTL(wstop) $rcntl]} {
set caddr [expr {( $laddr - $nent ) & $amax}]
}
rlc exec -wreg rm.addr [regbld rbmoni::ADDR [list laddr $caddr]]
set rval {}
set nblkmax [expr {( [rlc get bsizemax] >> 2 ) << 2}]; # ensure multiple of 4
set nrest $nent
while {$nrest > 0} {
set nblk [expr {$nrest << 2}]
if {$nblk > 256} {set nblk 256}
if {$nblk > $nblkmax} {set nblk $nblkmax}
rlc exec -rblk rm.data $nblk rawdat
foreach {d0 d1 d2 d3} $rawdat {
@@ -116,7 +134,9 @@ namespace eval rbmoni {
set nrest [expr {$nrest - ( $nblk >> 2 ) }]
}
rlc exec -wreg rm.addr $raddr
# resume and restore address
rlc exec -wreg rm.addr $raddr \
-wreg rm.cntl [regbld rbmoni::CNTL {func "RES"}]
set mbnext [regbld rbmoni::FLAGS bnext]
set mburst [regbld rbmoni::FLAGS burst]
@@ -149,7 +169,7 @@ namespace eval rbmoni {
set eind [expr {1 - [llength $mondat] }]
append rval \
" ind addr data delay nbsy flags bu to na ac bs er mode"
" ind addr data delay nbsy flags bu to na ac bs er mode"
set mbnext [regbld rbmoni::FLAGS bnext]
set mburst [regbld rbmoni::FLAGS burst]
@@ -199,7 +219,7 @@ namespace eval rbmoni {
if {$ftout} {append comment " TOUT=1!"}
if {[rlc amap -testaddr $eaddr]} {set ename [rlc amap -name $eaddr]}
append rval [format \
"\n%5d %-10s %4.4x %5s %4d %s %s %s %s %s %s %s %s %s" \
"\n%5d %-11s %4.4x %5s %4d %s %s %s %s %s %s %s %s %s" \
$eind $ename $edata $pedly $enbusy [pbvi b8 $eflag] \
$pburst $ptout $pnak $pack $pbusy $perr $pmode $comment]
incr eind

6
tools/tcl/rw11/shell.tcl
View File

@@ -1,4 +1,4 @@
# $Id: shell.tcl 837 2017-01-02 19:23:34Z mueller $
# $Id: shell.tcl 872 2017-04-09 20:48:05Z mueller $
#
# Copyright 2015-2017 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
#
@@ -13,6 +13,7 @@
#
# Revision History:
# Date Rev Version Comment
# 2017-04-09 872 2.2.1 adopt .ime to new interface
# 2017-01-02 837 2.2 code re-shuffle; add cpu status in prompt
# 2016-12-31 834 2.1 add '@' command
# 2016-12-30 833 2.0 major overhaul
@@ -567,7 +568,7 @@ namespace eval rw11 {
}
if {[$shell_cpu rmap -testname "im.cntl"]} {
append rval "\nibus monitor:"
append rval "\n .ime ; ibmon enable; mode: \[crl\]+n?"
append rval "\n .ime ; ibmon enable; mode: \[lrcnRW\]*"
append rval "\n .imd ; ibmon disable"
append rval "\n .imf ?lo? ?hi? ; ibmon filter"
append rval "\n .iml ?nent? ; ibmon list"
@@ -607,6 +608,7 @@ namespace eval rw11 {
append rval "\n r - for iopage access: rem (as seen by rlink)"
append rval "\n p - for memory access: physical (16bit)"
append rval "\n e - for memory access: extended (22 bit)"
append rval "\n u - for memory access via ubmap (22 bit)"
append rval "\n MS - for memory access via mmu mode=M and space=S"
append rval "\n - M (mode) as c,p,k,s,u for cm,pm,kern,sup,user"
append rval "\n - S (space) as i,d for instruction,data"