github.com/wfjm.w11
1
0
Fork 0
mirror of https://github.com/wfjm/w11.git synced 2026-04-16 01:30:43 +00:00
Code Issues Releases Wiki Activity

update vivado design vmfset files

Browse Source
This commit is contained in:
wfjm
2018-10-14 15:06:24 +02:00
parent 706abfa8cc
commit 90db21ac5e
5 changed files with 61 additions and 27 deletions
Download Patch File Download Diff File Expand all files Collapse all files

35
rtl/sys_gen/w11a/arty_bram/sys_w11a_br_arty.vmfset
View File

@@ -1,4 +1,4 @@
# $Id: sys_w11a_br_arty.vmfset 1039 2018-08-12 10:04:09Z mueller $
# $Id: sys_w11a_br_arty.vmfset 1056 2018-10-13 16:01:17Z mueller $
#
# ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
[syn]
@@ -18,9 +18,15 @@ I [Designutils 20-1567] # generic
# unconnected ports --------------------------------------------
I [Synth 8-3331] RB_MREQ # generic
I [Synth 8-3331] IB_MREQ # generic
I [Synth 8-3331] DM_STAT_DP # generic
# --> pdp11_hio70_arty uses only subset of CP_STAT info # OK 2016-06-05
I [Synth 8-3331] pdp11_hio70_arty.*CP_STAT[.*]
I [Synth 8-3331] DM_STAT_EXP # generic
I [Synth 8-3331] CP_STAT # generic
I [Synth 8-3331] SER_MONI # generic
# --> only 128 kB memory available
i [Synth 8-3331] pdp11_bram_memctl .* ADDR[1(6|7|8|9)] # OK 2018-10-13
# --> msec indeed not used
i [Synth 8-3331] ibdr_rl11 .* CE_MSEC # OK 2018-10-13
# sequential element removed (2017.1 nonsense) -----------------
I [Synth 8-6014] _reg # generic
@@ -61,22 +67,25 @@ i [Synth 8-3332] SEQ/SNUM0.R_VMWAIT_reg
{2017.1:2017.4}
I [Synth 8-3332] R_LREGS_reg[attn][\d*] # generic
# --> many HIO pins not used # OK 2017-06-06
# --> many HIO pins not used # OK 2018-10-13
I [Synth 8-3332] HIO/R_REGS_reg[(btn|swi)(eff)?][\d*]
i [Synth 8-3332] HIO/IOB_BTN/R_DI_reg[\d*]
i [Synth 8-3332] HIO/DEB.DEB_BTN/R_REGS_reg[(dref|dout|dchange|cecnt)][\d*]
# --> usec not used for serport clock domain # OK 2017-06-06
i [Synth 8-3332] CLKDIV_CLKS/R_REGS_reg[usec]
i [Synth 8-3332] IOB_BTN/R_DI_reg[\d*]
i [Synth 8-3332] DEB.DEB_BTN/R_REGS_reg[(dref|dout|dchange|cecnt)][\d*]
# --> usec not used for serport clock domain # OK 2018-10-13
i [Synth 8-3332] R_REGS_reg[usec]
# --> mawidth=4, nblock=11, so some cellen unused # OK 2016-06-05
i [Synth 8-3332] BRAM_CTL/R_REGS_reg[cellen][1\d]
### i [Synth 8-3332] BRAM_CTL/R_REGS_reg[cellen][1\d]
# --> indeed no types with [3] set # OK 2017-06-06
i [Synth 8-3332] R_REGS_reg[dtyp][3].* ibdr_rhrp
# --> not yet used # OK 2017-06-06
i [Synth 8-3332] R_REGS_reg[req_lock].* ibd_iist
i [Synth 8-3332] R_REGS_reg[req_boot].* ibd_iist
# --> monitor outputs moneop,monattn currently not used # OK 2016-06-05
i [Synth 8-3332] RLINK/CORE/RL/R_LREGS_reg[moneop]
i [Synth 8-3332] RLINK/CORE/RL/R_LREGS_reg[monattn]
# --> monitor outputs moneop,monattn currently not used # OK 2018-10-13
i [Synth 8-3332] CORE/RL/R_LREGS_reg[moneop]
i [Synth 8-3332] CORE/RL/R_LREGS_reg[monattn]
# --> PERFEXT(0:2) not used # OK 2018-10-13
i [Synth 8-3332] R_REGS_reg[psig][2(4|5|6)]
i [Synth 8-3332] PRE[2(4|5|6)].ENA.CNT/R_CNT_reg[\d*]
{2017.1:2017.3}
# --> inst_compl logic disabled in pdp11_mmu # OK 2017-06-06
@@ -92,6 +101,8 @@ i [Synth 8-3332] R_STATUS_reg[intvect][8].* pdp11_sequencer
i [Synth 8-3332] R_IDSTAT_reg[res_sel][2].* pdp11_sequencer
# --> dmcmon not configured, snum not used # OK 2017-06-06
i [Synth 8-3332] SNUM0.R_VMWAIT_reg.* pdp11_sequencer # OK 2017-06-06
# --> mawidth=4, nblock=11, so some cellen unused # OK 2018-10-13
i [Synth 8-3332] R_REGS_reg[cellen][1\d]
{2017.4}
# --> inst_compl logic disabled in pdp11_mmu # OK 2017-06-06

32
rtl/sys_gen/w11a/artys7_bram/sys_w11a_br_as7.vmfset
View File

@@ -1,4 +1,4 @@
# $Id: sys_w11a_br_as7.vmfset 1039 2018-08-12 10:04:09Z mueller $
# $Id: sys_w11a_br_as7.vmfset 1056 2018-10-13 16:01:17Z mueller $
#
# ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
[syn]
@@ -18,10 +18,15 @@ I [Designutils 20-1567] # generic
# unconnected ports --------------------------------------------
I [Synth 8-3331] RB_MREQ # generic
I [Synth 8-3331] IB_MREQ # generic
I [Synth 8-3331] DM_STAT_DP # generic
# --> pdp11_hio70_arty uses only subset of CP_STAT info # OK 2018-08-11
I [Synth 8-3331] pdp11_hio70_arty.*CP_STAT[.*]
I [Synth 8-3331] pdp11_hio70_artys7.*MEM_ACT_(R|W)
I [Synth 8-3331] DM_STAT_EXP # generic
I [Synth 8-3331] CP_STAT # generic
I [Synth 8-3331] SER_MONI # generic
# --> pdp11_hio70_arty doesn't use MEM_ACT # OK 2018-08-11
i [Synth 8-3331] pdp11_hio70_artys7.*MEM_ACT_(R|W)
# --> only 128 kB memory available
i [Synth 8-3331] pdp11_bram_memctl .* ADDR[1(6|7|8|9)] # OK 2018-10-13
# sequential element removed (2017.1 nonsense) -----------------
I [Synth 8-6014] _reg # generic
@@ -45,19 +50,22 @@ i [Synth 8-3332] R_IDSTAT_reg[res_sel][2].* pdp11_sequencer
i [Synth 8-3332] SNUM0.R_VMWAIT_reg.* pdp11_sequencer # OK 2018-08-11
{2017.2:2017.4}
# --> many HIO pins not used # OK 2018-08-11
# --> many HIO pins not used # OK 2018-10-13
I [Synth 8-3332] HIO/R_REGS_reg[(btn|swi)(eff)?][\d*]
i [Synth 8-3332] HIO/IOB_BTN/R_DI_reg[\d*]
i [Synth 8-3332] HIO/DEB.DEB_BTN/R_REGS_reg[(dref|dout|dchange|cecnt)][\d*]
# --> usec not used for serport clock domain # OK 2018-08-11
i [Synth 8-3332] CLKDIV_CLKS/R_REGS_reg[usec]
i [Synth 8-3332] IOB_BTN/R_DI_reg[\d*]
i [Synth 8-3332] DEB.DEB_BTN/R_REGS_reg[(dref|dout|dchange|cecnt)][\d*]
# --> usec not used for serport clock domain # OK 2018-10-13
i [Synth 8-3332] R_REGS_reg[usec]
# --> inst_compl logic disabled in pdp11_mmu # OK 2018-08-11
i [Synth 8-3332] MMU/R_SSR0_reg[inst_compl].* pdp11_vmbox
# --> IB_MREQ.cacc only used in ibd_ibmon, which is disabled # OK 2018-08-11
i [Synth 8-3332] R_REGS_reg[ibcacc].* pdp11_vmbox
# --> monitor outputs moneop,monattn currently not used # OK 2018-08-11
i [Synth 8-3332] RLINK/CORE/RL/R_LREGS_reg[moneop]
i [Synth 8-3332] RLINK/CORE/RL/R_LREGS_reg[monattn]
# --> monitor outputs moneop,monattn currently not used # OK 2018-10-13
i [Synth 8-3332] CORE/RL/R_LREGS_reg[moneop]
i [Synth 8-3332] CORE/RL/R_LREGS_reg[monattn]
# --> PERFEXT(0:2) not used # OK 2018-10-13
i [Synth 8-3332] R_REGS_reg[psig][2(4|5|6)]
i [Synth 8-3332] PRE[2(4|5|6)].ENA.CNT/R_CNT_reg[\d*]
{2018.1:}
# --> many HIO pins not used # OK 2018-08-11

7
rtl/sys_gen/w11a/basys3/sys_w11a_b3.vmfset
View File

@@ -1,4 +1,4 @@
# $Id: sys_w11a_b3.vmfset 1039 2018-08-12 10:04:09Z mueller $
# $Id: sys_w11a_b3.vmfset 1056 2018-10-13 16:01:17Z mueller $
#
# ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
[syn]
@@ -19,6 +19,8 @@ I [Designutils 20-1567] # generic
# unconnected ports --------------------------------------------
I [Synth 8-3331] RB_MREQ # generic
I [Synth 8-3331] DM_STAT_DP # generic
I [Synth 8-3331] DM_STAT_EXP # generic
I [Synth 8-3331] CP_STAT # generic
# sequential element removed (2017.1 nonsense) -----------------
I [Synth 8-6014] _reg # generic
@@ -77,6 +79,9 @@ i [Synth 8-3332] CORE/RL/R_LREGS_reg[moneop].* rlink_sp2c
i [Synth 8-3332] CORE/RL/R_LREGS_reg[monattn].* rlink_sp2c
# --> dmcmon not configured, snum not used # OK 2017-06-06
i [Synth 8-3332] SNUM0.R_VMWAIT_reg.* pdp11_sequencer
# --> PERFEXT(0:2) not used # OK 2018-10-13
i [Synth 8-3332] R_REGS_reg[psig][2(4|5|6)]
i [Synth 8-3332] PRE[2(4|5|6)].ENA.CNT/R_CNT_reg[\d*]
{2017.1:2017.4}
# --> inst_compl logic disabled in pdp11_mmu # OK 2017-06-06

7
rtl/sys_gen/w11a/cmoda7/sys_w11a_c7.vmfset
View File

@@ -1,4 +1,4 @@
# $Id: sys_w11a_c7.vmfset 1039 2018-08-12 10:04:09Z mueller $
# $Id: sys_w11a_c7.vmfset 1056 2018-10-13 16:01:17Z mueller $
#
# ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
[syn]
@@ -25,6 +25,8 @@ i [Synth 8-3295] EHIO:DSP_DP[(4|5|6|7)]
# unconnected ports --------------------------------------------
I [Synth 8-3331] RB_MREQ # generic
I [Synth 8-3331] DM_STAT_DP # generic
I [Synth 8-3331] DM_STAT_EXP # generic
I [Synth 8-3331] CP_STAT # generic
# sequential element removed (2017.1 nonsense) -----------------
I [Synth 8-6014] _reg # generic
@@ -78,6 +80,9 @@ i [Synth 8-3332] R_IDSTAT_reg[res_sel][2].* pdp11_sequencer
i [Synth 8-3332] R_REGS_reg[se_snum][(4|5|6)]
# --> upper 4 DSP_DP unused # OK 2017-06-24
i [Synth 8-3332] R_REGS_reg[dsp_dp][(4|5|6|7)]
# --> PERFEXT(0:2) not used # OK 2018-10-13
i [Synth 8-3332] R_REGS_reg[psig][2(4|5|6)]
i [Synth 8-3332] PRE[2(4|5|6)].ENA.CNT/R_CNT_reg[\d*]
{2017.1:2017.4}
# --> usec not used for serport clock domain # OK 2017-06-24

7
rtl/sys_gen/w11a/nexys4/sys_w11a_n4.vmfset
View File

@@ -1,4 +1,4 @@
# $Id: sys_w11a_n4.vmfset 1039 2018-08-12 10:04:09Z mueller $
# $Id: sys_w11a_n4.vmfset 1056 2018-10-13 16:01:17Z mueller $
#
# ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
[syn]
@@ -21,6 +21,8 @@ i [Synth 8-3917] O_RGBLED0[\d]
# unconnected ports --------------------------------------------
I [Synth 8-3331] RB_MREQ # generic
I [Synth 8-3331] DM_STAT_DP # generic
I [Synth 8-3331] DM_STAT_EXP # generic
I [Synth 8-3331] CP_STAT # generic
# sequential element removed (2017.1 nonsense) -----------------
I [Synth 8-6014] _reg # generic
@@ -74,6 +76,9 @@ i [Synth 8-3332] R_STATUS_reg[intvect][8].* pdp11_sequencer
i [Synth 8-3332] R_IDSTAT_reg[res_sel][2].* pdp11_sequencer
# --> scnt disabled, thus 3 SNUM bits '0' # OK 2017-06-06
i [Synth 8-3332] R_REGS_reg[se_snum][(4|5|6)]
# --> PERFEXT(0:2) not used # OK 2018-10-13
i [Synth 8-3332] R_REGS_reg[psig][2(4|5|6)]
i [Synth 8-3332] PRE[2(4|5|6)].ENA.CNT/R_CNT_reg[\d*]
{2017.1:2017.4}
# --> usec not used for serport clock domain # OK 2017-06-06