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- vmfset: now tested for viv 2017.2 and 2018.3
- imfset: now tested for ISE 14.7
This commit is contained in:
wfjm 2019-02-15 18:44:55 +01:00
parent 80fbad98c6
commit 913fe9b399
31 changed files with 506 additions and 564 deletions
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9
rtl/sys_gen/tst_mig/arty/sys_tst_mig_arty.vmfset
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@ -1,4 +1,9 @@
# $Id: sys_tst_mig_arty.vmfset 1101 2019-01-02 21:22:37Z mueller $
# $Id: sys_tst_mig_arty.vmfset 1108 2019-02-02 23:04:38Z mueller $
#
# Validated code/tool version combinations
# Date rev viv
# 2019-02-02 1108 2017.2
# 2019-02-02 1108 2018.3
#
# ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
[syn]
@ -32,6 +37,7 @@ i [Synth 8-3331] APP_SR_ACTIVE
I [Synth 8-6014] _reg # generic
# unused sequential element ------------------------------------
{2017.2:2018.2}
I [Synth 8-3332] R_LREGS_reg[attn][\d*] # generic
# --> usec unused # OK 2018-12-23
i [Synth 8-3332] R_REGS_reg[usec].* sys_tst_mig_arty
@ -40,6 +46,7 @@ i [Synth 8-3332] R_BREGS_reg[stat][(0|1|2|3)].* sys_tst_mig_arty
i [Synth 8-3332] R_LREGS_reg[(moneop|monattn)].* sys_tst_mig_arty
# --> no rbinit used # OK 2018-12-27
i [Synth 8-3332] R_BREGS_reg[rbinit].* sys_tst_mig_arty
{:}
# ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
[imp]

9
rtl/sys_gen/tst_mig/nexys4d/sys_tst_mig_n4d.vmfset
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@ -1,4 +1,9 @@
# $Id: sys_tst_mig_n4d.vmfset 1101 2019-01-02 21:22:37Z mueller $
# $Id: sys_tst_mig_n4d.vmfset 1108 2019-02-02 23:04:38Z mueller $
#
# Validated code/tool version combinations
# Date rev viv
# 2019-02-02 1108 2017.2
# 2019-02-02 1108 2018.3
#
# ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
[syn]
@ -40,6 +45,7 @@ i [Synth 8-3331] APP_SR_ACTIVE
I [Synth 8-6014] _reg # generic
# unused sequential element ------------------------------------
{2017.2:2018.2}
I [Synth 8-3332] R_LREGS_reg[attn][\d*] # generic
# --> usec unused # OK 2018-12-30
i [Synth 8-3332] R_REGS_reg[usec].* sys_tst_mig_n4d
@ -48,6 +54,7 @@ i [Synth 8-3332] R_BREGS_reg[stat][(0|1|2|3)].* sys_tst_mig_n4d
i [Synth 8-3332] R_LREGS_reg[(moneop|monattn)].* sys_tst_mig_n4d
# --> no rbinit used # OK 2018-12-30
i [Synth 8-3332] R_BREGS_reg[rbinit].* sys_tst_mig_n4d
{:}
# ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
[imp]

9
rtl/sys_gen/tst_rlink/arty/sys_tst_rlink_arty.vmfset
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@ -1,4 +1,9 @@
# $Id: sys_tst_rlink_arty.vmfset 1039 2018-08-12 10:04:09Z mueller $
# $Id: sys_tst_rlink_arty.vmfset 1108 2019-02-02 23:04:38Z mueller $
#
# Validated code/tool version combinations
# Date rev viv
# 2019-02-02 1108 2017.2
# 2019-02-02 1108 2018.3
#
# ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
[syn]
@ -17,6 +22,7 @@ i [Synth 8-3331] rlink_sp1c.*CE_USEC
I [Synth 8-6014] _reg # generic
# unused sequential element ------------------------------------
{2017.2:2018.2}
# --> many HIO pins not used # OK 2016-06-05
i [Synth 8-3332] IOB_(SWI|BTN)/R_DI_reg[\d*]
i [Synth 8-3332] DEB.DEB_(SWI|BTN)/R_REGS_reg[(dref|dout|dchange|cecnt)][\d*]
@ -29,6 +35,7 @@ i [Synth 8-3332] SERPORT/XONRX/R_REGS_reg[escseen]
i [Synth 8-3332] SERPORT/XONTX/R_REGS_reg[escpend]
# --> SER_MONI.rxovr indeed unused # OK 2016-06-05
i [Synth 8-3332] SERPORT/XONRX/R_REGS_reg[rxovr]
{:}
# ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
[imp]

9
rtl/sys_gen/tst_rlink/basys3/sys_tst_rlink_b3.vmfset
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@ -1,4 +1,9 @@
# $Id: sys_tst_rlink_b3.vmfset 1039 2018-08-12 10:04:09Z mueller $
# $Id: sys_tst_rlink_b3.vmfset 1108 2019-02-02 23:04:38Z mueller $
#
# Validated code/tool version combinations
# Date rev viv
# 2019-02-02 1108 2017.2
# 2019-02-02 1108 2018.3
#
# ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
[syn]
@ -17,6 +22,7 @@ i [Synth 8-3331] rlink_sp1c.*CE_USEC
I [Synth 8-6014] _reg # generic
# unused sequential element ------------------------------------
{2017.2:2018.2}
I [Synth 8-3332] R_REGS_reg[(btn|swi)(eff)?][\d*] # generic
# --> monitor outputs moneop,monattn currently not used # OK 2016-06-05
i [Synth 8-3332] CORE/RL/R_LREGS_reg[moneop]
@ -28,6 +34,7 @@ i [Synth 8-3332] SERPORT/XONRX/R_REGS_reg[escseen]
i [Synth 8-3332] SERPORT/XONTX/R_REGS_reg[escpend]
# --> SER_MONI.rxovr indeed unused # OK 2016-06-05
i [Synth 8-3332] SERPORT/XONRX/R_REGS_reg[rxovr]
{:}
# ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
[imp]

9
rtl/sys_gen/tst_rlink/cmoda7/sys_tst_rlink_c7.vmfset
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@ -1,4 +1,9 @@
# $Id: sys_tst_rlink_c7.vmfset 1039 2018-08-12 10:04:09Z mueller $
# $Id: sys_tst_rlink_c7.vmfset 1108 2019-02-02 23:04:38Z mueller $
#
# Validated code/tool version combinations
# Date rev viv
# 2019-02-02 1108 2017.2
# 2019-02-02 1108 2018.3
#
# ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
[syn]
@ -19,6 +24,7 @@ i [Synth 8-3331] I_BTN[\d+]
I [Synth 8-6014] _reg # generic
# unused sequential element ------------------------------------
{2017.2:2018.2}
# --> monitor outputs moneop,monattn currently not used # OK 2017-06-05
i [Synth 8-3332] CORE/RL/R_LREGS_reg[moneop]
i [Synth 8-3332] CORE/RL/R_LREGS_reg[monattn]
@ -27,6 +33,7 @@ i [Synth 8-3332] SERPORT/XONRX/R_REGS_reg[escseen]
i [Synth 8-3332] SERPORT/XONTX/R_REGS_reg[escpend]
# --> SER_MONI.rxovr indeed unused # OK 2017-06-05
i [Synth 8-3332] SERPORT/XONRX/R_REGS_reg[rxovr]
{:}
# ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
[imp]

16
rtl/sys_gen/tst_rlink/nexys2/sys_tst_rlink_n2.imfset
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@ -1,8 +1,7 @@
# $Id: sys_tst_rlink_n2.imfset 779 2016-06-26 15:37:16Z mueller $
# $Id: sys_tst_rlink_n2.imfset 1108 2019-02-02 23:04:38Z mueller $
#
# ----------------------------------------------------------------------------
[xst]
INFO:.*Mux is complete : default of case is discarded
Node <HIO/R_REGS.swieff_[1-7]> of sequential type is unconnected
Node <HIO/R_REGS.swi_[1-7]> of sequential type is unconnected
@ -14,11 +13,14 @@ Unconnected output port 'LOCKED' of component 'dcm_sfs'
Unconnected output port 'DOA' of component 'ram_1swar_1ar_gen'
Unconnected output port 'DOB' of component 'ram_2swsr_wfirst_gen'
Unconnected output port 'RL_MONI' of component 'rlink_sp1c'
Unconnected output port 'DOA' of component 'ram_2swsr_rfirst_gen'
Unconnected output port 'BUSY' of component 'fifo_1c_dram'
Input <I_MEM_WAIT> is never used
Input <RB_MREQ.din<\d+:\d+>> is never used
Input <RB_MREQ.init> is never used
Input <CE_USEC> is never used
Input <RB_MREQ\..*> is never used
Signal <L_DO<17:16>> is assigned but never used
Signal <FIFO_SIZE> is assigned but never used
@ -30,13 +32,21 @@ Signal <SER_MONI.rxerr> is assigned but never used
Signal <SER_MONI.abdone> is assigned but never used
Signal <STAT<7:2>> is assigned but never used
Signal <BTN> is assigned but never used
Signal <SER_MONI.abclkdiv_f> is assigned but never used
Signal <RB_SRES_RBMON\..*> is used but never assigned
FF/Latch <R_REGS.ledin_2> in Unit <sn_humanio_rbus> is equivalent
FF/Latch <R_REGS.rbre> in Unit <rlink_core> is equivalent
FF/Latch <R_REGS.ledin_2> has a constant value of 0
FF/Latch <R_REGS.ucnt_6> has a constant value of 0
FF/Latch <R_REGS.escseen> has a constant value of 0
FF/Latch <R_REGS.escpend> has a constant value of 0
Node <RLINK/SERPORT/XONRX/R_REGS.rxovr> of sequential type is unconnected
Node <RLINK/CORE/RL/R_LREGS.mon.*> of sequential type is unconnected
INFO:Xst:2261 .* is equivalent to
#
# ----------------------------------------------------------------------------
[tra]

9
rtl/sys_gen/tst_rlink/nexys4/sys_tst_rlink_n4.vmfset
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@ -1,4 +1,9 @@
# $Id: sys_tst_rlink_n4.vmfset 1039 2018-08-12 10:04:09Z mueller $
# $Id: sys_tst_rlink_n4.vmfset 1108 2019-02-02 23:04:38Z mueller $
#
# Validated code/tool version combinations
# Date rev viv
# 2019-02-02 1108 2017.2
# 2019-02-02 1108 2018.3
#
# ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
[syn]
@ -19,6 +24,7 @@ i [Synth 8-3331] rlink_sp1c.*CE_USEC
I [Synth 8-6014] _reg # generic
# unused sequential element ------------------------------------
{2017.2:2018.2}
I [Synth 8-3332] R_REGS_reg[(btn|swi)(eff)?][\d*] # generic
# --> monitor outputs moneop,monattn currently not used # OK 2016-06-05
i [Synth 8-3332] CORE/RL/R_LREGS_reg[moneop]
@ -30,6 +36,7 @@ i [Synth 8-3332] SERPORT/XONRX/R_REGS_reg[escseen]
i [Synth 8-3332] SERPORT/XONTX/R_REGS_reg[escpend]
# --> SER_MONI.rxovr indeed unused # OK 2016-06-05
i [Synth 8-3332] SERPORT/XONRX/R_REGS_reg[rxovr]
{:}
# ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
[imp]

51
rtl/sys_gen/tst_rlink_cuff/nexys2/ic/sys_tst_rlink_cuff_ic_n2.imfset
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@ -1,21 +1,27 @@
# $Id: sys_tst_rlink_cuff_ic_n2.imfset 769 2016-05-28 11:36:22Z mueller $
# $Id: sys_tst_rlink_cuff_ic_n2.imfset 1108 2019-02-02 23:04:38Z mueller $
#
# ----------------------------------------------------------------------------
[xst]
INFO:.*Mux is complete : default of case is discarded
Register <R_MONI_C.fifo_ep8> in unit <fx2_2fifoctl_ic> has a constant value
Register <R_MONI_C.flag_ep8_full> in unit <fx2_2fifoctl_ic> has a constant value
Register <R_MONI_C.flag_ep8_almost> in unit <fx2_2fifoctl_ic> has a constant value
Register <R_MONI_S.flag_ep8_almost> in unit <fx2_2fifoctl_ic> has a constant value
Register <R_MONI_S.flag_ep8_full> in unit <fx2_2fifoctl_ic> has a constant value
INFO:Xst:3029 .* LUT implementation is currently selected
INFO:Xst:2261 .* is equivalent to
Value "none" of property "fsm_encoding" not applicable
Register <R_MONI_S.flag_ep8.*> in unit <fx2_2fifoctl_ic> has a constant value
Register <R_MONI_S.fsm_tx2> in unit <fx2_2fifoctl_ic> has a constant value
Register <R_MONI_S.fifo_ep8> in unit <fx2_2fifoctl_ic> has a constant value
Register <R_MONI_C.fifo_ep8> in unit <fx2_2fifoctl_ic> has a constant value
Register <R_MONI_C.flag_ep8_.*> in unit <fx2_2fifoctl_ic> has a constant value
Register <R_MONI_C.fsm_tx2> in unit <fx2_2fifoctl_ic> has a constant value
Unconnected output port 'SIZE' of component 'fifo_1c_dram'
Unconnected output port 'LOCKED' of component 'dcm_sfs'
Unconnected output port 'DOA' of component 'ram_1swar_1ar_gen'
Unconnected output port 'DOB' of component 'ram_2swsr_wfirst_gen'
Unconnected output port 'RL_MONI' of component 'rlink_core8'
Unconnected output port 'BUSY' of component 'fifo_1c_dram'
Unconnected output port 'DOA' of component 'ram_2swsr_rfirst_gen'
Input <I_MEM_WAIT> is never used
Input <RB_MREQ.din<\d+:\d+>> is never used
@ -23,18 +29,8 @@ Input <RB_MREQ.init> is never used
Input <BTN> is never used
Input <SWI<7:3>> is never used
Input <SWI<0>> is never used
Input <FX2_MONI.pktend> is never used
Input <FX2_MONI.slrd> is never used
Input <FX2_MONI.slwr> is never used
Input <FX2_MONI.flag_ep4_empty> is never used
Input <FX2_MONI.flag_ep4_almost> is never used
Input <FX2_MONI.flag_ep6_full> is never used
Input <FX2_MONI.flag_ep6_almost> is never used
Input <FX2_MONI.flag_ep8_full> is never used
Input <FX2_MONI.flag_ep8_almost> is never used
Input <FX2_MONI.fifo_ep4> is never used
Input <FX2_MONI.fifo_ep6> is never used
Input <FX2_MONI.fifo_ep8> is never used
Input <FX2_MONI\..*> is never used
Input <RB_MREQ\..*> is never used
Output <FX2_TX2DATA> is never assigned
@ -42,9 +38,7 @@ Signal <L_DO<17:16>> is assigned but never used
Signal <FIFO_SIZE> is assigned but never used
Signal <RXFIFO_SIZE<2:0>> is assigned but never used
Signal <RB_LAM_TEST<1:0>> is assigned but never used
Signal <SER_MONI.rxovr> is assigned but never used
Signal <SER_MONI.rxerr> is assigned but never used
Signal <SER_MONI.abdone> is assigned but never used
Signal <SER_MONI\..*> is assigned but never used
Signal <STAT<7:2>> is assigned but never used
Signal <FX2_FLAG_N<3>> is assigned but never used
Signal <FX2_TXAFULL> is assigned but never used
@ -52,6 +46,7 @@ Signal <FX2_RXAEMPTY> is assigned but never used
Signal <FX2_TX2ENA> is assigned but never used
Signal <FX2_TX2DATA> is assigned but never used
Signal <TXSIZE_FX2> is assigned but never used
Signal <RXFIFO_BUSY> is assigned but never used
Signal <FX2_TX2ENA_L> is used but never assigned
Signal <RESET> is used but never assigned
@ -59,26 +54,24 @@ Signal <FX2_TX2BUSY> is used but never assigned
Signal <FX2_TX2AFULL> is never used or assigned
FF/Latch <R_REGS.rbre> in Unit <rlink_core> is equivalent
FF/Latch <R_REGS.ucnt_6> has a constant value of 0
FF/Latch <HIO/R_REGS.ledin_[2-6]> has a constant value of 0
FF/Latch <R_REGS.rxpipe> has a constant value of 0
FF/Latch <FX2_CNTL_IC.CNTL/[RT]XFIFO/R_REG[RW].rst[rw]> has a constant value of 0
FF/Latch <FX2_CNTL_IC.CNTL/[RT]XFIFO/R_REG[RW].rst[rw]_(c|s|sc|ss)> has a constant value of 0
FF/Latch <R_REGS.escseen> has a constant value
FF/Latch <R_REGS.escpend> has a constant value
Node <HIO/R_REGS.swieff_[3-7]> of sequential type is unconnected
Node <HIO/R_REGS.swi_[3-7]> of sequential type is unconnected
Node <HIO/R_REGS.btn_[0-3]> of sequential type is unconnected
Node <HIO/R_REGS.btneff_[0-3]> of sequential type is unconnected
Node <TST/SERPORT/XONRX/R_REGS.rxovr> of sequential type is unconnected
Node <TST/RLCORE/RL/R_REGS.moneop> of sequential type is unconnected
Node <TST/RLCORE/RL/R_REGS.monlamp> of sequential type is unconnected
Node <TST/RLCORE/RL/R_REGS.monattn> of sequential type is unconnected
Node <FX2_CNTL_IC.CNTL/R_MONI_S..*> of sequential type is unconnected
Node <FX2_CNTL_IC.CNTL/R_MONI_C..*> of sequential type is unconnected
Node <FX2_CNTL_IC.CNTL/R_REGS..*> of sequential type is unconnected
Node <TST/RLCORE/RL/R_LREGS.moneop> of sequential type is unconnected
Node <TST/RLCORE/RL/R_LREGS.monattn> of sequential type is unconnected
Node <FX2_CNTL_IC.CNTL/[RT]XFIFO/R_REG[RW].size[rw]_[0-4]> of sequential type is unconnected
#
# ----------------------------------------------------------------------------

50
rtl/sys_gen/tst_rlink_cuff/nexys3/ic/sys_tst_rlink_cuff_ic_n3.imfset
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@ -1,14 +1,21 @@
# $Id: sys_tst_rlink_cuff_ic_n3.imfset 769 2016-05-28 11:36:22Z mueller $
# $Id: sys_tst_rlink_cuff_ic_n3.imfset 1108 2019-02-02 23:04:38Z mueller $
#
# ----------------------------------------------------------------------------
[xst]
INFO:Xst:3216 .* LUT implementation is currently selected
INFO:Xst:3231 .* will be implemented on LUTs
INFO:Xst:1901 .* has been replaced by RAMB16
INFO:Xst:2261 .* is equivalent to
INFO:Xst:3203 .* is the opposite to
Value "none" of property "fsm_encoding" is not applicable
Case statement is complete. others clause is never selected
Using initial value '0' for reset since it is never assigned
Using initial value '0' for fx2_tx2ena_l since it is never assigned
Net <FX2_TX2BUSY> does not have a driver.
Output port <LOCKED> of the instance <DCM> is unconnected
Output port <RXAEMPTY> of the instance <FX2_CNTL_IC.CNTL> is unconnected
Output port <TXAFULL> of the instance <FX2_CNTL_IC.CNTL> is unconnected
Output port <FX2_TX2DATA> of the instance <TST> is unconnected
@ -24,6 +31,11 @@ Output port <MONI_abdone> of the instance <SERPORT> is unconnected
Output port <SIZE> of the instance <TXFIFO> is unconnected or connected
Output port <SIZE> of the instance <FIFO> is unconnected or connected
Output port <DOB> of the instance <BRAM> is unconnected
Output port <BUSY> of the instance <RXFIFO> is unconnected
Output port <MONI_abclkdiv_f> of the instance <SERPORT> is unconnected
Output port <DOA> of the instance <RTBUF> is unconnected
Output port <BUSY> of the instance <DOFIFO> is unconnected
Output port <LOCKED> of the instance <GEN_CLKSYS> is unconnected
Signal <FX2_TX2DATA> is used but never assigned
@ -34,51 +46,30 @@ Node <FX2_CNTL_IC.CNTL/R_REGS_moni_ep6_sel> of sequential type is unconnected
Node <FX2_CNTL_IC.CNTL/R_REGS_moni_ep6_pf> of sequential type is unconnected
Node <FX2_CNTL_IC.CNTL/R_REGS_moni_ep4_pf> of sequential type is unconnected
ode <FX2_CNTL_IC.CNTL/R_REGS_moni_ep4_sel> of sequential type is unconnected
Node <IOB_FX2_FLAG/R_DI_3> of sequential type is unconnected
Node <HIO/R_REGS_swieff_[3-7]> of sequential type is unconnected
Node <HIO/R_REGS_btn_[0-4]> of sequential type is unconnected
Node <HIO/R_REGS_swi_[3-7]> of sequential type is unconnected
Node <HIO/R_REGS_btneff_[0-4]> of sequential type is unconnected
Node <FX2_CNTL_IC.CNTL/[RT]XFIFO/R_REG[RW]_size[rw]_\d> of sequential type is unconnected
Node <TST/RLCORE/RL/R_REGS_monattn> of sequential type is unconnected
Node <TST/RLCORE/RL/R_REGS_monlamp> of sequential type is unconnected
Node <TST/RLCORE/RL/R_REGS_moneop> of sequential type is unconnected
Node <TST/SERPORT/XONRX/R_REGS_rxovr> of sequential type is unconnected
Node <TST/RLCORE/RL/R_LREGS_mon.*> of sequential type is unconnected
Input <RB_MREQ_init> is never used
Input <RB_MREQ_din<15:10>> is never used
Input <I_MEM_WAIT> is never used
Input <SWI<7:3>> is never used
Input <SWI<0:0>> is never used
Input <BTN<3:0>> is never used
Input <FX2_MONI_fifo_ep4> is never used
Input <FX2_MONI_fifo_ep6> is never used
Input <FX2_MONI_fifo_ep8> is never used
Input <FX2_MONI_flag_ep4_empty> is never used
Input <FX2_MONI_flag_ep4_almost> is never used
Input <FX2_MONI_flag_ep6_full> is never used
Input <FX2_MONI_flag_ep6_almost> is never used
Input <FX2_MONI_flag_ep8_full> is never used
Input <FX2_MONI_flag_ep8_almost> is never used
Input <FX2_MONI_slrd> is never used
Input <FX2_MONI_slwr> is never used
Input <FX2_MONI_pktend> is never used
Input <FX2_MONI_.*> is never used
Input <BTN> is never used
Input <RB_MREQ_.*> is never used
FF/Latch <R_MONI_[CS]_.*> has a constant value of 0
FF/Latch <TX2ENA_PSTR/R_REGS_busy_1> has a constant value
FF/Latch <TX2ENA_PSTR/R_REGS_busy_0> has a constant value
of type RAMB16_S18 has been replaced by RAMB16BWER
of type RAMB16_S36 has been replaced by RAMB16BWER
of type RAMB16_S36_S36 has been replaced by RAMB16BWER
FF/Latch <HIO/R_REGS_ledin_[2-6]> has a constant value of 0
FF/Latch <FX2_CNTL_IC.CNTL/[RT]XFIFO/R_REG[RW]_rst.*> has a constant value
The FF/Latch <R_REGS_rbre> .* is equivalent
The FF/Latch <HIO/HIO/HIO/DEB.DEB_SWI/R_REGS_cecnt_[01]> .* is equivalent
The FF/Latch <HIO/HIO/DRV/R_REGS_cdiv_0> .* is the opposite
#
# ----------------------------------------------------------------------------
[tra]
@ -87,13 +78,12 @@ The FF/Latch <HIO/HIO/DRV/R_REGS_cdiv_0> .* is the opposite
# ----------------------------------------------------------------------------
[map]
INFO:.*
Signal I_FX2_FLAG<3> .* has been removed
#
# ----------------------------------------------------------------------------
[par]
The signal I_MEM_WAIT_IBUF has no load
The signal I_FX2_FLAG<3>_IBUF has no load
There are 2 loadless signals in this design
There are \d* loadless signals in this design
#
# ----------------------------------------------------------------------------

9
rtl/sys_gen/tst_serloop/nexys4/sys_tst_serloop1_n4.vmfset
View File

@ -1,4 +1,9 @@
# $Id: sys_tst_serloop1_n4.vmfset 1039 2018-08-12 10:04:09Z mueller $
# $Id: sys_tst_serloop1_n4.vmfset 1108 2019-02-02 23:04:38Z mueller $
#
# Validated code/tool version combinations
# Date rev viv
# 2019-02-02 1108 2017.2
# 2019-02-02 1108 2018.3
#
# ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
[syn]
@ -34,9 +39,11 @@ i [Synth 8-3331] HIO_CNTL[enaftdi]
I [Synth 8-6014] _reg # generic
# unused sequential element ------------------------------------
{2017.2:2018.2}
# --> many HIO pins not used # OK 2016-06-05
i [Synth 8-3332] HIO/IOB_(SWI|BTN)/R_DI_reg[\d*]
i [Synth 8-3332] HIO/DEB.DEB_(SWI|BTN)/R_REGS_reg[(dref|dout|dchange)][\d*]
{:}
# +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
[imp]

9
rtl/sys_gen/tst_serloop/nexys4/sys_tst_serloop2_n4.vmfset
View File

@ -1,4 +1,9 @@
# $Id: sys_tst_serloop2_n4.vmfset 1097 2018-12-29 11:20:14Z mueller $
# $Id: sys_tst_serloop2_n4.vmfset 1108 2019-02-02 23:04:38Z mueller $
#
# Validated code/tool version combinations
# Date rev viv
# 2019-02-02 1108 2017.2
# 2019-02-02 1108 2018.3
#
# ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
[syn]
@ -36,12 +41,14 @@ i [Synth 8-3331] HIO_CNTL[enaftdi]
I [Synth 8-6014] _reg # generic
# unused sequential element ------------------------------------
{2017.2:2018.2}
I [Synth 8-3332] R_REGS_reg[(btn|swi)(eff)?][\d*] # generic
# --> currently CDUWIDTH=8, but clock below 127 MHz # OK 2018-12-29
i [Synth 8-3332] GEN_CLKALL/DIV_CLK0/R_REGS_reg[ucnt][7]
# --> many HIO pins not used # OK 2016-06-05
i [Synth 8-3332] HIO/IOB_(SWI|BTN)/R_DI_reg[\d*]
i [Synth 8-3332] HIO/DEB.DEB_(SWI|BTN)/R_REGS_reg[(dref|dout|dchange)][\d*]
{:}
# ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
[imp]

22
rtl/sys_gen/tst_serloop/s3board/sys_tst_serloop_s3.imfset
View File

@ -1,9 +1,7 @@
# $Id: sys_tst_serloop_s3.imfset 769 2016-05-28 11:36:22Z mueller $
# $Id: sys_tst_serloop_s3.imfset 1108 2019-02-02 23:04:38Z mueller $
#
# ----------------------------------------------------------------------------
[xst]
INFO:.*Mux is complete : default of case is discarded
Unconnected output port 'LOCKED' of component 'dcm_sfs'
Unconnected output port 'SIZE' of component 'fifo_1c_dram'
Unconnected output port 'DOA' of component 'ram_1swar_1ar_gen'
@ -12,10 +10,22 @@ Input <BTN<3:2>> is never used
Input <BTN<0>> is never used
Input <SWI<3>> is never used
Input <SWI<0>> is never used
Input <SER_MONI\..*> is never used.
Input <HIO_CNTL.enaftdi> is never used
Signal <RXFIFO_SIZE<2:0>> is assigned but never used
Signal <CE_USEC> is assigned but never used
Node <HIOMAP/R_REGS.enaftdi> of sequential type is unconnected
Node <CLKDIV/R_REGS.usec> of sequential type is unconnected in
Node <HIO/HIO/IOB_BTN/R_DI_\d> of sequential type is unconnected
Node <HIO/HIO/IOB_SWI/R_DI_\d> of sequential type is unconnected
Node <HIO/HIO/DEB.DEB_SWI/R_REGS.dout_\d> of sequential type is unconnected
Node <HIO/HIO/DEB.DEB_BTN/R_REGS.dout_\d> of sequential type is unconnected
Node <HIO/HIO/DEB.DEB_SWI/R_REGS.dchange_\d> of sequential type is unconnected
Node <HIO/HIO/DEB.DEB_BTN/R_REGS.dchange_\d> of sequential type is unconnected
Node <HIO/HIO/DEB.DEB_SWI/R_REGS.dref_\d> of sequential type is unconnected
Node <HIO/HIO/DEB.DEB_BTN/R_REGS.dref_\d> of sequential type is unconnected
#
# ----------------------------------------------------------------------------
[tra]
@ -24,11 +34,17 @@ Signal <CE_USEC> is assigned but never used
# ----------------------------------------------------------------------------
[map]
INFO:.*
WARNING:LIT:162 .* Proper phase relationship
#
# ----------------------------------------------------------------------------
[par]
The signal I_SWI<3>_IBUF has no load
The signal I_BTN<2>_IBUF has no load
The signal I_BTN<3>_IBUF has no load
There are \d+ loadless signals in this design
#
# ----------------------------------------------------------------------------
[bgn]
INFO:PhysDesignRules:772 .* To achieve optimal frequency synthesis performance

7
rtl/sys_gen/tst_snhumanio/basys3/sys_tst_snhumanio_b3.vmfset
View File

@ -1,4 +1,9 @@
# $Id: sys_tst_snhumanio_b3.vmfset 1039 2018-08-12 10:04:09Z mueller $
# $Id: sys_tst_snhumanio_b3.vmfset 1108 2019-02-02 23:04:38Z mueller $
#
# Validated code/tool version combinations
# Date rev viv
# 2019-02-02 1108 2017.2
# 2019-02-02 1108 2018.3
#
# ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
[syn]

3
rtl/sys_gen/tst_snhumanio/nexys2/sys_tst_snhumanio_n2.imfset
View File

@ -1,8 +1,7 @@
# $Id: sys_tst_snhumanio_n2.imfset 769 2016-05-28 11:36:22Z mueller $
# $Id: sys_tst_snhumanio_n2.imfset 1108 2019-02-02 23:04:38Z mueller $
#
# ----------------------------------------------------------------------------
[xst]
INFO:.*Mux is complete : default of case is discarded
Unconnected output port 'CE_USEC' of component 'clkdivce'

7
rtl/sys_gen/tst_snhumanio/nexys4/sys_tst_snhumanio_n4.vmfset
View File

@ -1,4 +1,9 @@
# $Id: sys_tst_snhumanio_n4.vmfset 1039 2018-08-12 10:04:09Z mueller $
# $Id: sys_tst_snhumanio_n4.vmfset 1108 2019-02-02 23:04:38Z mueller $
#
# Validated code/tool version combinations
# Date rev viv
# 2019-02-02 1108 2017.2
# 2019-02-02 1108 2018.3
#
# ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
[syn]

3
rtl/sys_gen/tst_snhumanio/s3board/sys_tst_snhumanio_s3.imfset
View File

@ -1,8 +1,7 @@
# $Id: sys_tst_snhumanio_s3.imfset 769 2016-05-28 11:36:22Z mueller $
# $Id: sys_tst_snhumanio_s3.imfset 1108 2019-02-02 23:04:38Z mueller $
#
# ----------------------------------------------------------------------------
[xst]
INFO:.*Mux is complete : default of case is discarded
Unconnected output port 'CE_USEC' of component 'clkdivce'

9
rtl/sys_gen/tst_sram/arty/sys_tst_sram_arty.vmfset
View File

@ -1,4 +1,9 @@
# $Id: sys_tst_sram_arty.vmfset 1101 2019-01-02 21:22:37Z mueller $
# $Id: sys_tst_sram_arty.vmfset 1108 2019-02-02 23:04:38Z mueller $
#
# Validated code/tool version combinations
# Date rev viv
# 2019-02-02 1108 2017.2
# 2019-02-02 1108 2018.3
#
# ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
[syn]
@ -37,7 +42,7 @@ I [Synth 8-6014] _reg # generic
# unused sequential element ------------------------------------
I [Synth 8-3332] R_LREGS_reg[attn][\d*] # generic
{:}
{2017.2:2018.2}
# --> only 18 bit address # OK 2018-12-22
i [Synth 8-3332] R_REGS_reg[wrtag][1(6|7)].* sramif2migui_core
i [Synth 8-3332] R_REGS_reg[rdtag][1(6|7)].* sramif2migui_core

24
rtl/sys_gen/tst_sram/cmoda7/sys_tst_sram_c7.vmfset
View File

@ -1,4 +1,9 @@
# $Id: sys_tst_sram_c7.vmfset 1097 2018-12-29 11:20:14Z mueller $
# $Id: sys_tst_sram_c7.vmfset 1108 2019-02-02 23:04:38Z mueller $
#
# Validated code/tool version combinations
# Date rev viv
# 2019-02-02 1108 2017.2
# 2019-02-02 1108 2018.3
#
# ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
[syn]
@ -33,7 +38,7 @@ i [Synth 8-3331] rlink_sp2c.*CE_(USEC|MSEC)
I [Synth 8-6014] _reg # generic
# unused sequential element ------------------------------------
{:2017.4}
{2017.2:2018.2}
I [Synth 8-3332] R_LREGS_reg[attn][\d*] # generic
# --> many HIO pins not used # OK 2017-06-11
i [Synth 8-3332] HIO/R_REGS_reg[led][\d*]
@ -49,20 +54,7 @@ i [Synth 8-3332] GEN_CLKALL/DIV_CLK0/R_REGS_reg[usec]
# --> CES_USEC isn't used # OK 2018-12-29
i [Synth 8-3332] GEN_CLKALL/DIV_CLK1/R_REGS_reg[usec]
{2018.1:}
I [Synth 8-3332] R_LREGS_reg[attn][\d*] # generic
# --> many HIO pins not used # OK 2018-08-12
i [Synth 8-3332] R_REGS_reg[led][\d*].* sn_humanio_emu_rbus
i [Synth 8-3332] R_REGS_reg[dsp_dp][\d*].* sn_humanio_emu_rbus
i [Synth 8-3332] R_REGS_reg[dsp_dat][\d*].* sn_humanio_emu_rbus
# --> monitor outputs moneop,monattn currently not used # OK 2018-08-12
i [Synth 8-3332] CORE/RL/R_LREGS_reg[moneop]
i [Synth 8-3332] CORE/RL/R_LREGS_reg[monattn]
# --> only RB_STAT 0,1 used by tst_sram # OK 2018-08-12
i [Synth 8-3332] CORE/RL/R_BREGS_reg[stat][(2|3)]
# --> CE_USEC isn't used (also not in rlink_sp2c) # OK 2018-08-12
# --> CES_USEC isn't used # OK 2018-08-12
i [Synth 8-3332] R_REGS_reg[usec].* clkdivce
{:}
# ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
[imp]

20
rtl/sys_gen/tst_sram/nexys4/sys_tst_sram_n4.vmfset
View File

@ -1,4 +1,9 @@
# $Id: sys_tst_sram_n4.vmfset 1097 2018-12-29 11:20:14Z mueller $
# $Id: sys_tst_sram_n4.vmfset 1108 2019-02-02 23:04:38Z mueller $
#
# Validated code/tool version combinations
# Date rev viv
# 2019-02-02 1108 2017.2
# 2019-02-02 1108 2018.3
#
# ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
[syn]
@ -33,13 +38,12 @@ i [Synth 8-3331] rlink_sp2c.*CE_(USEC|MSEC)
I [Synth 8-6014] _reg # generic
# unused sequential element ------------------------------------
{2017.2:2018.2}
I [Synth 8-3332] R_LREGS_reg[attn][\d*] # generic
# --> many HIO pins not used # OK 2016-06-05
i [Synth 8-3332] HIO/IOB_LED/R_DO_reg[\d*]
i [Synth 8-3332] HIO/IOB_(SWI|BTN)/R_DI_reg[\d*]
i [Synth 8-3332] HIO/DEB.DEB_(SWI|BTN)/R_REGS_reg[(dref|dout|dchange)][\d*]
{:2017.4}
# --> monitor outputs moneop,monattn currently not used # OK 2016-06-05
i [Synth 8-3332] RLINK/CORE/RL/R_LREGS_reg[moneop]
i [Synth 8-3332] RLINK/CORE/RL/R_LREGS_reg[monattn]
@ -50,15 +54,7 @@ i [Synth 8-3332] CLKALL/DIV_CLK0/R_REGS_reg[usec]
# --> CES_USEC isn't used # OK 2018-12-29
i [Synth 8-3332] GEN_CLKALL/DIV_CLK1/R_REGS_reg[usec]
{2018.1:}
# --> monitor outputs moneop,monattn currently not used # OK 2018-08-12
i [Synth 8-3332] CORE/RL/R_LREGS_reg[moneop]
i [Synth 8-3332] CORE/RL/R_LREGS_reg[monattn]
# --> only RB_STAT 0,1 used by tst_sram # OK 2018-08-12
i [Synth 8-3332] CORE/RL/R_BREGS_reg[stat][(2|3)]
# --> CE_USEC isn't used (also not in rlink_sp2c) # OK 2018-08-12
# --> CES_USEC isn't used # OK 2018-08-12
i [Synth 8-3332] R_REGS_reg[usec].* module clkdivce
{:}
# ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
[imp]

10
rtl/sys_gen/tst_sram/nexys4d/sys_tst_sram_n4d.vmfset
View File

@ -1,4 +1,9 @@
# $Id: sys_tst_sram_n4d.vmfset 1101 2019-01-02 21:22:37Z mueller $
# $Id: sys_tst_sram_n4d.vmfset 1108 2019-02-02 23:04:38Z mueller $
#
# Validated code/tool version combinations
# Date rev viv
# 2019-02-02 1108 2017.2
# 2019-02-02 1108 2018.3
#
# ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
[syn]
@ -33,6 +38,7 @@ i [Synth 8-3331] sramif2migui_core .*APP_RD_DATA_END
I [Synth 8-6014] _reg # generic
# unused sequential element ------------------------------------
{2017.2:2018.2}
I [Synth 8-3332] R_LREGS_reg[attn][\d*] # generic
# --> only 18 bit address # OK 2019-01-02
i [Synth 8-3332] R_REGS_reg[wrtag][1(6|7)].* sramif2migui_core
@ -55,6 +61,8 @@ i [Synth 8-3332] CLKALL/DIV_CLK0/R_REGS_reg[usec]
# --> CES_USEC isn't used # OK 2019-01-02
i [Synth 8-3332] GEN_CLKALL/DIV_CLK1/R_REGS_reg[usec]
{:}
# ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
[imp]
I [Vivado 12-2489] # multiple of 1 ps

9
rtl/sys_gen/w11a/arty/sys_w11a_arty.vmfset
View File

@ -1,4 +1,9 @@
# $Id: sys_w11a_arty.vmfset 1101 2019-01-02 21:22:37Z mueller $
# $Id: sys_w11a_arty.vmfset 1108 2019-02-02 23:04:38Z mueller $
#
# Validated code/tool version combinations
# Date rev viv
# 2019-02-02 1108 2017.2
# 2019-02-02 1108 2018.3
#
# ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
[syn]
@ -51,6 +56,7 @@ i [Synth 8-3331] sramif2migui_core .*APP_RD_DATA_END
I [Synth 8-6014] _reg # generic
# unused sequential element ------------------------------------
{2017.2:2018.2}
I [Synth 8-3332] R_LREGS_reg[attn][\d*] # generic
# --> many HIO pins not used # OK 2018-12-28
@ -78,6 +84,7 @@ i [Synth 8-3332] R_STATUS_reg[intvect][8].* pdp11_sequencer
i [Synth 8-3332] R_IDSTAT_reg[res_sel][2].* pdp11_sequencer
# --> scnt disabled, thus 3 SNUM bits '0' # OK 2018-12-28
i [Synth 8-3332] R_REGS_reg[se_snum][(4|5|6)]
{:}
# INFO: encoded FSM with state register as --------------------

90
rtl/sys_gen/w11a/arty_bram/sys_w11a_br_arty.vmfset
View File

@ -1,4 +1,9 @@
# $Id: sys_w11a_br_arty.vmfset 1091 2018-12-23 12:38:29Z mueller $
# $Id: sys_w11a_br_arty.vmfset 1108 2019-02-02 23:04:38Z mueller $
#
# Validated code/tool version combinations
# Date rev viv
# 2019-02-02 1108 2017.2
# 2019-02-02 1108 2018.3
#
# ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
[syn]
@ -51,39 +56,7 @@ i [Synth 8-3331] ibd_iist .* EI_ACK
I [Synth 8-6014] _reg # generic
# unused sequential element ------------------------------------
{:2016.4}
I [Synth 8-3332] R_LREGS_reg[attn][\d*] # generic
# --> many HIO pins not used # OK 2016-06-05
I [Synth 8-3332] HIO/R_REGS_reg[(btn|swi)(eff)?][\d*]
i [Synth 8-3332] HIO/IOB_BTN/R_DI_reg[\d*]
i [Synth 8-3332] HIO/DEB.DEB_BTN/R_REGS_reg[(dref|dout|dchange|cecnt)][\d*]
# --> usec not used for serport clock domain # OK 2016-06-05
i [Synth 8-3332] CLKDIV_CLKS/R_REGS_reg[usec]
# --> inst_compl logic disabled in pdp11_mmu # OK 2016-06-05
i [Synth 8-3332] VMBOX/MMU/R_SSR0_reg[inst_compl]
# --> IB_MREQ.cacc only used in ibd_ibmon, which is disabled # OK 2016-06-05
i [Synth 8-3332] VMBOX/R_REGS_reg[ibcacc]
# --> not yet used # OK 2016-06-05
i [Synth 8-3332] SEQ/R_STATUS_reg[suspext]
# --> mawidth=4, nblock=11, so some cellen unused # OK 2016-06-05
i [Synth 8-3332] BRAM_CTL/R_REGS_reg[cellen][1\d]
# --> indeed no types with [3] set # OK 2016-06-05
i [Synth 8-3332] R_REGS_reg[dtyp][3].*ibdr_rhrp
# --> not yet used # OK 2016-06-05
i [Synth 8-3332] R_REGS_reg[req_lock].*ibd_iist
i [Synth 8-3332] R_REGS_reg[req_boot].*ibd_iist
# --> [8] is for DZ11TX, not yet available # OK 2016-06-05
# --> [9] is for DZ11RX, unclear why this one isn't removed too !!
i [Synth 8-3332] SEQ/R_STATUS_reg[intvect][8]
# --> _decode only uses _[oalm]unit -> [2] always '0' in decode # OK 2016-06-05
i [Synth 8-3332] SEQ/R_IDSTAT_reg[res_sel][2]
# --> monitor outputs moneop,monattn currently not used # OK 2016-06-05
i [Synth 8-3332] RLINK/CORE/RL/R_LREGS_reg[moneop]
i [Synth 8-3332] RLINK/CORE/RL/R_LREGS_reg[monattn]
# --> dmcmon not configured, snum not used # OK 2017-06-06
i [Synth 8-3332] SEQ/SNUM0.R_VMWAIT_reg
{2017.1:2017.4}
{2017.2:2018.2}
I [Synth 8-3332] R_LREGS_reg[attn][\d*] # generic
# --> many HIO pins not used # OK 2018-10-13
@ -105,8 +78,6 @@ i [Synth 8-3332] CORE/RL/R_LREGS_reg[monattn]
# --> PERFEXT(0:2) not used # OK 2018-10-13
i [Synth 8-3332] R_REGS_reg[psig][2(4|5|6)]
i [Synth 8-3332] PRE[2(4|5|6)].ENA.CNT/R_CNT_reg[\d*]
{2017.1:2017.3}
# --> inst_compl logic disabled in pdp11_mmu # OK 2017-06-06
i [Synth 8-3332] MMU/R_SSR0_reg[inst_compl].* pdp11_vmbox
# --> IB_MREQ.cacc only used in ibd_ibmon, which is disabled # OK 2017-06-06
@ -123,53 +94,6 @@ i [Synth 8-3332] SNUM0.R_VMWAIT_reg.* pdp11_sequencer # OK 2017-06-06
# --> mawidth=4, nblock=11, so some cellen unused # OK 2018-10-13
i [Synth 8-3332] R_REGS_reg[cellen][1\d]
{2017.4}
# --> inst_compl logic disabled in pdp11_mmu # OK 2017-06-06
i [Synth 8-3332] MMU/R_SSR0_reg[inst_compl].* pdp11_core
# --> IB_MREQ.cacc only used in ibd_ibmon, which is disabled # OK 2018-08-11
i [Synth 8-3332] R_REGS_reg[ibcacc].* pdp11_core
# --> not yet used # OK 2018-08-11
i [Synth 8-3332] R_STATUS_reg[suspext].* pdp11_core
# --> [8] is for DZ11TX, not yet available # OK 2018-08-11
# --> [9] is for DZ11RX, unclear why this one isn't removed too !!
i [Synth 8-3332] R_STATUS_reg[intvect][8].* pdp11_core
# --> _decode only uses _[oalm]unit -> [2] always '0' in decode # OK 2018-08-11
i [Synth 8-3332] R_IDSTAT_reg[res_sel][2].* pdp11_core
# --> dmcmon not configured, snum not used # OK 2018-08-11
i [Synth 8-3332] SNUM0.R_VMWAIT_reg.* pdp11_core # OK 2018-08-11
{2018.1:}
I [Synth 8-3332] R_LREGS_reg[attn][\d*] # generic
# --> many HIO pins not used # OK 2017-06-06
I [Synth 8-3332] HIO/R_REGS_reg[(btn|swi)(eff)?][\d*]
i [Synth 8-3332] IOB_BTN/R_DI_reg[\d*]
i [Synth 8-3332] DEB.DEB_BTN/R_REGS_reg[(dref|dout|dchange|cecnt)][\d*]
# --> usec not used for serport clock domain # OK 2017-06-06
i [Synth 8-3332] R_REGS_reg[usec]
# --> mawidth=4, nblock=11, so some cellen unused # OK 2018-08-11
i [Synth 8-3332] R_REGS_reg[cellen][1\d]
# --> indeed no types with [3] set # OK 2017-06-06
i [Synth 8-3332] R_REGS_reg[dtyp][3].* ibdr_rhrp
# --> not yet used # OK 2017-06-06
i [Synth 8-3332] R_REGS_reg[req_lock].* ibd_iist
i [Synth 8-3332] R_REGS_reg[req_boot].* ibd_iist
# --> monitor outputs moneop,monattn currently not used # OK 2018-08-11
i [Synth 8-3332] CORE/RL/R_LREGS_reg[moneop]
i [Synth 8-3332] CORE/RL/R_LREGS_reg[monattn]
# --> inst_compl logic disabled in pdp11_mmu # OK 2017-06-06
i [Synth 8-3332] MMU/R_SSR0_reg[inst_compl].* pdp11_core
# --> IB_MREQ.cacc only used in ibd_ibmon, which is disabled # OK 2018-08-11
i [Synth 8-3332] R_REGS_reg[ibcacc].* pdp11_core
# --> not yet used # OK 2018-08-11
i [Synth 8-3332] R_STATUS_reg[suspext].* pdp11_sequencer
# --> [8] is for DZ11TX, not yet available # OK 2017-06-06
# --> [9] is for DZ11RX, unclear why this one isn't removed too !!
i [Synth 8-3332] R_STATUS_reg[intvect][8].* pdp11_sequencer
# --> _decode only uses _[oalm]unit -> [2] always '0' in decode # OK 2018-08-11
i [Synth 8-3332] R_IDSTAT_reg[res_sel][2].* pdp11_sequencer
# --> dmcmon not configured, snum not used
i [Synth 8-3332] SNUM0.R_VMWAIT_reg.* pdp11_sequencer # OK 2018-08-11
{:}
# INFO: encoded FSM with state register as --------------------

37
rtl/sys_gen/w11a/artys7/sys_w11a_as7.vmfset
View File

@ -1,4 +1,8 @@
# $Id: sys_w11a_as7.vmfset 1105 2019-01-12 19:52:45Z mueller $
# $Id: sys_w11a_as7.vmfset 1108 2019-02-02 23:04:38Z mueller $
#
# Validated code/tool version combinations
# Date rev viv
# 2019-02-02 1108 2018.3
#
# ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
[syn]
@ -52,37 +56,6 @@ i [Synth 8-3331] sramif2migui_core .*APP_RD_DATA_END
# sequential element removed (2017.1 nonsense) -----------------
I [Synth 8-6014] _reg # generic
# unused sequential element ------------------------------------
I [Synth 8-3332] R_LREGS_reg[attn][\d*] # generic
# --> many HIO pins not used # OK 2018-12-28
I [Synth 8-3332] HIO/R_REGS_reg[(btn|swi)(eff)?][\d*]
i [Synth 8-3332] IOB_BTN/R_DI_reg[\d*]
i [Synth 8-3332] DEB.DEB_BTN/R_REGS_reg[(dref|dout|dchange|cecnt)][\d*]
# --> usec not used for serport clock domain # OK 2018-12-28
i [Synth 8-3332] R_REGS_reg[usec]
# --> indeed no types with [3] set # OK 2018-12-28
i [Synth 8-3332] R_REGS_reg[dtyp][3].* ibdr_rhrp
# --> not yet used # OK 2018-12-28
i [Synth 8-3332] R_REGS_reg[req_lock].* ibd_iist
i [Synth 8-3332] R_REGS_reg[req_boot].* ibd_iist
# --> monitor outputs moneop,monattn currently not used # OK 2018-12-28
i [Synth 8-3332] CORE/RL/R_LREGS_reg[moneop]
i [Synth 8-3332] CORE/RL/R_LREGS_reg[monattn]
# --> inst_compl logic disabled in pdp11_mmu # OK 2018-12-28
i [Synth 8-3332] MMU/R_SSR0_reg[inst_compl].* pdp11_vmbox
# --> not yet used # OK 2018-12-28
i [Synth 8-3332] R_STATUS_reg[suspext].* pdp11_sequencer
# --> [8] is for DZ11TX, not yet available # OK 2018-12-28
# --> [9] is for DZ11RX, unclear why this one isn't removed too !!
i [Synth 8-3332] R_STATUS_reg[intvect][8].* pdp11_sequencer
# --> _decode only uses _[oalm]unit -> [2] always '0' in decode # OK 2018-12-28
i [Synth 8-3332] R_IDSTAT_reg[res_sel][2].* pdp11_sequencer
# --> scnt disabled, thus 3 SNUM bits '0' # OK 2018-12-28
i [Synth 8-3332] R_REGS_reg[se_snum][(4|5|6)]
{:}
# INFO: encoded FSM with state register as --------------------
# test for sys_w11a_as7 that all FSMs are one_hot
r [Synth 8-3354] R_BREGS_reg[state.*'one-hot'.*'rlink_core'

28
rtl/sys_gen/w11a/artys7_bram/sys_w11a_br_as7.vmfset
View File

@ -1,4 +1,9 @@
# $Id: sys_w11a_br_as7.vmfset 1091 2018-12-23 12:38:29Z mueller $
# $Id: sys_w11a_br_as7.vmfset 1108 2019-02-02 23:04:38Z mueller $
#
# Validated code/tool version combinations
# Date rev viv
# 2019-02-02 1108 2017.2
# 2019-02-02 1108 2018.3
#
# ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
[syn]
@ -46,12 +51,14 @@ i [Synth 8-3331] pdp11_bram_memctl .* ADDR[1(6|7|8|9)]
# --> ei_ack not used, interrupt request cleared via register # OK 2018-11-23
i [Synth 8-3331] ibdr_deuna .* EI_ACK
i [Synth 8-3331] ibd_iist .* EI_ACK
# --> rl11 doesn't use MSEC # OK 2019-02-02
i [Synth 8-3331] ibdr_rl11 .* CE_MSEC
# sequential element removed (2017.1 nonsense) -----------------
I [Synth 8-6014] _reg # generic
# unused sequential element ------------------------------------
{2017.2:}
{2017.2:2018.2}
I [Synth 8-3332] R_LREGS_reg[attn][\d*] # generic
# --> not yet used # OK 2018-08-11
i [Synth 8-3332] R_STATUS_reg[suspext].* pdp11_sequencer
@ -67,8 +74,6 @@ i [Synth 8-3332] R_STATUS_reg[intvect][8].* pdp11_sequencer
i [Synth 8-3332] R_IDSTAT_reg[res_sel][2].* pdp11_sequencer
# --> dmcmon not configured, snum not used
i [Synth 8-3332] SNUM0.R_VMWAIT_reg.* pdp11_sequencer # OK 2018-08-11
{2017.2:2017.4}
# --> many HIO pins not used # OK 2018-10-13
I [Synth 8-3332] HIO/R_REGS_reg[(btn|swi)(eff)?][\d*]
i [Synth 8-3332] IOB_BTN/R_DI_reg[\d*]
@ -86,21 +91,6 @@ i [Synth 8-3332] CORE/RL/R_LREGS_reg[monattn]
i [Synth 8-3332] R_REGS_reg[psig][2(4|5|6)]
i [Synth 8-3332] PRE[2(4|5|6)].ENA.CNT/R_CNT_reg[\d*]
{2018.1:}
# --> many HIO pins not used # OK 2018-08-11
I [Synth 8-3332] HIO/R_REGS_reg[(btn|swi)(eff)?][\d*]
i [Synth 8-3332] IOB_BTN/R_DI_reg[\d*]
i [Synth 8-3332] DEB.DEB_BTN/R_REGS_reg[(dref|dout|dchange|cecnt)][\d*]
# --> usec not used for serport clock domain # OK 2018-08-11
i [Synth 8-3332] R_REGS_reg[usec].* clkdivce
# --> inst_compl logic disabled in pdp11_mmu # OK 2018-08-11
i [Synth 8-3332] MMU/R_SSR0_reg[inst_compl].* pdp11_core
# --> IB_MREQ.cacc only used in ibd_ibmon, which is disabled # OK 2018-08-11
i [Synth 8-3332] R_REGS_reg[ibcacc].* pdp11_core
# --> monitor outputs moneop,monattn currently not used # OK 2018-08-11
i [Synth 8-3332] CORE/RL/R_LREGS_reg[moneop]
i [Synth 8-3332] CORE/RL/R_LREGS_reg[monattn]
{:}
# INFO: encoded FSM with state register as --------------------

46
rtl/sys_gen/w11a/basys3/sys_w11a_b3.vmfset
View File

@ -1,4 +1,9 @@
# $Id: sys_w11a_b3.vmfset 1097 2018-12-29 11:20:14Z mueller $
# $Id: sys_w11a_b3.vmfset 1108 2019-02-02 23:04:38Z mueller $
#
# Validated code/tool version combinations
# Date rev viv
# 2019-02-02 1108 2017.2
# 2019-02-02 1108 2018.3
#
# ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
[syn]
@ -51,36 +56,7 @@ i [Synth 8-3331] ibd_iist .* EI_ACK
I [Synth 8-6014] _reg # generic
# unused sequential element ------------------------------------
{:2016.4}
I [Synth 8-3332] R_LREGS_reg[attn][\d*] # generic
I [Synth 8-3332] HIO/R_REGS_reg[(btn|swi)(eff)?][\d*] # generic
# --> usec not used for serport clock domain # OK 2016-06-04
i [Synth 8-3332] CLKDIV_CLKS/R_REGS_reg[usec]
# --> inst_compl logic disabled in pdp11_mmu # OK 2016-06-04
i [Synth 8-3332] VMBOX/MMU/R_SSR0_reg[inst_compl]
# --> IB_MREQ.cacc only used in ibd_ibmon, which is disabled # OK 2016-06-05
i [Synth 8-3332] VMBOX/R_REGS_reg[ibcacc]
# --> not yet used # OK 2016-06-04
i [Synth 8-3332] SEQ/R_STATUS_reg[suspext]
# --> mawidth=4, nblock=11, so some cellen unused # OK 2016-06-05
i [Synth 8-3332] BRAM_CTL/R_REGS_reg[cellen][1\d]
# --> indeed no types with [3] set # OK 2016-06-04
i [Synth 8-3332] R_REGS_reg[dtyp][3].*ibdr_rhrp
# --> not yet used # OK 2016-06-04
i [Synth 8-3332] R_REGS_reg[req_lock].*ibd_iist
i [Synth 8-3332] R_REGS_reg[req_boot].*ibd_iist
# --> [8] is for DZ11TX, not yet available # OK 2016-06-04
# --> [9] is for DZ11RX, unclear why this one isn't removed too !!
i [Synth 8-3332] SEQ/R_STATUS_reg[intvect][8]
# --> _decode only uses _[oalm]unit -> [2] always '0' in decode # OK 2016-06-04
i [Synth 8-3332] SEQ/R_IDSTAT_reg[res_sel][2]
# --> monitor outputs moneop,monattn currently not used # OK 2016-06-04
i [Synth 8-3332] RLINK/CORE/RL/R_LREGS_reg[moneop]
i [Synth 8-3332] RLINK/CORE/RL/R_LREGS_reg[monattn]
# --> dmcmon not configured, snum not used # OK 2017-06-06
i [Synth 8-3332] SEQ/SNUM0.R_VMWAIT_reg
{2017.1:}
{2017.2:2018.2}
I [Synth 8-3332] R_LREGS_reg[attn][\d*] # generic
I [Synth 8-3332] R_REGS_reg[(btn|swi)(eff)?][\d*] # generic
# --> usec not used for serport clock domain # OK 2018-12-29
@ -107,19 +83,11 @@ i [Synth 8-3332] SNUM0.R_VMWAIT_reg.* pdp11_sequencer
# --> PERFEXT(0:2) not used # OK 2018-10-13
i [Synth 8-3332] R_REGS_reg[psig][2(4|5|6)]
i [Synth 8-3332] PRE[2(4|5|6)].ENA.CNT/R_CNT_reg[\d*]
{2017.1:2017.4}
# --> inst_compl logic disabled in pdp11_mmu # OK 2017-06-06
i [Synth 8-3332] MMU/R_SSR0_reg[inst_compl].* pdp11_vmbox
# --> IB_MREQ.cacc only used in ibd_ibmon, which is disabled # OK 2017-06-06
i [Synth 8-3332] R_REGS_reg[ibcacc].* pdp11_vmbox
{2018.1:}
# --> inst_compl logic disabled in pdp11_mmu # OK 2018-08-12
i [Synth 8-3332] MMU/R_SSR0_reg[inst_compl].* pdp11_core
# --> IB_MREQ.cacc only used in ibd_ibmon, which is disabled # OK 2018-08-12
i [Synth 8-3332] R_REGS_reg[ibcacc].* pdp11_core
{:}
# INFO: encoded FSM with state register as --------------------

51
rtl/sys_gen/w11a/cmoda7/sys_w11a_c7.vmfset
View File

@ -1,4 +1,9 @@
# $Id: sys_w11a_c7.vmfset 1097 2018-12-29 11:20:14Z mueller $
# $Id: sys_w11a_c7.vmfset 1108 2019-02-02 23:04:38Z mueller $
#
# Validated code/tool version combinations
# Date rev viv
# 2019-02-02 1108 2017.2
# 2019-02-02 1108 2018.3
#
# ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
[syn]
@ -59,36 +64,7 @@ i [Synth 8-3331] ibd_iist .* EI_ACK
I [Synth 8-6014] _reg # generic
# unused sequential element ------------------------------------
{:2016.4}
I [Synth 8-3332] R_LREGS_reg[attn][\d*] # generic
I [Synth 8-3332] HIO/R_REGS_reg[(btn|swi)(eff)?][\d*] # generic
# --> usec not used for serport clock domain # OK 2017-06-24
i [Synth 8-3332] CLKDIV_CLKS/R_REGS_reg[usec]
# --> inst_compl logic disabled in pdp11_mmu # OK 2017-06-24
i [Synth 8-3332] VMBOX/MMU/R_SSR0_reg[inst_compl]
# --> not yet used # OK 2017-06-24
i [Synth 8-3332] SEQ/R_STATUS_reg[suspext]
# --> mawidth=4, nblock=10, so some cellen unused # OK 2017-06-25
i [Synth 8-3332] BRAM_CTL/R_REGS_reg[cellen][1\d]
# --> indeed no types with [3] set # OK 2017-06-24
i [Synth 8-3332] R_REGS_reg[dtyp][3].*ibdr_rhrp
# --> not yet used # OK 2017-06-24
i [Synth 8-3332] R_REGS_reg[req_lock].*ibd_iist
i [Synth 8-3332] R_REGS_reg[req_boot].*ibd_iist
# --> [8] is for DZ11TX, not yet available # OK 2017-06-24
# --> [9] is for DZ11RX, unclear why this one isn't removed too !!
i [Synth 8-3332] SEQ/R_STATUS_reg[intvect][8]
# --> _decode only uses _[oalm]unit -> [2] always '0' in decode # OK 2017-06-24
i [Synth 8-3332] SEQ/R_IDSTAT_reg[res_sel][2]
# --> monitor outputs moneop,monattn currently not used # OK 2017-06-24
i [Synth 8-3332] RLINK/CORE/RL/R_LREGS_reg[moneop]
i [Synth 8-3332] RLINK/CORE/RL/R_LREGS_reg[monattn]
# --> scnt disabled, thus 3 SNUM bits '0' # OK 2017-06-24
i [Synth 8-3332] R_REGS_reg[se_snum][(4|5|6)]
# --> upper 4 DSP_DP unused # OK 2017-06-24
i [Synth 8-3332] R_REGS_reg[dsp_dp][(4|5|6|7)]
{2017.1:}
{2017.2:2018.2}
I [Synth 8-3332] R_LREGS_reg[attn][\d*] # generic
I [Synth 8-3332] R_REGS_reg[(btn|swi)(eff)?][\d*] # generic
# --> not yet used # OK 2017-06-24
@ -110,8 +86,6 @@ i [Synth 8-3332] R_REGS_reg[dsp_dp][(4|5|6|7)]
# --> PERFEXT(0:2) not used # OK 2018-10-13
i [Synth 8-3332] R_REGS_reg[psig][2(4|5|6)]
i [Synth 8-3332] PRE[2(4|5|6)].ENA.CNT/R_CNT_reg[\d*]
{2017.1:2017.4}
# --> usec not used for serport clock domain # OK 2018-12-29
i [Synth 8-3332] R_REGS_reg[usec].* s7_cmt_1ce1ce
# --> monitor outputs moneop,monattn currently not used # OK 2017-06-24
@ -122,17 +96,6 @@ i [Synth 8-3332] MMU/R_SSR0_reg[inst_compl].* pdp11_vmbox
# --> mawidth=4, nblock=11, so some cellen unused # OK 2017-06-25
i [Synth 8-3332] R_REGS_reg[cellen][1\d].* pdp11_bram_memctl
{2018.1:}
# --> usec not used for serport clock domain # OK 2018-08-12
i [Synth 8-3332] R_REGS_reg[usec].* sys_w11a_c7
# --> monitor outputs moneop,monattn currently not used # OK 2018-08-12
i [Synth 8-3332] R_LREGS_reg[moneop].* rlink_core
i [Synth 8-3332] R_LREGS_reg[monattn].* rlink_core
# --> inst_compl logic disabled in pdp11_mmu # OK 2018-08-12
i [Synth 8-3332] MMU/R_SSR0_reg[inst_compl].* pdp11_core
# --> mawidth=4, nblock=11, so some cellen unused # OK 2018-08-12
i [Synth 8-3332] R_REGS_reg[cellen][1\d].* sys_w11a_c7
{:}
# INFO: encoded FSM with state register as --------------------

184
rtl/sys_gen/w11a/nexys2/sys_w11a_n2.imfset
View File

@ -1,40 +1,47 @@
# $Id: sys_w11a_n2.imfset 779 2016-06-26 15:37:16Z mueller $
# $Id: sys_w11a_n2.imfset 1108 2019-02-02 23:04:38Z mueller $
#
# ----------------------------------------------------------------------------
[xst]
INFO:.*Mux is complete : default of case is discarded
INFO:.*You can improve the performance of the multiplier
INFO:Xst:2679 .* The register is replaced by logic.
INFO:Xst:2117 .* was re-encoded using one-hot encoding
INFO:Xst:1767 .* can share the same physical resources
INFO:Xst:3029 .* LUT implementation is currently selected
INFO:Xst:2261 .* FF/Latch .* is equivalent to the following
Node <IBD_MAXI.IBDR_SYS/IIST.I0/R_REGS.req_boot> of sequential type is unconnected
Node <IBD_MAXI.IBDR_SYS/IIST.I0/R_REGS.req_lock> of sequential type is unconnected
Node <CORE/VMBOX/R_REGS.ibcacc> of sequential type is unconnected
Node <HIO/R_REGS.swieff_\d*> of sequential type is unconnected
Node <HIO/R_REGS.btneff_\d*> of sequential type is unconnected
Node <HIO/R_REGS.swi_\d*> of sequential type is unconnected
Node <HIO/R_REGS.btn_\d*> of sequential type is unconnected
Node <MEM_SRAM.SRAM_CTL/R_REGS.addr0> of sequential type is unconnected
Node <RLINK/FX2CNTL/RXFIFO/R_REGR.sizer_\d> of sequential type is unconnected
Node <RLINK/FX2CNTL/RXFIFO/R_REGW.sizew_\d> of sequential type is unconnected
Node <RLINK/FX2CNTL/TXFIFO/R_REGR.sizer_\d> of sequential type is unconnected
Node <RLINK/FX2CNTL/TXFIFO/R_REGW.sizew_\d> of sequential type is unconnected
Node <RLINK/FX2CNTL/R_MONI_S.*> of sequential type is unconnected
Node <RLINK/FX2CNTL/R_MONI_C.*> of sequential type is unconnected
Node <RLINK/CORE/RL/R_LREGS.monattn> of sequential type is unconnected
Node <RLINK/CORE/RL/R_LREGS.moneop> of sequential type is unconnected
Node <RLINK/SERPORT/XONRX/R_REGS.rxovr> of sequential type is unconnected
Unconnected output port 'LOCKED' of component 'dcm_sfs'
Unconnected output port 'RL_MONI' of component 'rlink_base_serport'
Unconnected output port 'RL_SER_MONI' of component 'rlink_base_serport'
Unconnected output port 'ACK_W' of component 'n2_cram_memctl_as'
Unconnected output port 'OFIFO_SIZE' of component 'rlink_base'
Unconnected output port 'RL_MONI' of component 'rlink_sp1c_fx2'
Unconnected output port 'ACK_W' of component 'nx_cram_memctl_as'
Unconnected output port 'DOA' of component 'ram_1swar_1ar_gen'
Unconnected output port 'DOA' of component 'ram_2swsr_rfirst_gen'
Unconnected output port 'DOB' of component 'ram_2swsr_rfirst_gen'
Unconnected output port 'BUSY' of component 'fifo_1c_dram'
Unconnected output port 'SIZE' of component 'fifo_1c_dram'
Unconnected output port 'ESUSP_O' of component 'pdp11_core'
Input <RESET> is never used
Input <CE_MSEC> is never used
Input <DM_STAT_.*> is never used
Input <CP_STAT\..*> is never used
Input <RB_MREQ\..*> is never used
Input <RB_SRES\..*> is never used
Input <IB_MREQ\..*> is never used
Input <SER_MONI\..*> is never used
Input <RLB_MONI\..*> is never used
Input <CP_STAT.cpuwait> is never used
Input <CP_STAT.cmdbusy> is never used
Input <IB_MREQ.cacc> is never used
Input <IB_MREQ.rmw> is never used
Input <IB_MREQ.din<\d*:\d*>> is never used
Input <IB_MREQ.din<\d*>> is never used
Input <IB_MREQ.racc> is never used
Input <IB_MREQ.be0> is never used
Input <IB_MREQ.be1> is never used
Input <IB_MREQ.din> is never used
Input <IB_MREQ.re> is never used
Input <IB_MREQ.we> is never used
Input <IB_MREQ.addr<\d*:\d*>> is never used
Input <CCIN<2:1>> is never used
Input <EI_ACK> is never used
Input <IREG<\d*:\d*>> is never used
@ -42,84 +49,75 @@ Input <MONI.idone> is never used
Input <MONI.trace_prev> is never used
Input <DIN<\d*:\d*>> is never used
Input <I_MEM_WAIT> is never used
Input <RB_MREQ.init> is never used
Input <RB_MREQ.din<\d*:\d*>> is never used
Input <RB_MREQ.aval> is never used
Input <RB_MREQ.re> is never used
Input <CNTL.trap_done> is never used
Input <VADDR<\d*:\d*>> is never used
Input <CE_USEC> is never used
Signal <R_VMSTAT.trap_ysv> is assigned but never used
Signal <R_VMSTAT.trap_mmu> is assigned but never used
Signal <R_VMSTAT.ack> is assigned but never used
Signal <R_IDSTAT.is_res> is assigned but never used
Signal <R_IDSTAT.fork_srcr> is assigned but never used
Signal <R_IDSTAT.fork_op> is assigned but never used
Signal <R_IDSTAT.force_srcsp> is assigned but never used
Signal <R_IDSTAT.do_pref_dec> is assigned but never used
Signal <R_IDSTAT.do_fork_srcr> is assigned but never used
Signal <R_IDSTAT.do_fork_opg> is assigned but never used
Signal <R_IDSTAT.do_fork_op> is assigned but never used
Signal <R_IDSTAT.do_fork_dsta> is assigned but never used
Signal <TXSIZE_FX2> is assigned but never used
Signal <EI_ACK<\d*:\d*>> is assigned but never used
Signal <DM_STAT_VM.ibsres.dout> is assigned but never used
Signal <DM_STAT_VM.ibsres.busy> is assigned but never used
Signal <DM_STAT_VM.ibsres.ack> is assigned but never used
Signal <DM_STAT_VM.ibmreq.we> is assigned but never used
Signal <DM_STAT_VM.ibmreq.rmw> is assigned but never used
Signal <DM_STAT_VM.ibmreq.re> is assigned but never used
Signal <DM_STAT_VM.ibmreq.racc> is assigned but never used
Signal <DM_STAT_VM.ibmreq.din> is assigned but never used
Signal <DM_STAT_VM.ibmreq.cacc> is assigned but never used
Signal <DM_STAT_VM.ibmreq.be1> is assigned but never used
Signal <DM_STAT_VM.ibmreq.be0> is assigned but never used
Signal <DM_STAT_VM.ibmreq.aval> is assigned but never used
Signal <DM_STAT_VM.ibmreq.addr> is assigned but never used
Signal <DM_STAT_DP.psw.tflag> is assigned but never used
Signal <DM_STAT_DP.psw.rset> is assigned but never used
Signal <DM_STAT_DP.psw.pmode> is assigned but never used
Signal <DM_STAT_DP.psw.cc> is assigned but never used
Signal <DM_STAT_DP.pc> is assigned but never used
Signal <DM_STAT_DP.ireg_we> is assigned but never used
Signal <DM_STAT_DP.ireg> is assigned but never used
Signal <DM_STAT_DP.gpr_we> is assigned but never used
Signal <DM_STAT_DP.gpr_mode> is assigned but never used
Signal <DM_STAT_DP.gpr_bytop> is assigned but never used
Signal <DM_STAT_DP.gpr_adst> is assigned but never used
Signal <DM_STAT_DP.dtmp> is assigned but never used
Signal <DM_STAT_DP.dsrc> is assigned but never used
Signal <DM_STAT_DP.dres> is assigned but never used
Signal <DM_STAT_DP.ddst> is assigned but never used
Signal <DM_STAT_CO.cpuhalt> is assigned but never used
Signal <DM_STAT_CO.cpugo> is assigned but never used
Signal <R_VMSTAT\.trap_ysv> is assigned but never used
Signal <R_VMSTAT\.trap_mmu> is assigned but never used
Signal <R_VMSTAT\.ack> is assigned but never used
Signal <R_IDSTAT\.is_res> is assigned but never used
Signal <R_IDSTAT\.fork_srcr> is assigned but never used
Signal <R_IDSTAT\.fork_op> is assigned but never used
Signal <R_IDSTAT\.force_srcsp> is assigned but never used
Signal <R_IDSTAT\.do_pref_dec> is assigned but never used
Signal <R_IDSTAT\.do_fork_srcr> is assigned but never used
Signal <R_IDSTAT\.do_fork_opg> is assigned but never used
Signal <R_IDSTAT\.do_fork_op> is assigned but never used
Signal <R_IDSTAT\.do_fork_dsta> is assigned but never used
Signal <RXFIFO_BUSY> is assigned but never used
Signal <FX2_FLAG_N<3>> is assigned but never used
Signal <RXFIFO_SIZE<2:0>> is assigned but never used
Signal <FX2_TXAFULL> is assigned but never used
Signal <FX2_RXAEMPTY> is assigned but never used
Signal <IIST_MREQ.lock> is assigned but never used
Signal <IIST_MREQ.boot> is assigned but never used
Signal <VM_CNTL_L\..*> is assigned but never used
Signal <FX2_MONI\..*> is assigned but never used
Signal <BTN> is assigned but never used
Signal <R_REGS.crdone> is assigned but never used
Signal <EI_ACK_RL11> is assigned but never used
Signal <EI_ACK_KW11P> is assigned but never used
# DZ11 signals
Signal <EI_ACK_DZ11TX> is assigned but never used
Signal <EI_ACK_DZ11RX> is assigned but never used
Signal <EI_ACK<\d*>> is assigned but never used
Signal <IB_SRES_DZ11\..*> is used but never assigned
Signal <EI_REQ_DZ11TX> is used but never assigned
Signal <EI_REQ_DZ11RX> is used but never assigned
Signal <RB_LAM_DZ11> is used but never assigned
Signal <SIZE<\d*:\d*>> is assigned but never used
Signal <SWI<\d*:\d*>> is assigned but never used
Signal <BTN> is assigned but never used
# IIST signals
Signal <IB_SRES_IIST\..*> is used but never assigned
Signal <EI_REQ_IIST> is used but never assigned
Signal <EI_ACK_IIST> is assigned but never used
FF/Latch <R_REGS.dcf_brk_1> in Unit <ibd_iist> is equivalent
FF/Latch <R_REGS.paddr_iopage_\d*> in Unit <pdp11_vmbox> is equivalent
FF/Latch <R_REGS.rbre> in Unit <rlink_core> is equivalent
FF/Latch <MEM_SRAM.SRAM_CTL/R_REGS.memdi_\d*> in Unit <sys_w11a_n2> is equivalent
FF/Latch <CORE/SEQ/R_IDSTAT.aunit_srcmod_\d*> in Unit <sys_w11a_n2> is equivalent
FF/Latch <CORE/SEQ/R_IDSTAT.fork_dsta_\d*> in Unit <sys_w11a_n2> is equivalent
FF/Latch <IBD_MAXI.IBDR_SYS/IIST.I0/R_REGS.dcf_brk_\d*> in Unit <sys_w11a_n2> is equivalent
FF/Latch <R_REGS.escseen> has a constant value of 0
FF/Latch <R_REGS.escpend> has a constant value of 0
FF/Latch <R_STATUS.suspext> has a constant value of 0
FF/Latch <R_REGS.dtyp_3> has a constant value of 0
FF/Latch <RLINK/FX2CNTL/RXFIFO/R_REGR.rstr> has a constant value of 0
FF/Latch <RLINK/FX2CNTL/TXFIFO/R_REGW.rstw> has a constant value of 0
FF/Latch <RLINK/FX2CNTL/RXFIFO/R_REGR.rstr_sc> has a constant value of 0
FF/Latch <RLINK/FX2CNTL/TXFIFO/R_REGW.rstr_c> has a constant value of 0
FF/Latch <RLINK/FX2CNTL/TXFIFO/R_REGW.rstw_sc> has a constant value of 0
FF/Latch <SYS70/W11A/SEQ/R_IDSTAT.res_sel_2> has a constant value of 0
FF/Latch <SYS70/W11A/SEQ/R_STATUS.intvect_8> has a constant value of 0
FF/Latch <CRAMCTL/IOB_MEM_ADDRH/R_DO_21> has a constant value of 0
FF/Latch <CRAMCTL/IOB_MEM_ADDRH/R_DO_20> has a constant value of 0
FF/Latch <CRAMCTL/R_REGS.cntdly_2> has a constant value of 0
FF/Latch <R_SSR0.inst_compl> has a constant value of 0
FF/Latch <MEM_SRAM.SRAM_CTL/R_REGS.cntdly_\d*> has a constant value of 0
FF/Latch <RLINK/BASE/RL/R_REGS.attn_\d*> has a constant value
FF/Latch <MEM_SRAM.SRAM_CTL/IOB_MEM_ADDRH/R_DO_\d*> has a constant value of 0
FF/Latch <CORE/SEQ/R_STATUS.intvect_8> has a constant value of 0
FF/Latch <CORE/SEQ/R_IDSTAT.res_sel_2> has a constant value of 0
FF/Latch <RLINK/CORE/RL/R_LREGS\.attn_.*> has a constant value of 0
FF/Latch <SYS70/DMPCNT.I0/R_REGS\.psig_\d*> has a constant value of 0
FF/Latch <SYS70/DMPCNT.I0/PRE\[\d*\]\.ENA.CNT/R_CNT_\d*> has a constant value
WARNING:Xst:38 - Value "one_hot" of property "fsm_encoding" not applicable
WARNING:Xst:38 - Value "none" of property "fsm_encoding" not applicable.
WARNING:Xst:1896 - Due to other FF/Latch trimming
WARNING:Xst:790 .*ibus/ib_intmap24.vhd.*does not match array range
#
# ----------------------------------------------------------------------------
@ -131,14 +129,17 @@ INFO:.*TNM.*used in period specification.*was traced into DCM_SP
[map]
The signal <I_MEM_WAIT_IBUF> is incomplete
Logical network I_MEM_WAIT_IBUF has no load
Signal I_FX2_FLAG<3> connected to .* I_FX2_FLAG<3> has been removed
There is a dangling output parity pin
WARNING:Pack:266
WARNING:PhysDesignRules:1060
INFO:.*
#
# ----------------------------------------------------------------------------
[par]
The signal I_MEM_WAIT_IBUF has no load
There are 1 loadless signals in this design
WARNING:Place:1019
#
# ----------------------------------------------------------------------------
[bgn]
@ -146,3 +147,4 @@ Spartan-3 1200E and 1600E devices do not support bitstream
The signal <I_MEM_WAIT_IBUF> is incomplete
There is a dangling output parity pin
INFO:.*To achieve optimal frequency synthesis performance
WARNING:PhysDesignRules:1060

130
rtl/sys_gen/w11a/nexys3/sys_w11a_n3.imfset
View File

@ -1,45 +1,121 @@
# $Id: sys_w11a_n3.imfset 776 2016-06-18 17:22:51Z mueller $
# $Id: sys_w11a_n3.imfset 1108 2019-02-02 23:04:38Z mueller $
#
# ----------------------------------------------------------------------------
[xst]
INFO:.*Case statement is complete. others clause is never selected
INFO:.*The small RAM <.*> will be implemented on LUTs
INFO:Xst:2261 .* FF/Latch .* is equivalent to the following
INFO:HDLCompiler:679 .* Case statement is complete
INFO:Xst:3210 .* unconnected or connected to loadless signal
INFO:Xst:3216 .* LUT implementation is currently selected
INFO:Xst:3218 .* will be implemented on LUTs
INFO:Xst:3212 .* Asynchronous or synchronous initialization
INFO:Xst:3231 .* The small RAM
INFO:Xst:2774 .* IOB property attached
INFO:Xst:1901 .* has been replaced by RAMB16
Value "none" of property "fsm_encoding" is not applicable
Value "one_hot" of property "fsm_encoding" is not applicable
Using initial value '0' for rb_lam_dz11 since it is never assigned
Using initial value .* for ib_sres_dz11 since it is never assigned
Using initial value '0' for ei_req_dz11rx since it is never assigned
Using initial value '0' for ei_req_dz11tx since it is never assigned
ibdr_deuna.vhd.* Assignment to ibrd ignored
ibdr_rhrp.vhd.* Assignment to ibrd ignored
ibdr_rl11.vhd.* Assignment to ibwrem ignored
ibdr_rk11.vhd.* Assignment to ibrd ignored
ibdr_tm11.vhd.* Assignment to ibrd ignored
ibdr_maxisys.vhd.* Assignment to ei_ack_dz11rx ignored
ibdr_maxisys.vhd.* Assignment to ei_ack_dz11tx ignored
Net <IB_SRES_IIST_ack> does not have a driver
Net <EI_REQ_IIST> does not have a driver
Signal 'IB_SRES_IIST_dout', unconnected in block 'ibdr_maxisys'
Signal 'IB_SRES_IIST_ack', unconnected in block 'ibdr_maxisys'
Signal 'IB_SRES_IIST_busy', unconnected in block 'ibdr_maxisys'
Signal 'EI_REQ_IIST', unconnected in block 'ibdr_maxisys'
Input <RB_MREQ_.*> is never used.
Input <RB_SRES_.*> is never used.
Input <CP_STAT_.*> is never used.
Input <IB_MREQ_.*> is never used.
Input <SER_MONI_.*> is never used.
Input <RLB_MONI_.*> is never used.
Node <HIO/R_REGS.btneff_\d*> of sequential type is unconnected
Node <HIO/R_REGS.btn_\d*> of sequential type is unconnected
Node <RLINK/FX2CNTL/RXFIFO/R_REGR.sizer_\d> of sequential type is unconnected
Node <RLINK/FX2CNTL/RXFIFO/R_REGW.sizew_\d> of sequential type is unconnected
Node <RLINK/FX2CNTL/TXFIFO/R_REGR.sizer_\d> of sequential type is unconnected
Node <RLINK/FX2CNTL/TXFIFO/R_REGW.sizew_\d> of sequential type is unconnected
Node <RLINK/FX2CNTL/R_MONI_S.*> of sequential type is unconnected
Node <RLINK/FX2CNTL/R_MONI_C.*> of sequential type is unconnected
Node <RLINK/CORE/RL/R_LREGS.monattn> of sequential type is unconnected
Node <RLINK/CORE/RL/R_LREGS.moneop> of sequential type is unconnected
Node <RLINK/SERPORT/XONRX/R_REGS.rxovr> of sequential type is unconnected
Input <RESET> is never used
Input <CE_MSEC> is never used
Input <DM_STAT_.*> is never used
Input <CCIN<2:1>> is never used
Input <EI_ACK> is never used
Input <IREG<\d*:\d*>> is never used
Input <MONI.idone> is never used
Input <MONI.trace_prev> is never used
Input <DIN<\d*:\d*>> is never used
Input <I_MEM_WAIT> is never used
Input <CNTL.trap_done> is never used
Input <VADDR<\d*:\d*>> is never used
Input <CE_USEC> is never used
FF/Latch <R_STATUS.suspext> has a constant value of 0
FF/Latch <R_REGS.dtyp_3> has a constant value of 0
FF/Latch <SYS70/DMCMON.I0/R_REGS_se_snum.*> has a constant value
FF/Latch <SYS70/DMSCNT.I0/R_REGS_snum.*> has a constant value
FF/Latch <RLINK/CORE/RL/R_LREGS_attn_\d*> has a constant value
FF/Latch <CLKDIV/R_REGS_ucnt_\d*> has a constant value
FF/Latch <RLINK/FX2CNTL/RXFIFO/R_REGR.rstr> has a constant value of 0
FF/Latch <RLINK/FX2CNTL/TXFIFO/R_REGW.rstw> has a constant value of 0
FF/Latch <RLINK/FX2CNTL/RXFIFO/R_REGR.rstr_sc> has a constant value of 0
FF/Latch <RLINK/FX2CNTL/TXFIFO/R_REGW.rstr_c> has a constant value of 0
FF/Latch <RLINK/FX2CNTL/TXFIFO/R_REGW.rstw_sc> has a constant value of 0
FF/Latch <SYS70/W11A/SEQ/R_IDSTAT.res_sel_2> has a constant value of 0
FF/Latch <SYS70/W11A/SEQ/R_STATUS.intvect_8> has a constant value of 0
FF/Latch <CRAMCTL/IOB_MEM_ADDRH/R_DO_21> has a constant value of 0
FF/Latch <CRAMCTL/IOB_MEM_ADDRH/R_DO_20> has a constant value of 0
The FF/Latch <SYS70/DMCMON.I0/R_REGS_cnum_\d> .* is the opposite
The FF/Latch <HIO/HIO/DRV/R_REGS_cdiv_0> .* is the opposite
The FF/Latch <RLINK/FX2CNTL/IOB_FX2_SLRD/IOB/R_DO_0> .* is the opposite
WARNING:Xst:1896 - Due to other FF/Latch trimming
Output port <LOCKED> of the instance <GEN_CLKSYS> is unconnected
Output port <FX2_MONI_.*> of the instance <RLINK> is unconnected
Output port <BTN> of the instance <HIO> is unconnected
Output port <RL_MONI_.*> of the instance <RLINK> is unconnected
#
Input <CP_STAT_.*> is never used
Input <MONI_.*> is never used
Input <SER_MONI_.*> is never used
Input <IB_MREQ_.*> is never used
Input <RB_MREQ_.*> is never used
Input <RB_SRES_.*> is never used
Input <DM_STAT_(DP|VM|CO|SE)_.*> is never used
#
INFO:.*Instance.*has been replaced by RAMB16BWER
#
# ----------------------------------------------------------------------------
[tra]
INFO:.*TNM 'I_CLK100'.*was traced into DCM_SP
INFO:.*Setting CLKIN_PERIOD attribute associated with DCM instance
INFO:.*TNM.*used in period specification.*was traced into DCM_SP
INFO:NgdBuild:1222
#
# ----------------------------------------------------------------------------
[map]
WARNING:.*has the attribute CLK_FEEDBACK set to NONE
WARNING:.*The signal <I_MEM_WAIT_IBUF> is incomplete
WARNING:.*to use input parity pin.*dangling output for parity pin
Logical network I_MEM_WAIT_IBUF has no load
Signal I_FX2_FLAG<3> connected to .* I_FX2_FLAG<3> has been removed
WARNING:PhysDesignRules:1176
WARNING:Timing:3402 .* No phase relationship
INFO:.*
#
# ----------------------------------------------------------------------------
[par]
WARNING:.*has the attribute CLK_FEEDBACK set to NONE
WARNING:.*The signal I_MEM_WAIT_IBUF has no load
WARNING:.*There are 1 loadless signals in this design
There are 1 loadless signals in this design
WARNING:Timing:3402 .* No phase relationship
The signal I_MEM_WAIT_IBUF has no load
#
# ----------------------------------------------------------------------------
[bgn]
WARNING:.*The signal <I_MEM_WAIT_IBUF> is incomplete
WARNING:.*to use input parity pin.*dangling output for parity pin
INFO:.*To achieve optimal frequency synthesis performance
WARNING:PhysDesignRules:1176

48
rtl/sys_gen/w11a/nexys4/sys_w11a_n4.vmfset
View File

@ -1,4 +1,9 @@
# $Id: sys_w11a_n4.vmfset 1097 2018-12-29 11:20:14Z mueller $
# $Id: sys_w11a_n4.vmfset 1108 2019-02-02 23:04:38Z mueller $
#
# Validated code/tool version combinations
# Date rev viv
# 2019-02-02 1108 2017.2
# 2019-02-02 1108 2018.3
#
# ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
[syn]
@ -53,35 +58,7 @@ i [Synth 8-3331] nx_cram_memctl_as .* I_MEM_WAIT
I [Synth 8-6014] _reg # generic
# unused sequential element ------------------------------------
{:2016.4}
I [Synth 8-3332] R_LREGS_reg[attn][\d*] # generic
I [Synth 8-3332] HIO/R_REGS_reg[(btn|swi)(eff)?][\d*] # generic
# --> only 4 MB out of 16 MB used # OK 2016-05-28
i [Synth 8-3332] IOB_MEM_ADDRH/R_DO_reg[20]
i [Synth 8-3332] IOB_MEM_ADDRH/R_DO_reg[21]
# --> usec not used for serport clock domain # OK 2016-05-28
i [Synth 8-3332] CLKDIV_CLKS/R_REGS_reg[usec]
# --> inst_compl logic disabled in pdp11_mmu # OK 2016-05-28
i [Synth 8-3332] VMBOX/MMU/R_SSR0_reg[inst_compl]
# --> not yet used # OK 2016-05-28
i [Synth 8-3332] SEQ/R_STATUS_reg[suspext]
# --> indeed no types with [3] set # OK 2016-05-28
i [Synth 8-3332] R_REGS_reg[dtyp][3].*ibdr_rhrp
# --> not yet used # OK 2016-05-28
i [Synth 8-3332] R_REGS_reg[req_lock].*ibd_iist
i [Synth 8-3332] R_REGS_reg[req_boot].*ibd_iist
# --> [8] is for DZ11TX, not yet available # OK 2016-05-28
# --> [9] is for DZ11RX, unclear why this one isn't removed too !!
i [Synth 8-3332] SEQ/R_STATUS_reg[intvect][8]
# --> _decode only uses _[oalm]unit -> [2] always '0' in decode # OK 2016-05-28
i [Synth 8-3332] SEQ/R_IDSTAT_reg[res_sel][2]
# --> monitor outputs moneop,monattn currently not used # OK 2016-05-28
i [Synth 8-3332] RLINK/CORE/RL/R_LREGS_reg[moneop]
i [Synth 8-3332] RLINK/CORE/RL/R_LREGS_reg[monattn]
# --> scnt disabled, thus 3 SNUM bits '0' # OK 2017-04-22
i [Synth 8-3332] R_REGS_reg[se_snum][(4|5|6)]
{2017.1:}
{2017.2:2018.2}
I [Synth 8-3332] R_LREGS_reg[attn][\d*] # generic
I [Synth 8-3332] R_REGS_reg[(btn|swi)(eff)?][\d*] # generic
# --> only 4 MB out of 16 MB used # OK 2017-06-06
@ -104,8 +81,6 @@ i [Synth 8-3332] R_REGS_reg[se_snum][(4|5|6)]
# --> PERFEXT(0:2) not used # OK 2018-10-13
i [Synth 8-3332] R_REGS_reg[psig][2(4|5|6)]
i [Synth 8-3332] PRE[2(4|5|6)].ENA.CNT/R_CNT_reg[\d*]
{2017.1:2017.4}
# --> usec not used for serport clock domain # OK 2018-12-29
i [Synth 8-3332] R_REGS_reg[usec].* s7_cmt_1ce1ce
# --> inst_compl logic disabled in pdp11_mmu # OK 2017-06-06
@ -114,15 +89,6 @@ i [Synth 8-3332] MMU/R_SSR0_reg[inst_compl].* pdp11_vmbox
i [Synth 8-3332] CORE/RL/R_LREGS_reg[moneop].* rlink_sp2c
i [Synth 8-3332] CORE/RL/R_LREGS_reg[monattn].* rlink_sp2c
{2018.1:}
# --> usec not used for serport clock domain # OK 2018-08-12
i [Synth 8-3332] R_REGS_reg[usec].* sys_w11a_n4
# --> inst_compl logic disabled in pdp11_mmu # OK 2018-08-12
i [Synth 8-3332] MMU/R_SSR0_reg[inst_compl].* pdp11_core
# --> monitor outputs moneop,monattn currently not used # OK 2018-08-12
i [Synth 8-3332] R_LREGS_reg[moneop].* rlink_core
i [Synth 8-3332] R_LREGS_reg[monattn].* rlink_core
{:}
# INFO: encoded FSM with state register as --------------------

9
rtl/sys_gen/w11a/nexys4d/sys_w11a_n4d.vmfset
View File

@ -1,4 +1,9 @@
# $Id: sys_w11a_n4d.vmfset 1101 2019-01-02 21:22:37Z mueller $
# $Id: sys_w11a_n4d.vmfset 1108 2019-02-02 23:04:38Z mueller $
#
# Validated code/tool version combinations
# Date rev viv
# 2019-02-02 1108 2017.2
# 2019-02-02 1108 2018.3
#
# ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
[syn]
@ -53,7 +58,7 @@ i [Synth 8-3331] sramif2migui_core .*APP_RD_DATA_END
I [Synth 8-6014] _reg # generic
# unused sequential element ------------------------------------
{:}
{2017.2:2018.2}
I [Synth 8-3332] R_LREGS_reg[attn][\d*] # generic
I [Synth 8-3332] R_REGS_reg[(btn|swi)(eff)?][\d*] # generic
# --> not yet used # OK 2019-01-02

144
rtl/sys_gen/w11a/s3board/sys_w11a_s3.imfset
View File

@ -1,30 +1,37 @@
# $Id: sys_w11a_s3.imfset 769 2016-05-28 11:36:22Z mueller $
# $Id: sys_w11a_s3.imfset 1108 2019-02-02 23:04:38Z mueller $
#
# ----------------------------------------------------------------------------
[xst]
INFO:.*Mux is complete : default of case is discarded
INFO:Xst:2117 .* was re-encoded using one-hot encoding
INFO:Xst:1767 .* can share the same physical resources
INFO:Xst:2261 .* FF/Latch .* is equivalent to the following
INFO:Xst:1901 .* Instance .* of type .* has been replaced by RAMB16
Node <IBD_MAXI.IBDR_SYS/IIST.I0/R_REGS.req_boot> of sequential type is unconnected
Node <IBD_MAXI.IBDR_SYS/IIST.I0/R_REGS.req_lock> of sequential type is unconnected
Node <CORE/VMBOX/R_REGS.ibcacc> of sequential type is unconnected
Node <HIO/R_REGS.btneff_\d*> of sequential type is unconnected
Node <HIO/R_REGS.btn_\d*> of sequential type is unconnected
Node <RLINK/CORE/RL/R_LREGS.monattn> of sequential type is unconnected
Node <RLINK/CORE/RL/R_LREGS.moneop> of sequential type is unconnected
Node <RLINK/SERPORT/XONRX/R_REGS.rxovr> of sequential type is unconnected
Node <HIO/R_REGS.swieff_\d> of sequential type is unconnected
Node <HIO/R_REGS.swi_\d> of sequential type is unconnected
Unconnected output port 'DOA' of component 'ram_1swar_1ar_gen'
Unconnected output port 'DOA' of component 'ram_2swsr_rfirst_gen'
Unconnected output port 'DOB' of component 'ram_2swsr_rfirst_gen'
Unconnected output port 'BUSY' of component 'fifo_1c_dram'
Unconnected output port 'SIZE' of component 'fifo_1c_dram'
Unconnected output port 'ESUSP_O' of component 'pdp11_core'
Unconnected output port 'RL_MONI' of component 'rlink_sp1c'
Unconnected output port 'ACK_W' of component 's3_sram_memctl'
Input <CP_STAT.cpuwait> is never used
Input <CP_STAT.cmdbusy> is never used
Input <IB_MREQ.cacc> is never used
Input <IB_MREQ.rmw> is never used
Input <IB_MREQ.din<\d*:\d*>> is never used
Input <IB_MREQ.din<\d*>> is never used
Input <IB_MREQ.racc> is never used
Input <IB_MREQ.be0> is never used
Input <IB_MREQ.be1> is never used
Input <IB_MREQ.din> is never used
Input <IB_MREQ.re> is never used
Input <IB_MREQ.we> is never used
Input <IB_MREQ.addr<\d*:\d*>> is never used
Input <CE_MSEC> is never used
Input <DM_STAT_.*> is never used
Input <CP_STAT\..*> is never used
Input <RB_MREQ\..*> is never used
Input <IB_MREQ\..*> is never used
Input <SER_MONI\..*> is never used
Input <CCIN<2:1>> is never used
Input <EI_ACK> is never used
Input <IREG<\d*:\d*>> is never used
@ -33,72 +40,60 @@ Input <MONI.trace_prev> is never used
Input <DIN<\d*:\d*>> is never used
Input <CNTL.trap_done> is never used
Input <VADDR<\d*:\d*>> is never used
Input <CE_USEC> is never used
Signal <R_VMSTAT.trap_ysv> is assigned but never used
Signal <R_VMSTAT.trap_mmu> is assigned but never used
Signal <R_VMSTAT.ack> is assigned but never used
Signal <R_IDSTAT.is_res> is assigned but never used
Signal <R_IDSTAT.fork_srcr> is assigned but never used
Signal <R_IDSTAT.fork_op> is assigned but never used
Signal <R_IDSTAT.force_srcsp> is assigned but never used
Signal <R_IDSTAT.do_pref_dec> is assigned but never used
Signal <R_IDSTAT.do_fork_srcr> is assigned but never used
Signal <R_IDSTAT.do_fork_opg> is assigned but never used
Signal <R_IDSTAT.do_fork_op> is assigned but never used
Signal <R_IDSTAT.do_fork_dsta> is assigned but never used
Signal <RXFIFO_SIZE<2:0>> is assigned but never used
Signal <SWI<7:6>> is assigned but never used
Signal <SWI<2>> is assigned but never used
Signal <MEM_ADDR<19:18>> is assigned but never used
Signal <DM_STAT_VM.ibsres.dout> is assigned but never used
Signal <DM_STAT_VM.ibsres.busy> is assigned but never used
Signal <DM_STAT_VM.ibsres.ack> is assigned but never used
Signal <DM_STAT_VM.ibmreq.we> is assigned but never used
Signal <DM_STAT_VM.ibmreq.rmw> is assigned but never used
Signal <DM_STAT_VM.ibmreq.re> is assigned but never used
Signal <DM_STAT_VM.ibmreq.racc> is assigned but never used
Signal <DM_STAT_VM.ibmreq.din> is assigned but never used
Signal <DM_STAT_VM.ibmreq.cacc> is assigned but never used
Signal <DM_STAT_VM.ibmreq.be1> is assigned but never used
Signal <DM_STAT_VM.ibmreq.be0> is assigned but never used
Signal <DM_STAT_VM.ibmreq.aval> is assigned but never used
Signal <DM_STAT_VM.ibmreq.addr> is assigned but never used
Signal <DM_STAT_DP.psw.tflag> is assigned but never used
Signal <DM_STAT_DP.psw.rset> is assigned but never used
Signal <DM_STAT_DP.psw.pmode> is assigned but never used
Signal <DM_STAT_DP.psw.cc> is assigned but never used
Signal <DM_STAT_DP.pc> is assigned but never used
Signal <DM_STAT_DP.ireg_we> is assigned but never used
Signal <DM_STAT_DP.ireg> is assigned but never used
Signal <DM_STAT_DP.gpr_we> is assigned but never used
Signal <DM_STAT_DP.gpr_mode> is assigned but never used
Signal <DM_STAT_DP.gpr_bytop> is assigned but never used
Signal <DM_STAT_DP.gpr_adst> is assigned but never used
Signal <DM_STAT_DP.dtmp> is assigned but never used
Signal <DM_STAT_DP.dsrc> is assigned but never used
Signal <DM_STAT_DP.dres> is assigned but never used
Signal <DM_STAT_DP.ddst> is assigned but never used
Signal <DM_STAT_CO.cpuhalt> is assigned but never used
Signal <DM_STAT_CO.cpugo> is assigned but never used
Signal <EI_ACK<\d*:\d*>> is assigned but never used
Signal <IIST_MREQ.lock> is assigned but never used
Signal <IIST_MREQ.boot> is assigned but never used
Signal <R_VMSTAT\.trap_ysv> is assigned but never used
Signal <R_VMSTAT\.trap_mmu> is assigned but never used
Signal <R_VMSTAT\.ack> is assigned but never used
Signal <R_IDSTAT\.is_res> is assigned but never used
Signal <R_IDSTAT\.fork_srcr> is assigned but never used
Signal <R_IDSTAT\.fork_op> is assigned but never used
Signal <R_IDSTAT\.force_srcsp> is assigned but never used
Signal <R_IDSTAT\.do_pref_dec> is assigned but never used
Signal <R_IDSTAT\.do_fork_srcr> is assigned but never used
Signal <R_IDSTAT\.do_fork_opg> is assigned but never used
Signal <R_IDSTAT\.do_fork_op> is assigned but never used
Signal <R_IDSTAT\.do_fork_dsta> is assigned but never used
Signal <EI_ACK_RL11> is assigned but never used
Signal <EI_ACK_KW11P> is assigned but never used
Signal <VM_CNTL_L\..*> is assigned but never used
Signal <BTN> is assigned but never used
Signal <R_REGS.crdone> is assigned but never used
# DZ11 signals
Signal <EI_ACK_DZ11TX> is assigned but never used
Signal <EI_ACK_DZ11RX> is assigned but never used
Signal <EI_ACK<\d*>> is assigned but never used
Signal <IB_SRES_DZ11\..*> is used but never assigned
Signal <EI_REQ_DZ11TX> is used but never assigned
Signal <EI_REQ_DZ11RX> is used but never assigned
Signal <RB_LAM_DZ11> is used but never assigned
Signal <MEM_ADDR<\d*:\d*>> is assigned but never used
# IIST signals
Signal <IB_SRES_IIST\..*> is used but never assigned
Signal <EI_REQ_IIST> is used but never assigned
Signal <EI_ACK_IIST> is assigned but never used
FF/Latch <R_REGS.dcf_brk_1> in Unit <ibd_iist> is equivalent
FF/Latch <R_REGS.paddr_iopage_\d*> in Unit <pdp11_vmbox> is equivalent
FF/Latch <R_REGS.rbre> in Unit <rlink_core> is equivalent
FF/Latch <CORE/SEQ/R_IDSTAT.fork_dsta_\d*> in Unit <sys_w11a_s3> is equivalent
FF/Latch <CORE/SEQ/R_IDSTAT.aunit_srcmod_\d*> in Unit <sys_w11a_s3> is equivalent
FF/Latch <IBD_MAXI.IBDR_SYS/IIST.I0/R_REGS.dcf_brk_\d*> in Unit <sys_w11a_s3> is equivalent
FF/Latch <R_REGS.escseen> has a constant value of 0
FF/Latch <R_REGS.escpend> has a constant value of 0
FF/Latch <R_STATUS.suspext> has a constant value of 0
FF/Latch <R_REGS.dtyp_3> has a constant value of 0
FF/Latch <SYS70/W11A/SEQ/R_IDSTAT.res_sel_2> has a constant value of 0
FF/Latch <SYS70/W11A/SEQ/R_STATUS.intvect_8> has a constant value of 0
FF/Latch <R_SSR0.inst_compl> has a constant value of 0
FF/Latch <CORE/SEQ/R_STATUS.intvect_8> has a constant value of 0
FF/Latch <CORE/SEQ/R_IDSTAT.res_sel_2> has a constant value of 0
FF/Latch <RLINK/CORE/RL/R_LREGS\.attn_.*> has a constant value of 0
FF/Latch <SYS70/DMPCNT.I0/R_REGS\.psig_\d*> has a constant value of 0
FF/Latch <SYS70/DMPCNT.I0/PRE\[\d*\]\.ENA.CNT/R_CNT_\d*> has a constant value
WARNING:Xst:38 - Value "one_hot" of property "fsm_encoding" not applicable
WARNING:Xst:790 .*ibus/ib_intmap24.vhd.*does not match array range
#
# ----------------------------------------------------------------------------
@ -107,7 +102,7 @@ FF/Latch <CORE/SEQ/R_IDSTAT.res_sel_2> has a constant value of 0
#
# ----------------------------------------------------------------------------
[map]
There is a dangling output parity pin
WARNING:Pack:266
INFO:.*
#
@ -117,4 +112,3 @@ INFO:.*
#
# ----------------------------------------------------------------------------
[bgn]
There is a dangling output parity pin