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Code Issues Releases Wiki Activity

remove ISE build support for 7Series designs

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This commit is contained in:
wfjm
2018-12-01 13:07:59 +01:00
parent 86556f767f
commit a3bf3519d9
35 changed files with 40 additions and 345 deletions
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6
doc/CHANGELOG.md
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@@ -36,6 +36,11 @@ The full set of tests is only run for tagged releases.
2.10BSD kernel profiling code to 2.11BSD.
- stay with vivado 2017.2 as default tool, 2017.2 to 2018.2 exhibit much
longer build times for w11 designs (see [w11 blog posting](https://wfjm.github.io/blogs/w11/2018-09-01-vivado-2018.2-much-slower.html))
- the first Artix-7 designs for the nexys4 board where done in 2013 with
ISE 14.5, later with 14.7, simply because the early Vivado versions were
nice technology demonstrators, but didn't compile the w11 code base. That
changed with Vivado 2014.3, and since 2015 ISE wasn't used for 7Series. So
it's time to remove the ISE build support for the nexys4 designs.
### New features
- travis support via `.travis.yml`
@@ -52,6 +57,7 @@ The full set of tests is only run for tagged releases.
- generates create_disk compatible test patterns
### Changes
- remove ISE 14.x build support for 7Series (mostly nexys4 designs)
- Makefile: `make all_tcl` now quiet, use setup_packages_filt
- sys_w11_n4: reduce cache from 64 to 32 kB to keep timing closure
- changes for DM_STAT_* signals (debug and monitoring)

40
rtl/bplib/nexys4/tb/Makefile.ise
View File

@@ -1,40 +0,0 @@
# -*- makefile-gmake -*-
# $Id: Makefile.ise 733 2016-02-20 12:24:13Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2015-02-06 643 1.2 add nexys4_cram_aif
# 2015-02-01 641 1.1 drop nexys4_fusp_aif
# 2014-07-27 545 1.0.1 make reference board configurable via XTW_BOARD
# 2013-09-21 534 1.0 Initial version
#
EXE_all = tb_nexys4_dummy tb_nexys4_cram_dummy
#
ifndef XTW_BOARD
XTW_BOARD=nexys4
endif
include ${RETROBASE}/rtl/make_ise/xflow_default_$(XTW_BOARD).mk
#
.PHONY : all all_ssim all_tsim clean
#
all : $(EXE_all)
all_ssim : $(EXE_all:=_ssim)
all_tsim : $(EXE_all:=_tsim)
#
clean : ise_clean ghdl_clean isim_clean
#
#-----
#
include ${RETROBASE}/rtl/make_ise/generic_ghdl.mk
include ${RETROBASE}/rtl/make_ise/generic_isim.mk
include ${RETROBASE}/rtl/make_ise/generic_xflow.mk
#
VBOM_all = $(wildcard *.vbom)
#
ifndef DONTINCDEP
include $(VBOM_all:.vbom=.dep_xst)
include $(VBOM_all:.vbom=.dep_ghdl)
include $(VBOM_all:.vbom=.dep_isim)
include $(wildcard *.o.dep_ghdl)
endif
#

13
rtl/bplib/nexys4/tb/nexys4_cram_dummy.ucf_cpp
View File

@@ -1,13 +0,0 @@
## $Id: nexys4_cram_dummy.ucf_cpp 643 2015-02-07 17:41:53Z mueller $
##
## Revision History:
## Date Rev Version Comment
## 2015-02-06 463 1.1 factor out memory
## 2013-09-21 534 1.0 Initial version
##
## std board
##
#include "bplib/nexys4/nexys4_pins.ucf"
#include "bplib/nexys4/nexys4_pins_cram.ucf"
##

1
rtl/bplib/nexys4/tb/nexys4_cram_dummy.vbom
View File

@@ -5,4 +5,3 @@
../../nxcramlib/nx_cram_dummy.vbom
# design
nexys4_cram_dummy.vhd
@ucf_cpp: nexys4_cram_dummy.ucf

11
rtl/bplib/nexys4/tb/nexys4_dummy.ucf_cpp
View File

@@ -1,11 +0,0 @@
## $Id: nexys4_dummy.ucf_cpp 534 2013-09-22 21:37:24Z mueller $
##
## Revision History:
## Date Rev Version Comment
## 2013-09-21 534 1.0 Initial version
##
## std board
##
#include "bplib/nexys4/nexys4_pins.ucf"
##

1
rtl/bplib/nexys4/tb/nexys4_dummy.vbom
View File

@@ -2,4 +2,3 @@
../../../vlib/slvtypes.vhd
# design
nexys4_dummy.vhd
@ucf_cpp: nexys4_dummy.ucf

4
rtl/sys_gen/tst_rlink/arty/sys_tst_rlink_arty.vbom
View File

@@ -11,8 +11,8 @@
../../../bplib/sysmon/sysmonrbuslib.vbom
${sys_conf := sys_conf.vhd}
# components
[xst,vsyn]../../../vlib/xlib/s7_cmt_sfs_unisim.vbom
[ghdl,isim,vsim]../../../vlib/xlib/s7_cmt_sfs_gsim.vbom
[vsyn]../../../vlib/xlib/s7_cmt_sfs_unisim.vbom
[ghdl,vsim]../../../vlib/xlib/s7_cmt_sfs_gsim.vbom
../../../vlib/genlib/clkdivce.vbom
../../../bplib/bpgen/bp_rs232_2line_iob.vbom
../../../bplib/bpgen/bp_swibtnled.vbom

4
rtl/sys_gen/tst_rlink/basys3/sys_tst_rlink_b3.vbom
View File

@@ -11,8 +11,8 @@
../../../bplib/sysmon/sysmonrbuslib.vbom
${sys_conf := sys_conf.vhd}
# components
[xst,vsyn]../../../vlib/xlib/s7_cmt_sfs_unisim.vbom
[ghdl,isim,vsim]../../../vlib/xlib/s7_cmt_sfs_gsim.vbom
[vsyn]../../../vlib/xlib/s7_cmt_sfs_unisim.vbom
[ghdl,vsim]../../../vlib/xlib/s7_cmt_sfs_gsim.vbom
../../../vlib/genlib/clkdivce.vbom
../../../bplib/bpgen/bp_rs232_2line_iob.vbom
../../../bplib/bpgen/sn_humanio_rbus.vbom

4
rtl/sys_gen/tst_rlink/cmoda7/sys_tst_rlink_c7.vbom
View File

@@ -11,8 +11,8 @@
../../../bplib/sysmon/sysmonrbuslib.vbom
${sys_conf := sys_conf.vhd}
# components
[xst,vsyn]../../../vlib/xlib/s7_cmt_sfs_unisim.vbom
[ghdl,isim,vsim]../../../vlib/xlib/s7_cmt_sfs_gsim.vbom
[vsyn]../../../vlib/xlib/s7_cmt_sfs_unisim.vbom
[ghdl,vsim]../../../vlib/xlib/s7_cmt_sfs_gsim.vbom
../../../vlib/genlib/clkdivce.vbom
../../../bplib/bpgen/bp_rs232_2line_iob.vbom
../../../vlib/rlink/rlink_sp1c.vbom

29
rtl/sys_gen/tst_rlink/nexys4/Makefile.ise
View File

@@ -1,29 +0,0 @@
# -*- makefile-gmake -*-
# $Id: Makefile.ise 733 2016-02-20 12:24:13Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2013-09-28 535 1.0 Initial version
#
VBOM_all = $(wildcard *.vbom)
BIT_all = $(VBOM_all:.vbom=.bit)
#
include ${RETROBASE}/rtl/make_ise/xflow_default_nexys4.mk
#
.PHONY : all clean
#
all : $(BIT_all)
#
clean : ise_clean
rm -f $(VBOM_all:.vbom=.ucf)
#
#----
#
include ${RETROBASE}/rtl/make_ise/generic_xflow.mk
include ${RETROBASE}/rtl/make_ise/generic_ghdl.mk
#
ifndef DONTINCDEP
include $(VBOM_all:.vbom=.dep_xst)
include $(VBOM_all:.vbom=.dep_ghdl)
endif
#

17
rtl/sys_gen/tst_rlink/nexys4/sys_tst_rlink_n4.ucf_cpp
View File

@@ -1,17 +0,0 @@
## $Id: sys_tst_rlink_n4.ucf_cpp 640 2015-02-01 09:56:53Z mueller $
##
## Revision History:
## Date Rev Version Comment
## 2015-01-25 639 1.1 drop fusp iface
## 2013-09-28 535 1.0 Initial version
##
NET "I_CLK100" TNM_NET = "I_CLK100";
TIMESPEC "TS_I_CLK100" = PERIOD "I_CLK100" 10.0 ns HIGH 50 %;
OFFSET = IN 10 ns BEFORE "I_CLK100";
OFFSET = OUT 20 ns AFTER "I_CLK100";
## std board
##
#include "bplib/nexys4/nexys4_pins.ucf"
##

5
rtl/sys_gen/tst_rlink/nexys4/sys_tst_rlink_n4.vbom
View File

@@ -11,8 +11,8 @@
../../../bplib/sysmon/sysmonrbuslib.vbom
${sys_conf := sys_conf.vhd}
# components
[xst,vsyn]../../../vlib/xlib/s7_cmt_sfs_unisim.vbom
[ghdl,isim,vsim]../../../vlib/xlib/s7_cmt_sfs_gsim.vbom
[vsyn]../../../vlib/xlib/s7_cmt_sfs_unisim.vbom
[ghdl,vsim]../../../vlib/xlib/s7_cmt_sfs_gsim.vbom
../../../vlib/genlib/clkdivce.vbom
../../../bplib/bpgen/bp_rs232_4line_iob.vbom
../../../bplib/bpgen/sn_humanio_rbus.vbom
@@ -26,6 +26,5 @@ ${sys_conf := sys_conf.vhd}
../../../vlib/rbus/rb_sres_or_6.vbom
# design
sys_tst_rlink_n4.vhd
@ucf_cpp: sys_tst_rlink_n4.ucf
@xdc:../../../bplib/nexys4/nexys4_pclk.xdc
@xdc:../../../bplib/nexys4/nexys4_pins.xdc

4
rtl/sys_gen/tst_rlink/nexys4/sys_tst_rlink_n4.vhd
View File

@@ -1,4 +1,4 @@
-- $Id: sys_tst_rlink_n4.vhd 984 2018-01-02 20:56:27Z mueller $
-- $Id: sys_tst_rlink_n4.vhd 1073 2018-11-23 18:05:51Z mueller $
--
-- Copyright 2013-2016 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@@ -31,7 +31,7 @@
-- Test bench: tb/tb_tst_rlink_n4
--
-- Target Devices: generic
-- Tool versions: ise 14.5-14.7; viv 2014.4-2015.4; ghdl 0.29-0.33
-- Tool versions: viv 2014.4-2017.2; ghdl 0.29-0.34 (ise 14.5-14.7 retired)
--
-- Synthesized:
-- Date Rev viv Target flop lutl lutm bram slic

33
rtl/sys_gen/tst_rlink/nexys4/tb/Makefile.ise
View File

@@ -1,33 +0,0 @@
# -*- makefile-gmake -*-
# $Id: Makefile.ise 733 2016-02-20 12:24:13Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2013-09-28 535 1.0 Initial version
#
EXE_all = tb_tst_rlink_n4
#
include ${RETROBASE}/rtl/make_ise/xflow_default_nexys4.mk
#
.PHONY : all all_ssim all_tsim clean
#
all : $(EXE_all)
all_ssim : $(EXE_all:=_ssim)
all_tsim : $(EXE_all:=_tsim)
#
clean : ise_clean ghdl_clean
rm -f sys_tst_rlink_n4.ucf
#
#-----
#
include ${RETROBASE}/rtl/make_ise/generic_ghdl.mk
include ${RETROBASE}/rtl/make_ise/generic_xflow.mk
#
VBOM_all = $(wildcard *.vbom)
#
ifndef DONTINCDEP
include $(VBOM_all:.vbom=.dep_xst)
include $(VBOM_all:.vbom=.dep_ghdl)
include $(wildcard *.o.dep_ghdl)
endif
#

1
rtl/sys_gen/tst_rlink/nexys4/tb/sys_tst_rlink_n4.ucf_cpp
View File

@@ -1 +0,0 @@
../sys_tst_rlink_n4.ucf_cpp

4
rtl/sys_gen/tst_rlink/nexys4d/sys_tst_rlink_n4d.vbom
View File

@@ -11,8 +11,8 @@
../../../bplib/sysmon/sysmonrbuslib.vbom
${sys_conf := sys_conf.vhd}
# components
[xst,vsyn]../../../vlib/xlib/s7_cmt_sfs_unisim.vbom
[ghdl,isim,vsim]../../../vlib/xlib/s7_cmt_sfs_gsim.vbom
[vsyn]../../../vlib/xlib/s7_cmt_sfs_unisim.vbom
[ghdl,vsim]../../../vlib/xlib/s7_cmt_sfs_gsim.vbom
../../../vlib/genlib/clkdivce.vbom
../../../bplib/bpgen/bp_rs232_4line_iob.vbom
../../../bplib/bpgen/sn_humanio_rbus.vbom

4
rtl/sys_gen/tst_rlink/nexys4d/sys_tst_rlink_n4d.vhd
View File

@@ -1,4 +1,4 @@
-- $Id: sys_tst_rlink_n4d.vhd 984 2018-01-02 20:56:27Z mueller $
-- $Id: sys_tst_rlink_n4d.vhd 1073 2018-11-23 18:05:51Z mueller $
--
-- Copyright 2017- by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@@ -31,7 +31,7 @@
-- Test bench: tb/tb_tst_rlink_n4d
--
-- Target Devices: generic
-- Tool versions: ise 14.5-14.7; viv 2014.4-2015.4; ghdl 0.29-0.33
-- Tool versions: viv 2014.4-2015.4; ghdl 0.29-0.33
--
-- Synthesized:
-- Date Rev viv Target flop lutl lutm bram slic

4
rtl/sys_gen/tst_sram/cmoda7/sys_tst_sram_c7.vbom
View File

@@ -12,8 +12,8 @@
../../../bplib/cmoda7/cmoda7lib.vhd
${sys_conf := sys_conf.vhd}
# components
[xst,vsyn]../../../vlib/xlib/s7_cmt_sfs_unisim.vbom
[ghdl,isim,vsim]../../../vlib/xlib/s7_cmt_sfs_gsim.vbom
[vsyn]../../../vlib/xlib/s7_cmt_sfs_unisim.vbom
[ghdl,vsim]../../../vlib/xlib/s7_cmt_sfs_gsim.vbom
../../../vlib/genlib/clkdivce.vbom
../../../bplib/bpgen/bp_rs232_2line_iob.vbom
../../../vlib/rlink/rlink_sp2c.vbom

29
rtl/sys_gen/tst_sram/nexys4/Makefile.ise
View File

@@ -1,29 +0,0 @@
# -*- makefile-gmake -*-
# $Id: Makefile.ise 733 2016-02-20 12:24:13Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2013-09-21 534 1.0 Initial version
#
VBOM_all = $(wildcard *.vbom)
BIT_all = $(VBOM_all:.vbom=.bit)
#
include ${RETROBASE}/rtl/make_ise/xflow_default_nexys4.mk
#
.PHONY : all clean
#
all : sys_tst_sram_n4.bit
#
clean : ise_clean
rm -f $(VBOM_all:.vbom=.ucf)
#
#-----
#
include ${RETROBASE}/rtl/make_ise/generic_ghdl.mk
include ${RETROBASE}/rtl/make_ise/generic_xflow.mk
#
ifndef DONTINCDEP
include $(VBOM_all:.vbom=.dep_xst)
include $(VBOM_all:.vbom=.dep_ghdl)
endif
#

16
rtl/sys_gen/tst_sram/nexys4/sys_tst_sram_n4.ucf_cpp
View File

@@ -1,16 +0,0 @@
## $Id: sys_tst_sram_n4.ucf_cpp 643 2015-02-07 17:41:53Z mueller $
##
## Revision History:
## Date Rev Version Comment
## 2013-09-21 534 1.0 Initial version
##
NET "I_CLK100" TNM_NET = "I_CLK100";
TIMESPEC "TS_I_CLK100" = PERIOD "I_CLK100" 10.0 ns HIGH 50 %;
OFFSET = IN 10 ns BEFORE "I_CLK100";
OFFSET = OUT 20 ns AFTER "I_CLK100";
## std board
##
#include "bplib/nexys4/nexys4_pins.ucf"
#include "bplib/nexys4/nexys4_pins_cram.ucf"

5
rtl/sys_gen/tst_sram/nexys4/sys_tst_sram_n4.vbom
View File

@@ -12,8 +12,8 @@
../../../bplib/nxcramlib/nxcramlib.vhd
${sys_conf := sys_conf.vbom}
# components
[xst,vsyn]../../../vlib/xlib/s7_cmt_sfs_unisim.vbom
[ghdl,isim,vsim]../../../vlib/xlib/s7_cmt_sfs_gsim.vbom
[vsyn]../../../vlib/xlib/s7_cmt_sfs_unisim.vbom
[ghdl,vsim]../../../vlib/xlib/s7_cmt_sfs_gsim.vbom
../../../vlib/genlib/clkdivce.vbom
../../../bplib/bpgen/bp_rs232_4line_iob.vbom
../../../bplib/bpgen/sn_humanio.vbom
@@ -25,7 +25,6 @@ ${sys_conf := sys_conf.vbom}
../../../vlib/rbus/rb_sres_or_3.vbom
# design
sys_tst_sram_n4.vhd
@ucf_cpp: sys_tst_sram_n4.ucf
@xdc:../../../bplib/nexys4/nexys4_pclk.xdc
@xdc:../../../bplib/nexys4/nexys4_pins.xdc
@xdc:../../../bplib/nexys4/nexys4_pins_cram.xdc

4
rtl/sys_gen/tst_sram/nexys4/sys_tst_sram_n4.vhd
View File

@@ -1,4 +1,4 @@
-- $Id: sys_tst_sram_n4.vhd 984 2018-01-02 20:56:27Z mueller $
-- $Id: sys_tst_sram_n4.vhd 1073 2018-11-23 18:05:51Z mueller $
--
-- Copyright 2013-2017 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@@ -29,7 +29,7 @@
-- Test bench: tb/tb_tst_sram_n4
--
-- Target Devices: generic
-- Tool versions: ise 14.5-14.7; viv 2014.4-2016.4; ghdl 0.29-0.33
-- Tool versions: viv 2014.4-2017.2; ghdl 0.29-0.34 (ise 14.5-14.7 retired)
--
-- Synthesized:
-- Date Rev viv Target flop lutl lutm bram slic

33
rtl/sys_gen/tst_sram/nexys4/tb/Makefile.ise
View File

@@ -1,33 +0,0 @@
# -*- makefile-gmake -*-
# $Id: Makefile.ise 733 2016-02-20 12:24:13Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2013-09-21 534 1.0 Initial version
#
EXE_all = tb_tst_sram_n4
#
include ${RETROBASE}/rtl/make_ise/xflow_default_nexys4.mk
#
.PHONY : all all_ssim all_tsim clean
#
all : $(EXE_all)
all_ssim : $(EXE_all:=_ssim)
all_tsim : $(EXE_all:=_tsim)
#
clean : ise_clean ghdl_clean
rm -f sys_tst_sram_n4.ucf
#
#-----
#
include ${RETROBASE}/rtl/make_ise/generic_ghdl.mk
include ${RETROBASE}/rtl/make_ise/generic_xflow.mk
#
VBOM_all = $(wildcard *.vbom)
#
ifndef DONTINCDEP
include $(VBOM_all:.vbom=.dep_xst)
include $(VBOM_all:.vbom=.dep_ghdl)
include $(wildcard *.o.dep_ghdl)
endif
#

1
rtl/sys_gen/tst_sram/nexys4/tb/sys_tst_sram_n4.ucf_cpp
View File

@@ -1 +0,0 @@
../sys_tst_sram_n4.ucf_cpp

4
rtl/sys_gen/w11a/arty_bram/sys_w11a_br_arty.vbom
View File

@@ -13,8 +13,8 @@
../../../w11a/pdp11.vhd
${sys_conf := sys_conf.vhd}
# components
[xst,vsyn]../../../vlib/xlib/s7_cmt_sfs_unisim.vbom
[ghdl,isim,vsim]../../../vlib/xlib/s7_cmt_sfs_gsim.vbom
[vsyn]../../../vlib/xlib/s7_cmt_sfs_unisim.vbom
[ghdl,vsim]../../../vlib/xlib/s7_cmt_sfs_gsim.vbom
../../../vlib/genlib/clkdivce.vbom
../../../bplib/bpgen/bp_rs232_2line_iob.vbom
../../../vlib/rlink/rlink_sp2c.vbom

4
rtl/sys_gen/w11a/artys7_bram/sys_w11a_br_as7.vbom
View File

@@ -13,8 +13,8 @@
../../../w11a/pdp11.vhd
${sys_conf := sys_conf.vhd}
# components
[xst,vsyn]../../../vlib/xlib/s7_cmt_sfs_unisim.vbom
[ghdl,isim,vsim]../../../vlib/xlib/s7_cmt_sfs_gsim.vbom
[vsyn]../../../vlib/xlib/s7_cmt_sfs_unisim.vbom
[ghdl,vsim]../../../vlib/xlib/s7_cmt_sfs_gsim.vbom
../../../vlib/genlib/clkdivce.vbom
../../../bplib/bpgen/bp_rs232_2line_iob.vbom
../../../vlib/rlink/rlink_sp2c.vbom

4
rtl/sys_gen/w11a/basys3/sys_w11a_b3.vbom
View File

@@ -14,8 +14,8 @@
../../../w11a/pdp11.vhd
${sys_conf := sys_conf.vhd}
# components
[xst,vsyn]../../../vlib/xlib/s7_cmt_sfs_unisim.vbom
[ghdl,isim,vsim]../../../vlib/xlib/s7_cmt_sfs_gsim.vbom
[vsyn]../../../vlib/xlib/s7_cmt_sfs_unisim.vbom
[ghdl,vsim]../../../vlib/xlib/s7_cmt_sfs_gsim.vbom
../../../vlib/genlib/clkdivce.vbom
../../../bplib/bpgen/bp_rs232_2line_iob.vbom
../../../vlib/rlink/rlink_sp2c.vbom

4
rtl/sys_gen/w11a/cmoda7/sys_w11a_c7.vbom
View File

@@ -15,8 +15,8 @@
../../../w11a/pdp11.vhd
${sys_conf := sys_conf.vhd}
# components
[xst,vsyn]../../../vlib/xlib/s7_cmt_sfs_unisim.vbom
[ghdl,isim,vsim]../../../vlib/xlib/s7_cmt_sfs_gsim.vbom
[vsyn]../../../vlib/xlib/s7_cmt_sfs_unisim.vbom
[ghdl,vsim]../../../vlib/xlib/s7_cmt_sfs_gsim.vbom
../../../vlib/genlib/clkdivce.vbom
../../../bplib/bpgen/bp_rs232_2line_iob.vbom
../../../vlib/rlink/rlink_sp2c.vbom

29
rtl/sys_gen/w11a/nexys4/Makefile.ise
View File

@@ -1,29 +0,0 @@
# -*- makefile-gmake -*-
# $Id: Makefile.ise 733 2016-02-20 12:24:13Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2013-09-22 534 1.0 Initial version (derived from _n3 version)
#
VBOM_all = $(wildcard *.vbom)
BIT_all = $(VBOM_all:.vbom=.bit)
#
include ${RETROBASE}/rtl/make_ise/xflow_default_nexys4.mk
#
.PHONY : all clean
#
all : $(BIT_all)
#
clean : ise_clean
rm -f $(VBOM_all:.vbom=.ucf)
#
#----
#
include ${RETROBASE}/rtl/make_ise/generic_xflow.mk
include ${RETROBASE}/rtl/make_ise/generic_ghdl.mk
#
ifndef DONTINCDEP
include $(VBOM_all:.vbom=.dep_xst)
include $(VBOM_all:.vbom=.dep_ghdl)
endif
#

21
rtl/sys_gen/w11a/nexys4/sys_w11a_n4.ucf_cpp
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@@ -1,21 +0,0 @@
## $Id: sys_w11a_n4.ucf_cpp 643 2015-02-07 17:41:53Z mueller $
##
## Revision History:
## Date Rev Version Comment
## 2013-10-13 540 1.1 add pad->clk constraints
## 2013-09-22 534 1.0 Initial version
##
NET "I_CLK100" TNM_NET = "I_CLK100";
TIMESPEC "TS_I_CLK100" = PERIOD "I_CLK100" 10.0 ns HIGH 50 %;
OFFSET = IN 10 ns BEFORE "I_CLK100";
OFFSET = OUT 20 ns AFTER "I_CLK100";
## constrain pad->net clock delay
NET CLK TNM = TNM_CLK;
TIMESPEC TS_PAD_CLK=FROM PADS(I_CLK100) TO TNM_CLK 10 ns;
## std board
##
#include "bplib/nexys4/nexys4_pins.ucf"
#include "bplib/nexys4/nexys4_pins_cram.ucf"

5
rtl/sys_gen/w11a/nexys4/sys_w11a_n4.vbom
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@@ -15,8 +15,8 @@
../../../w11a/pdp11.vhd
${sys_conf := sys_conf.vbom}
# components
[xst,vsyn]../../../vlib/xlib/s7_cmt_sfs_unisim.vbom
[ghdl,isim,vsim]../../../vlib/xlib/s7_cmt_sfs_gsim.vbom
[vsyn]../../../vlib/xlib/s7_cmt_sfs_unisim.vbom
[ghdl,vsim]../../../vlib/xlib/s7_cmt_sfs_gsim.vbom
../../../vlib/genlib/clkdivce.vbom
../../../bplib/bpgen/bp_rs232_4line_iob.vbom
../../../vlib/rlink/rlink_sp2c.vbom
@@ -32,7 +32,6 @@ ${sys_conf := sys_conf.vbom}
# design
sys_w11a_n4.vhd
# constraints
@ucf_cpp: sys_w11a_n4.ucf
@xdc:../../../bplib/nexys4/nexys4_pclk.xdc
@xdc:../../../bplib/nexys4/nexys4_pins.xdc
@xdc:../../../bplib/nexys4/nexys4_pins_cram.xdc

4
rtl/sys_gen/w11a/nexys4/sys_w11a_n4.vhd
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@@ -1,4 +1,4 @@
-- $Id: sys_w11a_n4.vhd 1056 2018-10-13 16:01:17Z mueller $
-- $Id: sys_w11a_n4.vhd 1073 2018-11-23 18:05:51Z mueller $
--
-- Copyright 2013-2018 by Walter F.J. Mueller <W.F.J.Mueller@gsi.de>
--
@@ -32,7 +32,7 @@
-- Test bench: tb/tb_sys_w11a_n4
--
-- Target Devices: generic
-- Tool versions: ise 14.5-14.7; viv 2014.4-2018.2; ghdl 0.29-0.34
-- Tool versions: viv 2014.4-2018.2; ghdl 0.29-0.34 (ise 14.5-14.7 retired)
--
-- Synthesized:
-- Date Rev viv Target flop lutl lutm bram slic MHz

32
rtl/sys_gen/w11a/nexys4/tb/Makefile.ise
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@@ -1,32 +0,0 @@
# -*- makefile-gmake -*-
# $Id: Makefile.ise 733 2016-02-20 12:24:13Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2013-09-22 534 1.0 Initial version
#
EXE_all = tb_w11a_n4
#
include ${RETROBASE}/rtl/make_ise/xflow_default_nexys4.mk
#
.PHONY : all all_ssim all_tsim clean
#
all : $(EXE_all)
all_ssim : $(EXE_all:=_ssim)
all_tsim : $(EXE_all:=_tsim)
#
clean : ise_clean ghdl_clean
#
#-----
#
include ${RETROBASE}/rtl/make_ise/generic_ghdl.mk
include ${RETROBASE}/rtl/make_ise/generic_xflow.mk
#
VBOM_all = $(wildcard *.vbom)
#
ifndef DONTINCDEP
include $(VBOM_all:.vbom=.dep_xst)
include $(VBOM_all:.vbom=.dep_ghdl)
include $(wildcard *.o.dep_ghdl)
endif
#

1
rtl/sys_gen/w11a/nexys4/tb/sys_w11a_n4.ucf_cpp
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@@ -1 +0,0 @@
../sys_w11a_n4.ucf_cpp

4
rtl/sys_gen/w11a/nexys4d_bram/sys_w11a_br_n4d.vbom
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@@ -15,8 +15,8 @@
../../../w11a/pdp11.vhd
${sys_conf := sys_conf.vhd}
# components
[xst,vsyn]../../../vlib/xlib/s7_cmt_sfs_unisim.vbom
[ghdl,isim,vsim]../../../vlib/xlib/s7_cmt_sfs_gsim.vbom
[vsyn]../../../vlib/xlib/s7_cmt_sfs_unisim.vbom
[ghdl,vsim]../../../vlib/xlib/s7_cmt_sfs_gsim.vbom
../../../vlib/genlib/clkdivce.vbom
../../../bplib/bpgen/bp_rs232_4line_iob.vbom
../../../vlib/rlink/rlink_sp2c.vbom