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Code Issues Releases Wiki Activity

remove ISE build support for 7Series designs

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wfjm
2018-12-01 13:07:59 +01:00
parent 86556f767f
commit a3bf3519d9
35 changed files with 40 additions and 345 deletions
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40
rtl/bplib/nexys4/tb/Makefile.ise
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@@ -1,40 +0,0 @@
# -*- makefile-gmake -*-
# $Id: Makefile.ise 733 2016-02-20 12:24:13Z mueller $
#
# Revision History:
# Date Rev Version Comment
# 2015-02-06 643 1.2 add nexys4_cram_aif
# 2015-02-01 641 1.1 drop nexys4_fusp_aif
# 2014-07-27 545 1.0.1 make reference board configurable via XTW_BOARD
# 2013-09-21 534 1.0 Initial version
#
EXE_all = tb_nexys4_dummy tb_nexys4_cram_dummy
#
ifndef XTW_BOARD
XTW_BOARD=nexys4
endif
include ${RETROBASE}/rtl/make_ise/xflow_default_$(XTW_BOARD).mk
#
.PHONY : all all_ssim all_tsim clean
#
all : $(EXE_all)
all_ssim : $(EXE_all:=_ssim)
all_tsim : $(EXE_all:=_tsim)
#
clean : ise_clean ghdl_clean isim_clean
#
#-----
#
include ${RETROBASE}/rtl/make_ise/generic_ghdl.mk
include ${RETROBASE}/rtl/make_ise/generic_isim.mk
include ${RETROBASE}/rtl/make_ise/generic_xflow.mk
#
VBOM_all = $(wildcard *.vbom)
#
ifndef DONTINCDEP
include $(VBOM_all:.vbom=.dep_xst)
include $(VBOM_all:.vbom=.dep_ghdl)
include $(VBOM_all:.vbom=.dep_isim)
include $(wildcard *.o.dep_ghdl)
endif
#

13
rtl/bplib/nexys4/tb/nexys4_cram_dummy.ucf_cpp
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@@ -1,13 +0,0 @@
## $Id: nexys4_cram_dummy.ucf_cpp 643 2015-02-07 17:41:53Z mueller $
##
## Revision History:
## Date Rev Version Comment
## 2015-02-06 463 1.1 factor out memory
## 2013-09-21 534 1.0 Initial version
##
## std board
##
#include "bplib/nexys4/nexys4_pins.ucf"
#include "bplib/nexys4/nexys4_pins_cram.ucf"
##

1
rtl/bplib/nexys4/tb/nexys4_cram_dummy.vbom
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@@ -5,4 +5,3 @@
../../nxcramlib/nx_cram_dummy.vbom
# design
nexys4_cram_dummy.vhd
@ucf_cpp: nexys4_cram_dummy.ucf

11
rtl/bplib/nexys4/tb/nexys4_dummy.ucf_cpp
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@@ -1,11 +0,0 @@
## $Id: nexys4_dummy.ucf_cpp 534 2013-09-22 21:37:24Z mueller $
##
## Revision History:
## Date Rev Version Comment
## 2013-09-21 534 1.0 Initial version
##
## std board
##
#include "bplib/nexys4/nexys4_pins.ucf"
##

1
rtl/bplib/nexys4/tb/nexys4_dummy.vbom
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@@ -2,4 +2,3 @@
../../../vlib/slvtypes.vhd
# design
nexys4_dummy.vhd
@ucf_cpp: nexys4_dummy.ucf